CN1232059C - Methd of collecting code plate clock synchronized signal used under mobile communicatin environment - Google Patents
Methd of collecting code plate clock synchronized signal used under mobile communicatin environment Download PDFInfo
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- CN1232059C CN1232059C CNB021474761A CN02147476A CN1232059C CN 1232059 C CN1232059 C CN 1232059C CN B021474761 A CNB021474761 A CN B021474761A CN 02147476 A CN02147476 A CN 02147476A CN 1232059 C CN1232059 C CN 1232059C
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Abstract
The present invention relates to a method for extracting code plate clock synchronized signals in mobile communication environment. The method comprises: a frame pulse select module selects one frame timing pulse signal as a datum reference pulse signal from a plurality of frame timing pulse signals of pilot channels according to preset selection conditions; the phases of the reference pulse signal and local frame timing pulse signals are discriminated by a phase discriminator to generate a phase error control quantity; a loop filter responds to the error control quantity to generate a pulse control signal; NCO carries out frequency division on externally input driving clock signals according to the pulse control signal to generate a code plate clock synchronized signal; counting and frequency division are carried out on the code plate clock synchronized signal by a counting frequency divider to generate a local frame synchronized pulse signal which is input in the phase discriminator for carrying out phase discrimination with the reference pulse signal. The present invention avoids the problem that in the mobile communication environment, because of the uninterrupted variation of paths of received signals, extracted chip clock signals are not stable (disappearance or oversize dithering).
Description
Technical field
The present invention relates to a kind of method of extraction chip (chip) clock sync signal in mobile communication environment, special, relate to a kind of method that is applied in extraction chip (chip) clock sync signal in the CDMA mobile telecommunication.
Prior art
In existing mobile spread spectrum sending and receiving letter machine, the conventional method that receiver extracts the chip clock is to realize by delay lock loop (DLL).The chip clock that utilizes locking ring to extract is used to drive local pseudo-code generator, thereby guarantees the local pseudo-code that produces and receive frequency expansion sequence synchronous fully; Simultaneously, the chip clock of extraction also is used as the spread spectrum clock of sender.The foundation that frequency expansion sequence is carried out tracking lock is the autocorrelation performance correlation properties of spread-spectrum pseudo code (suppose as shown in Figure 1) of frequency expansion sequence.Fig. 1 illustrates the correlation properties of spread-spectrum pseudo code, and wherein τ represents the pseudo noise code that receives and the phase difference of local pseudo-code, and R (τ) represents the relative amplitude of both relevant peaks.As seen from Figure 1, when the pseudo noise code of reception and local pseudo-code complete matching, the correlation maximum, and both deviations are big more, correlation is more little.The size of correlation has reflected the degree of the two alignment.In order to reflect that local pseudo-code is in advance or lags behind the reception pseudo-code, usually make to receive pseudo-code and the local pseudo-code of the two-way of phase delay half-chip, the leading half-chip of phase place and carry out relevantly, two-way in advance, the correlation of hysteresis local code and the received signal value of subtracting each other gained just reflected the direction and the size of phase difference.Use this phase signal (by the autocorrelation performance decision) to go the phase place of the local sequence of closed-loop adjustment, two sequence phase differences are controlled to minimum state, promptly realized tracking thereby reach, thus output chip clock sync signal.
Delay locked loop is exactly a phase-locked loop in essence, expresses the basic comprising of track loop among Fig. 2.As shown in the figure, it mainly is made up of following components: phase discriminator (PD), loop filter (LF), voltage controlled oscillator (VCO).Phase discriminator (PD) is a phase comparison device, is used for detecting the phase difference of input signal phase place and feedback signal.The slope of phase characteristic and phase demodulation gain size also are very important, and it directly influences the basic parameter of loop.Voltage controlled oscillator (VCO) is an integrator in essence, and the chip clock that its output is extracted is used for driving local pseudo-code generator.
Yet, in mobile communication environment, the footpath of received signal is accompanied by the disappearance in some footpaths always in the variation that does not stop, there is new footpath to generate simultaneously, and the amplitude, phase place in footpath also ceaselessly changing, if the simple delay lock loop that adopts extracts the chip clock, can only carry out Dan Jing, if should disappear in the footpath, then the chip clock of Ti Quing will interrupt, if amplitude, the phase change in footpath are very fast, will cause the chip clock jitter that extracts excessive.The interruption or unusual if the chip clock that extracts also as the spread spectrum clock of transmitter, will cause transmitting.
Summary of the invention
As previously mentioned: adopt the method for a delay lock loop to extract clock merely,, can cause extracting the instability of clock owing to the variation of mobile environment.Therefore, the object of the present invention is to provide a kind of method of extracting the chip clock sync signal of in mobile environment, stablizing, be used for overcoming in actual working environment, because the continuous variation of multipath signal, stablize unified chip clock signal and the difficulty brought to extraction.
Based on this, the method that the present invention extracts stable chip clock synchronizing signal is as follows:
Tracking loop in a plurality of fingers peak of RAKE receiver follow the tracks of respectively a footpath and output to should the footpath the chip clock synchronizing signal, utilize described clock signal to count then respectively according to certain frame length, obtain a plurality of pilot channel frame timing pulse signals;
Frame pulse selects module according to predefined alternative condition, selects a frame timing pulse signal in a plurality of pilot channel frame timing pulse signals, as the reference reference pulse signal;
Phase discriminator produces quantity of phase error to this reference pulse signal and local frame timing pulse signal phase demodulation;
The described ERROR CONTROL amount of loop filter response produces pulse control signal;
The drive clock signal frequency split that numerically-controlled oscillator (NCO) is imported to external world according to described pulse control signal produces the chip clock synchronizing signal;
Frequency-dividing counter is counted frequency division to described chip clock synchronizing signal, produces local frame-synchronizing impulse signal, and imports in the described phase discriminator, with described reference pulse signal phase demodulation.
The present invention adopts under multi-path environment each is directly followed the tracks of, therefrom select suitable frame timing pulse signal as the reference benchmark, extract the scheme of chip clock by phase-locked loop, the unsettled defective of Clock Extraction of utilizing single drive signal to bring can be overcome, stable chip clock can be in mobile multipath communication environment, extracted as the reference signal.Thereby avoided in mobile communication environment and since the footpath of received signal do not stop change the problem of the chip clock signal instability that causes extracting (disappear or shake excessive).
Below in conjunction with drawings and Examples the present invention is further detailed.
Description of drawings
Fig. 1 is the schematic diagram of the autocorrelation performance of PN (pseudo noise) sign indicating number;
Fig. 2 is the basic comprising schematic diagram of track loop;
Fig. 3 is the schematic diagram of RAKE receiver basic comprising of the present invention;
Fig. 4 is the basic comprising schematic diagram of RAKE receiver finger of the present invention;
Fig. 5 is that the chip Clock Extraction that the present invention moves under the multi-path environment realizes schematic diagram;
Fig. 6 is the CHIP clock extracting circuit schematic diagram of the present invention in the WCDMA travelling carriage;
Embodiment
Represented RAKE (rake) receiver basic comprising among Fig. 3.In the mobile CDMA system, received signal generally adopts RAKE receiver to realize, as shown in the figure, dotted line encloses and partly is RAKE receiver among Fig. 3.RAKE receiver comprises a plurality of fingers peak (hereafter is " finger "), and each finger is exactly a direct sequence spread spectrum list footpath receiver.The workflow of RAKE receiver is: after the spread-spectrum signal input, under the effect of multipath, search out the time delay distribution in each footpath, each finger (list in the corresponding diagram 3 directly receives 1～N) of receiving of RAKE then, according to the time delay distribution of distributing the footpath, trace demodulation is somebody's turn to do the footpath separately, and exports the data demodulates result in this footpath.At last, the demodulation result of each finger merges according to certain rule (as high specific merging method), thereby exports unified demodulation result.
Therefore, each finger that RAKE receives, its inside constitutes, operation principle should be just the same, and Fig. 4 represents the basic comprising schematic diagram of RAKE receiver finger.Among Fig. 4, base-band input signal at first is input to correlator, finishes the spread spectrum related operation by correlator, and channel estimating is extracted the transmission characteristic of channel, be used for eliminating the influence of channel transfer characteristic for the delay equalization module, thereby realize data demodulates modulating data.Local spectrum-spreading code generator then under the chip clock sync signal that delay lock loop extracts drives, produces spreading code.In each finger that RAKE receives, all comprise a delay lock loop, it is used for producing corresponding its and receives the chip clock sync signal in footpath.Like this, if a RAKE receiver has N finger, just can produce N chip clock sync signal at most.And in the operational environment of reality, in order to guarantee reception, a RAKE receiver needs 4 finger at least.The key of problem to be solved by this invention is exactly how from this N chip clock sync signal, extracts unified chip clock sync signal.
As noted earlier: can not rely on an independent finger, with the chip clock sync signal of its output as unified chip clock sync signal.Because in the operational environment of reality, the footpath that finger followed the tracks of is constantly taking place to change, if the footpath of being followed the tracks of disappears, the chip clock sync signal of Ti Quing will be made mistakes so, can not keep stable.
Therefore, unified chip clock sync signal method is stablized in extraction provided by the present invention, is used for overcoming in actual working environment, stablizes the difficulty that unified chip clock sync signal is brought owing to the continuous variation of multipath signal to extraction.The method of concrete realization Clock Extraction is narrated hereinafter.
Each finger for RAKE receiver, in the course of the work, require pilot channel frame timing pulse signal of output, the production method of this signal is as follows: if after a certain finger starts, tracking loop among this finger is followed the tracks of a specific footpath, and output is to chip clock sync signal that should the footpath; Utilize this clock signal then, count, just can obtain the pilot channel frame timing pulse signal according to certain frame length.Like this, the variation of chip clock among this finger just directly embodies on the pilot channel frame timing pulse signal of this finger.
Therefore, after RAKE starts,, just can export N pilot channel frame timing pulse signal simultaneously if N finger work is arranged.Utilize these pilot channel frame timing pulse signals, utilize principle of phase lock loop again, just can extract the stable chip clock sync signal of output.Whole leaching process describes with reference to Fig. 5.
Fig. 5 realizes the schematic diagram that the chip clock sync signal extracts under the mobile multi-path environment.As shown in the figure, at first, select module from the pilot channel frame timing pulse signal of N figner of RAKE output, select the pilot channel frame timing pulse signal of some finger output, as the reference reference pulse signal by frame pulse.This selection can be carried out according to different principles, and as according to the most powerful path principle: promptly to follow the tracks of the energy in footpath the strongest for which finger, then selects the pilot channel frame timing pulse signal of this finger output; All right basis is the footpath principle the earliest, and promptly the footpath which finger followed the tracks of arrives the earliest, then selects the pilot channel frame timing pulse signal of this finger output.In addition, if a certain footpath disappears, the finger that then follows the tracks of this footpath quits work, and no longer exports the pilot channel frame timing pulse signal, and this finger just no longer participates in selection.And if have a new footpath to generate, then distribute a finger that it is followed the tracks of, the pilot channel frame timing pulse signal of this finger output is just participated in selection.Like this, how the footpath no matter environment causes changes, and can obtain a reference frame lock-out pulse, extracts loop for whole chip clock sync signal and uses.
Then, the pilot channel frame timing pulse signal that chooses, i.e. " reference data pulse signal " hereinafter, output to phase discriminator, carry out phase demodulation by the local frame timing pulse signal (will be described hereinafter) that frequency division produces there with by the frequency-dividing counter among the figure, generate leading or lagging phase ERROR CONTROL amount.Production method leading or the lagging phase error signal is: a fixed position after local frame synchronizing signal pulse (set time skew) produces a time benchmark lock-out pulse.The frame commutator pulse that chooses starts a counter, and the time benchmark then stops this counter synchronously.Count value that counter stops to locate and set time skew are subtracted each other.If the result is being for just, the frame synchronization that then local frame sync advance chooses, thus produce leading ERROR CONTROL amount; Otherwise, if the result is for bearing the frame synchronizing signal that then local frame synchronization lags behind and chooses, thereby generation hysteresis error controlled quentity controlled variable.Immediately, phase discriminator outputs to loop filter with above-mentioned ERROR CONTROL amount.Among the present invention, loop filter can adopt the filter of pacing up and down at random to realize.An intermediate quantity and a side-play amount are set in filter.If the intermediate quantity initial value is M, side-play amount is made as L.After leading ERROR CONTROL amount arrives, intermediate quantity is added 1, and after the arrival of hysteresis error controlled quentity controlled variable, then intermediate quantity subtracts 1.If by a series ofly add, the reducing intermediate quantity arrives M+L, then the loop filter intermediate quantity is got back to initial value M, export " adding " pulse control signal simultaneously, if and a series of operation causes the filter median is M-L, then filter is also got back to initial value M, simultaneously output " subtracting " pulse control signal.The filter of pacing up and down at random output " adding ", " subtracting " pulse control signal remove to control NCO (number controloscillator, numerically-controlled oscillator).
NCO among Fig. 5 can utilize the method for counting frequency division to realize its function.Promptly, drive a counter, carry out frequency division by a high-speed clock pulse, thus the chip clock sync signal that obtains extracting.Only this frequency-dividing counter is operation under the control of " adding ", " subtracting " pulse.When promptly " adding " the pulse arrival, counter keeps counting constant; And " subtracting " pulse is when arriving, and then counter is added a high-frequency clock cycle.Frequency divider is then according to count value, and the drive clock that inputs to it is to external world carried out frequency division, and like this, the chip clock sync signal of extraction is accelerated as required or slowed down, thereby realizes the synchronous tracking to the side of emission chip clock.
The chip clock sync signal of NCO output further arrives frequency-dividing counter and counts, and frequency division produces local frame-synchronizing impulse signal then.This frame-synchronizing impulse feeds back to phase discriminator, carries out than mutually with the reference data pulse signal that chooses.
Like this, just constitute one and be applied to phase-locked clock extraction loop complete under the mobile multi-path environment.And the final chip clock sync signal that extracts is exported by the NCO in the loop.
Fig. 6 is the preferably schematic diagram of CHIP clock sync signal extraction circuit in the WCDMA travelling carriage of the present invention; In the process of design WCDMA travelling carriage, utilize the method for narrating among the present invention to extract the chip clock sync signal, be used for driving the band spectrum modulation of up link.Concrete implementation structure as shown in Figure 6.
At first, utilize the downlink pilot frequency channel frame-synchronizing impulse of exporting in the RAKE receiver, extract the pilot channel frame timing pulse signal of loop as defeated people's clock.Most powerful path selects module to be used to realize selection to the reference data pulse among Fig. 6.In order to select the reference data pulse, need the RAKE receiver of front end to export the locking indication of frame timing pulse signal, pilot channel INTIME branch energy and each finger tracking loop of the pilot channel of each finger.Under the WCDMA system, the tracking loop in each footpath realizes that by following the tracks of pilot channel simultaneously, each finger exports a frame synchronizing signal every 10ms.Like this,,, carry out energy relatively, select the frame-synchronizing impulse of the maximum finger of energy, as the reference reference pulse to locked finger according to lock indication signal.This selection 10ms carries out once.If there is not the finger locking, then control whole loop and do not adjust, keep a stable chip clock signal output.Most powerful path is selected and can be carried out at a fixing time slot place.The method of selecting is a comparison method successively.Promptly after selecting index signal to arrive, the one finger is made as the strongest finger, and (no matter whether it locks, if non-locking, its energy is made as 0), compare with the 2nd finger energy then, if the 2nd finger energy greater than a finger, then most powerful path is the 2nd finger, otherwise most powerful path keeps a finger constant.Then, the strongest finger and the 3rd finger that stay compare, and comparison principle is constant.Carry out so successively, relatively finish up to all finger.In order to simplify the comparison control procedure, for the finger of non-locking, its energy is set to 0 and compares.Then, deliver to the loop phase discriminator with selecting the strongest most powerful path of signal energy.
The effect of phase discriminator is the position relation of the local pilot channel frame-synchronizing impulse of judgment standard frame synchronization and loop output among the figure: promptly reference frame is in advance or the reference pilot channel frame lock-out pulse that lags behind and select synchronously.If benchmark frame sync advance pilot channel frame synchronization, then output adds 1 control impuls to loop filter; Otherwise then output subtracts 1 control impuls.Relatively phase place still lags behind in advance and can realize by inserting the high-speed pulse counting method.Promptly a fixed position (set time skew) produces a time benchmark frame-synchronizing impulse after local pilot channel frame synchronization.Reference frame starts a counter synchronously, and time ratio then stops this counter synchronously than reference frame.Count value that counter stops to locate and set time skew are subtracted each other.If the result is being for just, the local pilot channel frame synchronization of benchmark frame sync advance then; Otherwise, the reference frame local pilot channel frame synchronization that lags behind synchronously then.Utilize " in advance ", " hysteresis " controlled quentity controlled variable, the running of removing the control loop filter.
Loop filter is to adopt the sequence filter of pacing up and down at random to realize.According to the WCDMA protocol requirement, the chip clock index request of extraction is as follows: each adjustment can not be greater than 1/4chip, and every 200ms adjustment amount can not be greater than 1/4chip.Therefore, must be according to this index Design loop filter parameter.The filter of pacing up and down at random output " adding ", " subtracting " control impuls remove to control NCO.
In the present embodiment, the drive clock of loop NCO adopts 8 times of chip clock signals to realize that under the WCDMA system, standard chip clock signal is 3.84MHz, so drive clock is 30.72MHz.The core of whole NCO is one 8 frequency counter.Count range is from 0～7.When pacing up and down filter output " adding " pulse control signal at random, 8 frequency division phase count values remain unchanged, and after having subtract pulse signal to arrive, count value adds one; Export high and low level according to count value then, promptly count value is 3 o'clock, the output high level, and count value is 7 o'clock, output low level, thus obtain the CHIP clock sync signal of 3.84MHz.
The chip clock sync signal of NCO output arrives CPICH (Common Pilot Channel, Common Pilot Channel) channel timing information generation module, CPICH channel timing information among the figure takes place, also be to utilize the frequency division counter principle, produce local CPICH channel frame commutator pulse, thereby carry out phase demodulation with the most powerful path frame-synchronizing impulse that chooses.Particularly, local frame synchronizing signal is according to the chip clock signal of extracting, and realizes by a secondary counter.According to the requirement of WCDMA system, design first order count range is from 0～511, and when first order count value was 511, second level counter added 1; Second level count range when second level counting equals 74, produces local frame synchronizing signal from 0～74.
Like this, just constitute one and be applied to phase-locked clock extraction loop complete under the WCDMA environment.And the final chip clock signal of extracting, by the output of the NCO in the loop, this stable chip clock signal by phase-lock technique output is as the drive clock of up link band spectrum modulation.
When the WCDMA travelling carriage is used in actual working environment, the chip clock signal extracting circuit that utilizes said method to constitute, can carry out work reliably, and stable output chip clock sync signal, the relative change rate of clock signal and absolute change rate meet the requirement of 3GPP agreement regulation fully.
More than describe specific embodiments of the invention in detail, but for the person of ordinary skill of the art, can make the variations that much do not exceed thought of the present invention and concept on this basis, so the present invention is not limited to each embodiment, should comprises that also this class changes.
Claims (4)
1. method of extracting the chip clock synchronizing signal is characterized in that may further comprise the steps:
Tracking loop in a plurality of fingers peak of RAKE receiver follow the tracks of respectively a footpath and output to should the footpath the chip clock synchronizing signal, utilize described clock signal to count then respectively according to certain frame length, obtain a plurality of pilot channel frame timing pulse signals;
Frame pulse selects module according to predefined alternative condition, selects a frame timing pulse signal in a plurality of pilot channel frame timing pulse signals, as the reference reference pulse signal;
Phase discriminator produces quantity of phase error to this reference pulse signal and local frame timing pulse signal phase demodulation;
The described ERROR CONTROL amount of loop filter response produces pulse control signal;
The drive clock signal frequency split that numerically-controlled oscillator (NCO) is imported to external world according to described pulse control signal produces the chip clock synchronizing signal;
Frequency-dividing counter is counted frequency division to described chip clock synchronizing signal, produces local frame-synchronizing impulse signal, and imports in the described phase discriminator, with described reference pulse signal phase demodulation.
2. the method for extraction chip clock synchronizing signal as claimed in claim 1 is characterized in that, described reference data pulse signal is selected according to the most powerful path principle.
3. the method for extraction chip clock synchronizing signal as claimed in claim 1 is characterized in that, described reference data pulse signal is selected according to footpath principle the earliest.
4. the method for extraction chip clock synchronizing signal as claimed in claim 1 is characterized in that described loop filter is one and selects to pace up and down filter at random.
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| CNB021474761A CN1232059C (en) | 2002-11-01 | 2002-11-01 | Methd of collecting code plate clock synchronized signal used under mobile communicatin environment |
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| CNB021474761A CN1232059C (en) | 2002-11-01 | 2002-11-01 | Methd of collecting code plate clock synchronized signal used under mobile communicatin environment |
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| CN101567871B (en) * | 2008-04-21 | 2011-08-03 | 电信科学技术研究院 | Method and device for improving ACLR index |
| CN107359901B (en) * | 2017-08-03 | 2019-05-07 | 中国电子科技集团公司第五十四研究所 | A kind of synchronization timing device and method for the incoherent band spectrum modulation of satellite channel |
| WO2020007451A1 (en) * | 2018-07-03 | 2020-01-09 | Huawei Technologies Co., Ltd. | Time interleaving code division multiple access (cdma) system for clock recovery |
| CN112687232B (en) * | 2019-10-18 | 2022-06-10 | 北京小米移动软件有限公司 | Dimming method and device of OLED display screen, electronic equipment and storage medium |
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