CN101517655A - A secure non-volatile memory device and a method of protecting data therein - Google Patents
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- CN101517655A CN101517655A CNA2007800357731A CN200780035773A CN101517655A CN 101517655 A CN101517655 A CN 101517655A CN A2007800357731 A CNA2007800357731 A CN A2007800357731A CN 200780035773 A CN200780035773 A CN 200780035773A CN 101517655 A CN101517655 A CN 101517655A
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 238000009826 distribution Methods 0.000 description 12
- 238000003860 storage Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 9
- 238000001514 detection method Methods 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000013500 data storage Methods 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 239000000523 sample Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
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Abstract
The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and - a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1', D1'') into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.
Description
Technical field
The present invention relates to a kind of nonvolatile semiconductor memory member.The invention still further relates to a kind of method that data in the nonvolatile semiconductor memory member are protected.
Background technology
Nonvolatile semiconductor memory member (ROM, PROM, EPROM, EEPROM etc.) is well-known.And in their application of being widely used in wherein needing data are protected, for example domestic. applications, move and use, and set-top box (pay TV, satellite television etc.).In the many decades, developed the whole bag of tricks that the data on the nonvolatile semiconductor memory member are attacked in the past:
The positive reverse process that combines with optical imagery;
The back side reverse process that combines with the voltage contrast imaging;
Little detection analysis;
UV handles;
Software attacks;
FIB (cutting and sensing);
Or the like.
Usually, thought that picture is very safe based on the storer of floating boom with based on the nonvolatile memory of the storer of ONO for these attacks.Yet recently, people such as C.De Nardi are at Microelectronics Reliability, and Vol.45 (205) among the p1514-1519, has announced a kind of method that can obtain data from eeprom memory spare.This publication has been announced the method for " scene " programmed charges in a kind of EEPROM of measurement device.Use comes direct detection floating boom electromotive force based on the technology (electric power microscope (EFM) and scanning Kai Erwen probe microscope (SKPM)) of electronics AFM.Preparation method not only has been discussed detection method also has been discussed.In that several nanometers enter floating boom/oxide interface and the sample of data discharges can not to be prepared ratio detection technology itself more not crucial from the back side.This method is also referred to as the back-side voltage contrast imaging.
Therefore, the shortcoming of known nonvolatile semiconductor memory member is that the data of storing thereon no longer are safe enoughs for external attack.
Summary of the invention
The purpose of this invention is to provide a kind of nonvolatile semiconductor memory member safer for external attack.Another object of the present invention provides and a kind ofly prevents that the data in the nonvolatile semiconductor memory member are subjected to the method for external attack.
The present invention is limited by independent claims.Dependent claims defines advantageous embodiment.
Provide a kind of nonvolatile semiconductor memory member to realize purpose of the present invention, described nonvolatile semiconductor memory member comprises:
Input end is used for providing the external data that will be stored in nonvolatile semiconductor memory member;
First non-volatile memory modules and second non-volatile memory modules, first non-volatile memory modules and second non-volatile memory modules are arranged on the single nude film, wherein first non-volatile memory modules is different types with the easy property of second non-mistake memory module, thereby in order to obtain data from first non-volatile memory modules and second non-volatile memory modules, need incompatible external attack technique, external data is stored in first non-volatile memory modules and two modules of second non-volatile memory modules in a kind of mode of distribution.
Fundamental of the present invention is that nonvolatile semiconductor memory member comprises two memory modules that store external data at least.The result of this measure is in order to obtain the external data of original stored on memory device, must obtain this data from first non-volatile memory modules and two modules of second non-volatile memory modules.
Non-volatile memory cells generally includes the have electric charge storage region transistor of (electric charge capture layer in floating boom, the monox-silicon-nitride and silicon oxide device etc.).Each external attack technique can comprise reverse process (reverse engineering) step, so that can visit the electric charge storage region of memory module and be (perhaps from positive or from the back side) how to connect so that determine storage unit; Also comprise the research/detection/observation step that is used for determining electric charge on the electric charge storage region.Essential characteristic of the present invention is that first non-volatile memory modules requires with different incompatible external attack technique with second non-volatile memory modules.Because the above-mentioned feature according to non-volatile device of the present invention is difficult to obtain the data of original stored on nonvolatile semiconductor memory member.
In the advantageous embodiment according to nonvolatile semiconductor memory member of the present invention, the first of a word of external data is deposited in first non-volatile memory modules, and the second portion of this word of external data is deposited in second non-volatile memory modules.In the alternative advantageous embodiment according to nonvolatile semiconductor memory member of the present invention, first word of external data is deposited in first non-volatile memory modules, and second word of external data deposited in second non-volatile memory modules.Two embodiment have guaranteed not only to need to know the data from first non-volatile memory modules in order to obtain the data of original stored in nonvolatile semiconductor memory member, have also needed to know the data from second non-volatile memory modules.
In a specific embodiment according to nonvolatile semiconductor memory member of the present invention, the layout type of first non-volatile memory modules and second non-volatile memory modules interlocks.The staggered layout of first non-volatile memory modules and second non-volatile memory modules makes more difficultly carries out reverse engineering to two modules on the same nude film.
In another embodiment according to nonvolatile semiconductor memory member of the present invention, first non-volatile memory modules is polysilicon fuse (poly fuse) storer, and second non-volatile memory modules is floating boom (floating gate) storer.This combination of the type of memory on the single nude film makes it possible to very well resist external attack, this is because the polysilicon fuse storer need carry out reverse engineering from the front of device, and floating-gate memory need carry out reverse engineering from the back side, so that can visit floating boom.Importantly, note removing material from front and back respectively during the reverse engineering step, this makes may carry out reverse engineering to two memory modules on the same nude film hardly simultaneously.
Preferably, polysilicon fuse storer and floating-gate memory use same polysilicon layer physically, and this makes and more difficultly simultaneously two memory modules to be carried out reverse engineering.When the hacker attempted to obtain data from first memory module (the molten silk of polysilicon storer), the data of obtaining on second memory module (floating-gate memory) by optical imagery were prevented from.This is because the optical imagery of polysilicon fuse storer need carry out the front to nude film and remove layer, and the back-side voltage contrast imaging of nonvolatile memory need be carried out the back side to nude film and removes layer.And, from two being exceedingly difficult at least, or even impossible in the face of nude film removes layer.Similarly, attempt to go layer to come in fact can not continue to obtain memorizer information when floating-gate memory obtains data as the hacker from the polysilicon fuse storer of same nude film by the back side.
In another improvement embodiment according to nonvolatile semiconductor memory member of the present invention, the bit line of at least one in first non-volatile memory modules and second non-volatile memory modules is by scramble.The bit line scramble meaned in the mode of certain type " similar multi-layer intercrossed " arrange bit line.Utilize this measure, make the reverse engineering of being undertaken become very difficult thus by the optical observation interconnection structure.
In a specific embodiment according to nonvolatile semiconductor memory member of the present invention, nonvolatile memory also comprises:
The 3rd non-volatile memory modules, the 3rd non-volatile memory modules is arranged on the nude film identical with second non-volatile memory modules with first non-volatile memory modules, wherein the 3rd non-volatile memory modules belongs to different types with first non-volatile memory modules and second non-volatile memory modules, thereby for from first non-volatile memory modules, obtaining data in second non-volatile memory modules and the 3rd non-volatile memory modules needs incompatible external attack technique, with distribution mode with external data storage to first non-volatile memory modules, in second non-volatile memory modules and the 3rd non-volatile memory modules.Provide more memory module and the distribution external data has increased the reverse engineering parameter that the hacker need determine on more memory module number, thereby make the external attack to this device become more difficult.
The invention still further relates to a kind of method of protecting the data in the nonvolatile semiconductor memory member, this method may further comprise the steps:
The external data that will be stored in the nonvolatile semiconductor memory member is provided, described nonvolatile semiconductor memory member comprises first non-volatile memory modules and second non-volatile memory modules, first non-volatile memory modules and second non-volatile memory modules are arranged on the single nude film, wherein first non-volatile memory modules belongs to different types with second non-volatile memory modules, thereby, need incompatible a plurality of external attack technique in order from first non-volatile memory modules and second non-volatile memory modules, to obtain data;
With distribution mode with external data storage in first non-volatile memory modules and second non-volatile memory modules.
The method according to this invention provides a kind of method that makes things convenient for of protecting data in the nonvolatile semiconductor memory member.
Description of drawings
Any supplementary features can be combined, and any supplementary features and any aspect can be made up.Other advantage is obvious to those skilled in the art.Can under the situation of the scope that does not break away from claim of the present invention, make various variants and modifications.Therefore, should be expressly understood that this instructions is exemplary rather than will limits the scope of the invention.
Now will by describing how to implement the present invention in the mode of example with reference to the accompanying drawings.Wherein:
Fig. 1 shows first embodiment according to nonvolatile semiconductor memory member of the present invention;
Fig. 2 shows first kind of mode on DATA DISTRIBUTION to two memory module;
Fig. 3 shows the second way on DATA DISTRIBUTION to two memory module;
Fig. 4 shows second embodiment according to nonvolatile semiconductor memory member of the present invention;
Fig. 5 to Fig. 8 shows four kinds of different modes that memory module is interlocked.
Embodiment
In Fig. 1, schematically show nonvolatile semiconductor memory member according to first embodiment of the invention.In this embodiment, via the input end (not shown) external data D is offered nonvolatile semiconductor memory member.Nonvolatile semiconductor memory member comprises first non-volatile memory modules 100 and second non-volatile memory modules 200, first non-volatile memory block 100 and second non-volatile memory block 200 belong to dissimilar, thereby, need incompatible multiple external attack technique in order from them, to obtain data.
Store external data D1 into first non-volatile memory modules 100 and second non-volatile memory modules 200 in the two with distribution mode, the D1 ' of first is stored on first non-volatile memory modules 100, second portion D1 " be stored on second non-volatile memory modules 200.First non-volatile memory modules 100 and second non-volatile memory modules 200 are positioned on the same nude film 10, and this is an essential characteristic of the present invention.Two non-volatile memory modules 100,200 required external attack technique are incompatible, and this feature provides the so-called interlocking LCK between two non-volatile memory modules 100,200.Therefore, be difficult to from first non-volatile memory modules 100 and second non-volatile memory modules 200, obtain data simultaneously.
Fig. 2 shows external data D1 is distributed to first kind of mode on two memory modules 100,200.In this method, from the word W of external data D1
n, W
N+1Be divided into two part D1 ', D1 ".Original word W
n, W
N+1The W1 of first
n, W1
N+1Be stored in first non-volatile memory modules 100.Original word W
n, W
N+1Second portion W2
n, W2
N+1Be stored in second non-volatile memory modules 200.In this example, original word comprises 8, yet in actual design, any amount of position all is feasible.And in this example, original word is distributed on two memory modules 100,200 fifty-fifty, this means in each memory module to distribute 4.In actual design, other distribution proportions also are feasible, for example distribute 6 in first memory module 100, distribute 2 in second memory module, perhaps other any distribution proportions.
Fig. 3 shows external data D1 is distributed to the second way on two memory modules 100,200.In this method, not having will be from the word W of external data D1
n, W
N+1Cut apart.But with original word W
n, W
N+1Store into respectively in an alternating manner in first non-volatile memory modules 100 and second non-volatile memory modules 200.Original word W
n(as word W1
n) be stored in first non-volatile memory modules 100 original word W
N+1(as word W2
n) be stored in second non-volatile memory modules 200.In this example, original word comprises 8, yet any amount of position all is feasible in the actual design.And in this example, original word is distributed on two memory modules 100,200 fifty-fifty, this means that the quantity of the word in each memory module is identical.In actual design, other distribution proportions also are feasible, for example distribute 3 words and the ratio of 1 word that distributes in second memory module 200 in first memory module 100, perhaps other any distribution proportions.
In Fig. 4, schematically show nonvolatile semiconductor memory member according to second embodiment of the invention.Be according to this embodiment of nonvolatile semiconductor memory member of the present invention and the difference of first embodiment: nonvolatile semiconductor memory member also comprises the 3rd non-volatile memory modules 300.Now, external data D1 comprises the D1 ' of first that is stored on first non-volatile memory modules 100, is stored in the second portion D1 on second non-volatile memory modules 200 ", and be stored in third part D1 ' on the 3rd non-volatile memory modules 300 ".External data D1 is distributed on a plurality of non-volatile memory modules 100,200,300 provides more powerful interlocking LCK, thereby added security is provided.
In the above-described embodiments, in some examples, word can comprise 16,32,64,128.But in theory, in all embodiments, word can have random length.
It is important should be noted that external data may also be a data encrypted.When this nonvolatile semiconductor memory member was employed, this measure had resisted the attack technology of similar IC pin detection and so on.
In the concrete example according to first embodiment of nonvolatile semiconductor memory member of the present invention, product is paid close attention to " the product X " of the single chip secure of making in the 90nm technology.This technology be a feature with the silicification polysilicon fuse that will be used as nonvolatile memory.In " product X ", this type of memory is used to first non-volatile memory modules 100.This technology is a feature with the floating-gate memory as nonvolatile memory also.In " product X ", this type of memory is used to second non-volatile memory modules.The Physical layer of the floating boom in second non-volatile memory modules 200 is fabricated on the Physical layer identical with silicification polysilicon fuse in first non-volatile memory modules 100.This has guaranteed the firm interlock LCK between first non-volatile memory modules and second non-volatile memory modules.When the content of polysilicon fuse memory module 100 was attacked, the content of another floating boom memory module 200 was damaged; Vice versa.In " product X ", first non-volatile memory modules 100 comprises the part of DieID sign indicating number, and second non-volatile memory modules 200 comprises other parts." product X " also can comprise may be from the supplier ID of the company of UPC or KPN and so on, and wherein supplier ID is distributed on first non-volatile memory modules 100 and second non-volatile memory modules, 200 these two memory modules.And on first non-volatile memory modules 100 and second non-volatile memory modules 200, all provide Customer ID.Sometimes, need be distributed to public keys on first non-volatile memory modules 100 and second non-volatile memory modules 200 equally.Sometimes, this public keys is interim.
Further the another kind of mode of improving the Data Protection on the nonvolatile semiconductor memory member is that the layout of memory module is interlocked.Fig. 5 to Fig. 8 shows the different schemes that two memory modules are interlocked.Fig. 5 shows first non-volatile memory modules 100 and second non-volatile memory modules 200, and wherein first non-volatile memory modules 100 is disposed in second non-volatile memory modules 200.Fig. 6 shows another kind of scheme, and wherein the storage unit 100 ' of first non-volatile memory modules 100 is disperseed or is distributed in the layout of second non-volatile memory modules 200.Fig. 7 shows the third scheme, has wherein alternately arranged the storage unit 100 ' of first non-volatile memory modules 100 and the storage unit 200 ' of second non-volatile memory modules 200 on column direction.When memory module 100,200 had similar size, this scheme was to make the people interested.Fig. 8 shows the 4th kind of scheme, wherein the storage unit 100 ' of equal arranged alternate first non-volatile memory modules 100 and the storage unit 200 ' of second non-volatile memory modules 200 on line direction and column direction.This scheme aims to provide best interlocking.But when the storage unit 200 ' of the storage unit 100 ' of first non-volatile memory modules 100 and second non-volatile memory modules 200 had similar size, this scheme was just the most effective.
The optional mode of further improving the Data Protection on the nonvolatile semiconductor memory member is to implement bit line scramble (bit-line scrambling).The bit line scramble is a kind of part " encryption ", thereby logical bit and physical bit are by scramble.Example is to utilize multilayer wiring in the technology by the mode of " similar multi-layer intercrossed ", thereby makes equal different fully with other byte/word of bit line of each byte (or word) row.In this way, physically scramble logical bit, become very difficult thereby it is sought track.For example, the byte behind 3 Bit Shifts may become: the position 3, the position 4, the position 5, the position 6, the position 7, the position 0, the position 1, the position 2 (rather than the position 0, the position 1 ... and the mirror image byte may have the position order of position 7, position 6, position 5, position 4, position 3, position 2, position 1, position 0 position 7).In the enforcement of reality, scramble is the combination of displacement, mirror image, exchange (swapping) etc.The feasible reverse engineering by means of optical detection of bit line scramble becomes very difficult.The bit line scramble can combine with storer is staggered.
Therefore, the invention provides a kind of nonvolatile semiconductor memory member safer for external attack technique.An importance of the present invention is the interlocking of two or more memory modules.Those skilled in the art become known for the non-volatile memory technologies among the embodiment.Those skilled in the art also understand the operation of nonvolatile memory and integrated.Inventor's thought is: therefore the ingenious combination of the more than one storer on single nude film and the integrated good interlocking that provides data provide the good guarantee that prevents external attack.The present invention can be used in the various application, for example: identification application, domestic. applications, the mobile application and set-top box (pay TV, satellite television etc.).
The present invention also provides a kind of method that data in the nonvolatile semiconductor memory member are protected, and described method comprises the steps:
The external data that will be stored in the nonvolatile semiconductor memory member is provided, nonvolatile semiconductor memory member comprises first non-volatile memory modules and second non-volatile memory modules, first non-volatile memory modules and second non-volatile memory modules are arranged on the single nude film, wherein first non-volatile memory modules belongs to different types with second non-volatile memory modules, thereby needs incompatible multiple external attack technique in order to obtain data from first non-volatile memory modules and second non-volatile memory modules;
With distribution mode with external data storage in first non-volatile memory modules and second non-volatile memory modules.
The advantage of this method is identical with improvement with the advantage of above-mentioned memory device with improvement.
Described the present invention, but the present invention is not limited to these specific embodiments, but only is defined by the claims with reference to specific embodiment and relevant drawings.Any reference number in the claim all should not be interpreted as the restriction to protection domain.Described accompanying drawing only is schematically, rather than restrictive.In the accompanying drawing, for purposes of illustration, some size of component may be exaggerated, perhaps not drawn on scale.Employed term " comprises " existence of not getting rid of other element or step in this instructions and the claim.Remove nonspecific statement, otherwise the definite article or the indefinite article (for example " " or " a kind of ") that use comprise plural noun when the single noun of indication.
And the term first, second, third, etc. in instructions and the claim are used to like is distinguished, but not are used for description order or sequential.The term that it should be understood that such use can exchange in appropriate circumstances, and embodiments of the invention described herein can be according to other sequential operation except order described herein.
When using " row " and " OK ", can employed speech " row " and " OK " be exchanged without departing from the scope of the invention.
Claims (9)
1. nonvolatile semiconductor memory member, it comprises:
Input end is used to provide the external data that will be stored on the nonvolatile semiconductor memory member (D1);
First non-volatile memory modules (100) and second non-volatile memory modules (200), first non-volatile memory modules (100) and second non-volatile memory modules (200) are arranged on the single nude film (10), wherein first non-volatile memory modules (100) belongs to different types with second non-volatile memory modules (200), thereby in order from first non-volatile memory modules (100) and second non-volatile memory modules (200), to obtain data, need incompatible a plurality of external attack technique, external data (D1) stores in first non-volatile memory modules (100) and second non-volatile memory modules (200) in the mode that distributes (D1 ', D1 ").
2. nonvolatile semiconductor memory member according to claim 1, the wherein word (W of external data (D1)
n, W
N+1) first (D1 ') be stored in first non-volatile memory modules (100) and the word (W of external data (D1)
n, W
N+1) second portion (D1 ") be stored in second non-volatile memory modules (200).
3. nonvolatile semiconductor memory member according to claim 1 and 2, wherein first word (W of external data (D1)
n) be stored in first non-volatile memory modules (100), and second word (W of external data (D1)
N+1) be stored in second non-volatile memory modules (200).
4. according to the described nonvolatile semiconductor memory member of arbitrary claim in the claim 1 to 3, wherein the layout type of first non-volatile memory modules (100) and second non-volatile memory modules (200) interlocks.
5. according to one of aforesaid right requirement described nonvolatile semiconductor memory member, wherein first non-volatile memory modules (100) is the polysilicon fuse storer, and second non-volatile memory modules (200) is a floating-gate memory.
6. nonvolatile semiconductor memory member according to claim 5, wherein polysilicon fuse storer (100) uses and the identical polysilicon layer of floating-gate memory (200) physically.
7. according to one of aforesaid right requirement described nonvolatile semiconductor memory member, wherein the bit line at least one memory module in first non-volatile memory modules (100) and second non-volatile memory modules (200) carries out scramble.
8. according to one of aforesaid right requirement described nonvolatile semiconductor memory member, wherein said nonvolatile semiconductor memory member also comprises:
The 3rd non-volatile memory modules (300), described the 3rd non-volatile memory modules (300) is arranged on the single nude film (10) identical with second non-volatile memory modules (200) with first non-volatile memory modules (100), wherein the 3rd non-volatile memory modules (300) belongs to different types with first non-volatile memory modules (100) and second non-volatile memory modules (200), thereby for from first non-volatile memory modules (100), obtain data in second non-volatile memory modules (200) and the 3rd non-volatile memory modules (300), need incompatible multiple external attack technique, with the mode that distributes (D1 ', D1 ", D1 ' ") store external data (D1) into first non-volatile memory modules (100), in second non-volatile memory modules (200) and the 3rd non-volatile memory modules (300).
9. method that the data in the nonvolatile semiconductor memory member are protected, this method comprises the steps:
The external data that will be stored in the nonvolatile semiconductor memory member (D1) is provided, described nonvolatile semiconductor memory member comprises first non-volatile memory modules (100) and second non-volatile memory modules (200), first non-volatile memory modules (100) and second non-volatile memory modules (200) are arranged on the single nude film (10), wherein first non-volatile memory modules (100) belongs to different types with second non-volatile memory modules (200), thereby, need incompatible multiple external attack technique in order from first non-volatile memory modules (100) and second non-volatile memory modules (200), to obtain data;
In the mode that distributes (D1 ', D1 ") external data (D1) is stored in first non-volatile memory modules (100) and second non-volatile memory modules (200).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP06121567A EP1906413A1 (en) | 2006-09-29 | 2006-09-29 | A secure non-volatile memory device and a method of protecting data therein |
| EP06121567.9 | 2006-09-29 | ||
| PCT/IB2007/053923 WO2008038243A1 (en) | 2006-09-29 | 2007-09-27 | A secure non-volatile memory device and a method of protecting data therein |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101517655A true CN101517655A (en) | 2009-08-26 |
| CN101517655B CN101517655B (en) | 2012-12-19 |
Family
ID=37775233
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200780035773.1A Active CN101517655B (en) | 2006-09-29 | 2007-09-27 | A secure non-volatile memory device and a method of protecting data therein |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7907447B2 (en) |
| EP (2) | EP1906413A1 (en) |
| JP (1) | JP2010505213A (en) |
| CN (1) | CN101517655B (en) |
| WO (1) | WO2008038243A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412235A (en) * | 2010-09-02 | 2012-04-11 | 佳能株式会社 | Semiconductor integrated circuit device |
| JP2017107409A (en) * | 2015-12-10 | 2017-06-15 | 日本電信電話株式会社 | Sensor repeating device |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009157515A (en) * | 2007-12-25 | 2009-07-16 | Toshiba Corp | Semiconductor memory controller and semiconductor memory |
| EP2369127A1 (en) * | 2010-03-09 | 2011-09-28 | Sandvik Intellectual Property AB | A rock drill bit, a drilling assembly and a method for percussive rock drilling |
| JP5911456B2 (en) * | 2012-06-27 | 2016-04-27 | 日本電波工業株式会社 | Electronics |
| RU2527758C2 (en) * | 2012-10-22 | 2014-09-10 | Федеральное государственное унитарное предприятие "18 Центральный научно-исследовательский институт" Министерства обороны Российской Федерации | Method for concealed storage of confidential data in secure non-volatile memory and device therefor |
| KR102687192B1 (en) * | 2019-02-18 | 2024-07-19 | 삼성전자주식회사 | A memory device and system |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62121979A (en) * | 1985-11-22 | 1987-06-03 | Mitsubishi Electric Corp | Integrated circuit memory |
| FR2599176A1 (en) * | 1986-05-23 | 1987-11-27 | Eurotechnique Sa | MEMORY DEADLY PROGRAMMABLE ELECTRICALLY |
| JPS63115252A (en) * | 1986-11-04 | 1988-05-19 | Hitachi Ltd | Microcomputer constituting method |
| JP3210324B2 (en) * | 1990-09-18 | 2001-09-17 | 富士通株式会社 | Semiconductor device |
| JPH04370969A (en) * | 1991-06-19 | 1992-12-24 | Fujitsu Ltd | Semiconductor integrated circuit |
| JPH05275657A (en) * | 1992-03-26 | 1993-10-22 | Toshiba Corp | Semiconductor memory device |
| JPH06187246A (en) * | 1992-12-22 | 1994-07-08 | Kawasaki Steel Corp | Programmable logic device and its writer |
| US6515906B2 (en) | 2000-12-28 | 2003-02-04 | Intel Corporation | Method and apparatus for matched-reference sensing architecture for non-volatile memories |
| EP1261241A1 (en) * | 2001-05-17 | 2002-11-27 | Shipley Co. L.L.C. | Resistor and printed wiring board embedding those resistor |
| US6608498B2 (en) * | 2001-06-20 | 2003-08-19 | Koninklijke Philips Electronics N.V. | Method for characterizing an active track and latch sense-amp (comparator) in a one time programmable (OTP) salicided poly fuse array |
| JP2003196158A (en) * | 2001-12-26 | 2003-07-11 | Matsushita Electric Ind Co Ltd | Nonvolatile semiconductor storage device |
| US6687154B2 (en) * | 2002-02-25 | 2004-02-03 | Aplus Flash Technology, Inc. | Highly-integrated flash memory and mask ROM array architecture |
| WO2004070730A1 (en) * | 2003-01-29 | 2004-08-19 | Aplus Flash Technology, Inc. | A novel highly-integrated flash memory and mask rom array architecture |
| JP2005108304A (en) * | 2003-09-29 | 2005-04-21 | Toshiba Corp | Semiconductor memory and its control method |
-
2006
- 2006-09-29 EP EP06121567A patent/EP1906413A1/en not_active Ceased
-
2007
- 2007-09-27 US US12/443,528 patent/US7907447B2/en active Active
- 2007-09-27 WO PCT/IB2007/053923 patent/WO2008038243A1/en active Application Filing
- 2007-09-27 JP JP2009529834A patent/JP2010505213A/en not_active Ceased
- 2007-09-27 CN CN200780035773.1A patent/CN101517655B/en active Active
- 2007-09-27 EP EP07826559A patent/EP2074629B1/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412235A (en) * | 2010-09-02 | 2012-04-11 | 佳能株式会社 | Semiconductor integrated circuit device |
| US8878551B2 (en) | 2010-09-02 | 2014-11-04 | Canon Kabushiki Kaisha | Semiconductor integrated circuit device |
| CN102412235B (en) * | 2010-09-02 | 2015-04-29 | 佳能株式会社 | Semiconductor integrated circuit device |
| JP2017107409A (en) * | 2015-12-10 | 2017-06-15 | 日本電信電話株式会社 | Sensor repeating device |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1906413A1 (en) | 2008-04-02 |
| WO2008038243A1 (en) | 2008-04-03 |
| EP2074629A1 (en) | 2009-07-01 |
| US7907447B2 (en) | 2011-03-15 |
| EP2074629B1 (en) | 2012-10-24 |
| US20100002511A1 (en) | 2010-01-07 |
| JP2010505213A (en) | 2010-02-18 |
| CN101517655B (en) | 2012-12-19 |
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