JP2007227498A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which an integrated circuit device can be protected against machining or alteration by means of an FIB from the backside of the device. <P>SOLUTION: Backside shield wiring 16 is formed on a semiconductor substrate 13 to cover the lower part of a protection integrated circuit region 14. A pattern generation circuit 21 connected with one end of the backside shield wiring, and a pattern detection circuit 24 connected with the other end of the backside shield wiring 16 and the pattern generation circuit 21 are formed in the protection integrated circuit region 14. An arbitrary pattern signal generated from the pattern generation circuit 21 is inputted to one end of the backside shield wiring 16 and the pattern detection circuit 24 where coincidence/noncoincidence of a signal inputted from the pattern generation circuit 21 and a pattern signal inputted through the backside shield wiring 16 is detected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and more particularly, to a semiconductor integrated circuit device provided with a shield capable of preventing attacks such as external observation, analysis, unauthorized reading, processing, and data alteration on the integrated circuit. And a manufacturing method thereof.

  A security LSI such as a smart card that holds confidential information requires a countermeasure for preventing various attacks from an attacker, so-called tamper resistant technology. As one of the tamper resistance techniques, there are reverse engineering, probing, shield techniques for combating physical attacks such as laser cutters and FIB (Focused Ion Beam).

  In a semiconductor integrated circuit device having a conventional shield, an aluminum layer is provided above the integrated circuit so as to cover the integrated circuit portion of the IC chip, thereby preventing analysis inside the integrated circuit by observation from above. (For example, refer to Patent Document 1).

Also, a protective film provided on the integrated circuit, called at least one “passivation layer”, which prevents the static internal signal means of the integrated circuit from being observed by an electron microscope, is provided on the integrated circuit. In order to detect whether the surface is optimally monitored, a meandering metal wire is provided under the protective film so as to cover the surface of the integrated circuit, a pulse signal is passed through the metal wire, and a count value from the pulse signal is provided. In some cases, the presence of the protective film is detected by comparing the value with a reference value (for example, see Patent Document 2).
Japanese Patent No. 3048429 (page 5, FIG. 1) Japanese Patent Laid-Open No. 9-134961 (first page, FIG. 1)

  However, in the conventional semiconductor integrated circuit device, since the shield is provided only only above the integrated circuit, there are insufficient measures to prevent attacks such as processing and falsification from below the integrated circuit, that is, from the back surface of the chip. There was a problem.

  Also, in recent years, techniques for performing analysis from the back surface of an integrated circuit have been improved. In such analysis technology, for example, processing is performed from the back surface of a chip using FIB, cutting of wiring inside the integrated circuit, drawing of wiring, Alternatively, since connection between wirings can be performed, information such as circuit information, memory data, and operation signals in the integrated circuit can be easily obtained and tampered with them.

  The present invention has been made to solve the above-described problems, and a semiconductor integrated circuit device capable of protecting an integrated circuit against attacks such as processing and tampering by FIB from the back surface of the chip, and its An object is to provide a manufacturing method.

  In order to solve the above problems, a semiconductor integrated circuit device according to the present invention is formed with a semiconductor substrate, an integrated circuit provided on the semiconductor substrate, and a well on the semiconductor substrate so as to cover a lower portion of the integrated circuit. One or a plurality of back shield wirings, a back shield wiring pattern generation circuit for generating an arbitrary pattern signal connected to one end of the back shield wiring, and the back shield wiring pattern generation circuit A back shield wiring pattern detection circuit connected via a reference signal line different from the back shield wiring, and the back shield wiring pattern generation circuit includes the generated pattern. The signal is input to the back shield wiring pattern detection circuit via the back shield wiring and the reference signal line, Face shield interconnection pattern detecting circuit is for detecting a signal input through the back surface shield wire, the match / mismatch of the input signal through the reference signal line.

  Thereby, it is possible to make it difficult to attack from the back surface of the integrated circuit, such as processing or falsification by FIB or the like, and as a result, the integrated circuit can be protected. Further, since the back shield wiring is formed of a well, the shape of the back shield wiring cannot be observed with a microscope, and there is an effect that resistance to tampering with the back shield wiring is enhanced.

  Furthermore, the semiconductor integrated circuit device of the present invention is connected to one or more surface shield wirings formed on the surface of the integrated circuit so as to cover the upper side of the integrated circuit and one end of the surface shield wiring. A surface generation pattern generating circuit for generating an arbitrary pattern signal and a surface connected to the pattern generation circuit for the surface shield wiring via a reference signal line different from the surface shield wiring and the surface shield wiring A pattern detection circuit for shield wiring, and the pattern generation circuit for surface shield wiring transmits the generated pattern signal to the pattern detection circuit for surface shield wiring via the surface shield wiring and the reference signal line. The surface shield wiring pattern detection circuit inputs the signal input via the surface shield wiring. When, and detects a match / mismatch of the input signal through the reference signal line.

  Thereby, there is an effect that the integrated circuit can be protected against attacks from the surface of the integrated circuit, such as microscopic observation, processing by the FIB, or alteration.

  The semiconductor integrated circuit device according to the present invention includes a semiconductor substrate, an integrated circuit provided on the semiconductor substrate, and a single well formed on the semiconductor substrate so as to cover a lower portion of the integrated circuit, or A plurality of back shield wires, one or more surface shield wires formed on the surface of the integrated circuit so as to cover the top of the integrated circuit, one end of the back shield wire, and the surface shield wires A pattern generation circuit for generating an arbitrary pattern signal connected to one end of the pattern, and a connection to the pattern generation circuit via a reference signal line different from the back shield wiring, the front shield wiring, and both shield wirings A pattern detection circuit, wherein the pattern generation circuit sends the generated pattern signal to the back surface shield wiring and the front surface seal. Wiring is input to the pattern detection circuit via the reference signal line, and the pattern detection circuit matches / matches the signal input via the back shield wiring and the signal input via the reference signal line. A mismatch or a match / mismatch between a signal input via the surface shield wiring and a signal input from the reference signal line is detected.

  Thereby, in addition to being able to protect the integrated circuit against attacks such as microscopic observation and processing and tampering by FIB etc. from both sides of the integrated circuit, the back shield wiring and the front shield wiring, The pattern generation circuit and the pattern detection circuit can be shared, and the configuration of the apparatus can be simplified.

  Furthermore, in the semiconductor integrated circuit device of the present invention, the back shield wiring is composed of a plurality of layers.

  Thereby, there is an effect that an attack such as processing or falsification by the FIB or the like from the back surface of the integrated circuit can be made more difficult. Further, the resistance to falsification of the back shield wiring can be further increased.

  In the method for manufacturing a semiconductor integrated circuit device of the present invention, a well composed of one region or a plurality of regions is formed on the substrate so as to cover a lower portion of the integrated circuit formed on the semiconductor substrate, and the formation is performed. A pattern generation circuit for generating an arbitrary pattern signal on the formed well, and a pattern signal input from the pattern generation circuit via the well and a match / mismatch between the pattern signal input from the pattern generation circuit Forming an integrated circuit including a pattern detection circuit for detecting the pattern, and connecting one end of the well and the pattern generation circuit, the other end of the well and the pattern detection circuit, and the pattern generation circuit and the pattern detection circuit It is.

  As a result, a semiconductor integrated circuit device having a back shield wiring for protecting the integrated circuit against attacks such as processing by the FIB and tampering from the back surface of the integrated circuit can be manufactured.

  According to the semiconductor integrated circuit device of the present invention, a semiconductor substrate, an integrated circuit provided on the semiconductor substrate, and one or a plurality of wells formed on the semiconductor substrate so as to cover a lower portion of the integrated circuit. A back shield wiring composed of a book, a pattern generation circuit connected to one end of the back shield wiring, and a pattern detection circuit connected to the other end of the back shield wiring, and the pattern at one end of the back shield wiring A signal generated in the generation circuit is input, the input signal is output from the other end of the back shield wiring, and the pattern detection circuit includes a signal output from the other end of the back shield wiring, and the pattern generation circuit Because of the detection of coincidence / non-coincidence with the signal generated by the It can be protected circuit. In addition, since the back shield wiring is formed of a well, it is possible to prevent the back shield wiring from being observed with a microscope, and the back shield wiring can be more resistant to tampering.

  Furthermore, one or a plurality of surface shield wirings formed on the surface of the integrated circuit so as to cover the upper side of the integrated circuit, a pattern generation circuit connected to one end of the surface shield wiring, and the surface shield wiring And a pattern detection circuit connected to the other end of the surface, the signal generated by the pattern generation circuit is input to one end of the surface shield wiring, the input signal is output from the other end of the surface shield wiring, Since the pattern detection circuit detects the coincidence / mismatch between the signal output from the other end of the surface shield wiring and the signal generated by the pattern generation circuit, the pattern detection circuit can detect from the front surface or the back surface of the integrated circuit. The integrated circuit can be protected against attacks such as microscopic observation, processing by FIB, tampering, and the like.

  Furthermore, if the back shield wiring of the semiconductor integrated circuit device of the present invention is formed of a plurality of layers, it becomes more difficult to attack from the back surface of the integrated circuit by FIB or the like, or to attack such as tampering. There is an effect that can.

  Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a well is formed so as to cover a lower portion of the integrated circuit formed on the semiconductor substrate, one end of the well is connected to the pattern generation circuit, and the other end Is connected to the pattern detection circuit, so that it is possible to manufacture a semiconductor integrated circuit device on which a back shield wiring is formed which makes it difficult to perform an attack such as processing or modification by FIB from the back surface of the integrated circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
1A and 1B are diagrams showing a configuration of a semiconductor integrated circuit device according to the first embodiment. FIG. 1A is a perspective view of the semiconductor integrated circuit device, and FIG. 1B shows a surface of the integrated circuit. Figure (c) is a diagram showing the back side.

  As shown in FIG. 1, the semiconductor integrated circuit device 10 according to the first embodiment includes an integrated circuit region 11 in which an integrated circuit is formed, a deep well layer 12 in which a deep well is formed, and a semiconductor substrate 13. The integrated circuit region 11 includes a protection integrated circuit region 14 in which an integrated circuit to be protected is formed. The integrated circuit region 11 is provided on the semiconductor substrate 13, and the deep well layer 12 is provided on the semiconductor substrate 13 so as to cover the lower side of the integrated circuit region 11.

  In the first embodiment, a surface shield wiring 15 is formed on the surface of the integrated circuit region 11 so as to cover the protective integrated circuit region 14 as shown in FIG. On the back surface of the region 11, as shown in FIG. 1C, a back surface shield wiring 16 composed of a deep well is formed on the semiconductor substrate 13 so as to cover the lower part of the protection integrated circuit region 14. Yes. In FIG. 1, each shield wiring 15, 16 is formed so as to cover the entire surface of the protection integrated circuit region 14 with one wiring, but is formed so as to partially cover the protection integrated circuit region 14. It may be formed by a plurality of lines.

FIG. 2 is a circuit diagram of the semiconductor integrated circuit device according to the first embodiment.
In FIG. 2, 21 is a pattern generation circuit, 24 is a pattern detection circuit, 22 and 23 are comparison reference signals for inputting comparison reference signals s11 and s21 output from the pattern generation circuit 21 to the pattern generation circuit 24. Is a line. The pattern generation circuit 21 and the pattern detection circuit 24 are provided in the protection integrated circuit region 14.

  The pattern generation circuit 21 generates an arbitrary pattern signal, inputs it as an attack detection signal s12, s22 to one end of each shield wiring 15, 16, and has the same pattern as the attack detection signal s12, s22. The comparison reference signals s11 and s21 are input to one end of the comparison reference signal lines 22 and 23.

  The pattern generation circuit 21 is connected to one end of each shield wiring 15, 16, and the pattern detection circuit 24 is connected to each other end of each shield wiring 15, 16.

  The shield lines 15 and 16 and the comparison reference signal lines 22 and 23 are connected to the pattern detection circuit 24. The attack detection signals s12 and s22 generated by the pattern generation circuit 21 are connected to the pattern detection circuit 24. Are input through the shield wirings 15 and 16, and the comparison reference signals s11 and s21 generated by the pattern generation circuit 21 are input through the comparison reference signal lines 22 and 23, respectively. The inputted attack detection signals s12 and s22 are compared with the comparison reference signals s11 and s21, and an abnormality detection signal SEN is output when a mismatch between them is detected.

  In the first embodiment, shield wirings 15 and 16 and comparison reference signal lines 22 and 23 formed on the front and back surfaces of the integrated circuit region 11 are formed on the front and back surfaces, respectively. Although cases have been described as examples, a plurality of these may be used.

  FIG. 3 is a diagram showing in detail an example of connection between the front shield wiring and the rear shield wiring of the first embodiment, the pattern generation circuit, and the pattern detection circuit.

  3, 30a to 30d are contacts, 31 is STI (Shallow Trench Isolation), 32a to 32d are P type wells, 33 are N type wells, 34a and 34b are N + regions, 35 is a deep P type well, and 36 is a protection. A circuit element region in which elements of an integrated circuit to be formed are formed.

The back shield wiring 16 is formed of a deep N type well.
The semiconductor substrate 13, the P-type wells 32 a to 32 d, and the deep P-type well 35 are grounded (GND) and are designed so that no reverse current flows at the PN junction surface with the back shield wiring 16. Has been.

  The pattern generation circuit 21 is connected to one end of the back shield wiring 16 via a contact 30a and an N + region 34a, and connected to the other end of the pattern detection circuit 24 via an N + region 34b and a contact 30b. Is done. Further, the pattern generation circuit 21 is connected to one end of the surface shield wiring 15 via a contact 30c, and the pattern detection circuit 24 is connected to the other end of the surface shield wiring 15 via a contact 30d. .

Next, in the semiconductor integrated circuit device 10 configured as described above, an operation for detecting that there has been a processing or tampering attack by an external FIB or the like on the integrated circuit will be described.
The random first pattern signal generated by the pattern generation circuit 21 is input as an attack detection signal s22 to one end of the back shield wiring 16 via the contact 30a and the N + region 34a, and the signal s22 is The other end of the back shield wiring 16 is input to the pattern detection circuit 24 through the N + region 34b and the contact 30b.

  The first pattern signal generated by the pattern generation circuit 21 is input to the pattern detection circuit 24 through the comparison reference signal line 23 as a comparison reference signal s21.

  Further, the random second pattern signal generated by the pattern generation circuit 21 is input as an attack detection signal s12 to one end of the surface shield wiring 15 via the contact 30c, and the signal s12 is input to the surface shield. The other end of the wiring 15 is input to the pattern detection circuit 24 through a contact 30d.

  The second pattern signal generated by the pattern generation circuit 21 is input to the pattern detection circuit 24 via the comparison reference signal line 22 as a comparison reference signal s11.

  That is, the same pattern signal is input to the front shield wiring 15 and the comparison reference signal line 22 and to the back shield wiring 16 and the comparison reference signal line 23.

  In the pattern detection circuit 24, it is determined whether the attack detection signal s12 via the front shield wiring 15 and the comparison reference signal s11 via the comparison reference signal line 22 are the same pattern signal. The attack detection signal s22 and the comparison reference signal s21 via the comparison reference signal line 23 are checked for the same pattern signal, and the attack detection signal and the comparison reference signal are not the same pattern. Is detected, the abnormality detection signal SEN is output.

  For example, when the back shield wiring 16 is removed or cut from the back surface of the integrated circuit region 11 by a third party, the attack detection signal input to the pattern detection circuit 24 through the back shield wiring 16. Since the pattern of s22 becomes different from the comparison reference signal s21, the pattern detection circuit 24 detects a mismatch between the attack detection signal s22 and the comparison reference signal s21, and outputs an abnormality detection signal SEN.

  When the abnormality detection signal SEN is output from the pattern detection circuit 24, for example, if a signal for stopping a CPU (not shown) is generated according to the output of the SEN, the back surface or the front surface of the integrated circuit is generated. Therefore, it is possible to prevent the operation analysis of the integrated circuit from being performed.

  Further, if each of the shield wirings 15 and 16 is constituted by a plurality of wirings so that different pattern signals flow in adjacent wirings, a short circuit between the shield wirings can be detected.

  As described above, according to the semiconductor integrated circuit device 10 of the first embodiment, the back shield wiring 16 is formed on the substrate 13 of the device 10 so as to cover the lower part of the protective integrated circuit region 14. A pattern generation circuit 21 for generating a random pattern signal and the pattern detection circuit 24 for detecting a signal from the pattern generation circuit 21 are connected via the back shield wiring 16 and the comparison reference signal line 23, and The pattern detection circuit 24 detects whether or not the pattern signal via the back shield wiring 16 and the pattern signal via the comparison reference signal line 23 match. If they do not match, the CPU operation is stopped. As a result, it is possible to prevent the backside shield wiring from the backside of the integrated circuit from being observed with a microscope, and to add the FIB from the backside of the integrated circuit. Against attacks such as and falsification, it is possible to protect the integrated circuit.

  Further, according to the semiconductor integrated circuit device of the first embodiment, the surface shield wiring is formed on the surface of the integrated circuit so as to cover the upper side of the protection integrated circuit 14, and the pattern generating circuit 21 and the pattern generating circuit are formed. The pattern detection circuit 24 that detects a signal from the signal line 21 is connected via the surface shield wiring 15 and the comparison reference signal line 22, and the pattern detection circuit 24 uses the pattern signal via the surface shield wiring 15 and Since it is detected whether or not the pattern signal via the comparison reference signal line 22 matches, and if it does not match, the operation of the CPU is stopped, so that observation of the microscope from the surface of the integrated circuit can be prevented. The integrated circuit can be protected against attacks such as processing and falsification by the FIB from the surface of the integrated circuit.

  Furthermore, in the first embodiment, since the back shield wiring 16 is formed by a well, the shape of the back shield wiring 16 cannot be observed with a microscope, and therefore the back shield wiring 16 is resistant to tampering. Can be strengthened.

  In the first embodiment of the present invention, the generation of pattern signals in each of the front shield wiring 15 and the rear shield wiring 16 and the detection of coincidence / non-coincidence of the pattern signals are performed using one pattern generation circuit 21 and a pattern. Although the case where the detection circuit 24 is used is taken as an example, a pattern generation circuit and a pattern detection circuit may be provided for each of the front shield wiring 15 and the rear shield wiring 16.

  In the first embodiment, the case where the shield wiring is provided on both the front surface and the back surface of the integrated circuit is described as an example. However, the shield wiring described above is provided only on the back surface side, and the above-described patent is provided on the front surface side. For example, a conventional technique such as Document 1 or Patent Document 2 may be used to prevent an attack from the surface of the integrated circuit.

(Embodiment 2)
In the second embodiment, a method for manufacturing the semiconductor integrated circuit device described in the first embodiment will be described. FIG. 4 is a diagram showing an example of a series of flows of the manufacturing method of the semiconductor integrated circuit device according to the second embodiment.

(Step 1) First, the back shield wiring 16 is formed on the semiconductor substrate 13.
Specifically, first, as shown in FIG. 4A, an oxide film a4 and a nitride film a3 are formed on the surface of the semiconductor substrate a5 by a known method, and an STIa2 is formed using the active region formation mask a1. To do.

  Next, as shown in FIG. 4B, using the deep N-type well formation mask b1, the deep N corresponding to the back shield wiring 16 is wider than the protection integrated circuit region 14 where the integrated circuit to be protected is formed. A mold well b2 is formed. Note that the deep N-type well b2 may be divided into a plurality of regions.

  Then, as shown in FIG. 4C, a deep P-type well c2 corresponding to the back shield wiring 16 is formed using the deep P-type well formation mask c1.

(Step 2) Thereafter, a circuit element region 36 including elements of the pattern generation circuit 21 and elements (not shown) of the pattern detection circuit 24 is formed above the back shield wiring 16.
Specifically, first, as shown in FIG. 4D, an N-type well d2 is formed in a region where a P-channel MOS transistor is to be formed using an N-type well formation mask d1. At this time, impurities such as P + (phosphorus) are again implanted into the extraction portion of the deep N-type well b2, thereby increasing the impurity concentration in the shallow portion of the deep N-type well b2 and increasing the depth of the deep portion of the well b2. Approach the concentration.

  Next, as shown in FIG. 4E, a P-type well e2 is formed using a P-type well formation mask e1, and then as shown in FIG. 4F, a gate formation mask f3 is used. Thus, the gate f4 is formed. Before forming the gate f4, in order to adjust the threshold voltage of the transistor to a predetermined value, the channel doping is performed by using the channel doping formation mask f1 for the P-type well and the channel doping formation mask f2 for the N-type well. May be.

  Then, as shown in FIG. 4G, a source / drain region g7 is formed using a source / drain region formation mask g3 for P-type well and a source / drain region formation mask g4 for N-type well. At this time, an impurity such as B + (boron) is implanted into a region to be a connection point between the deep N-type well b2 and a pattern generation circuit (not shown) or a pattern detection circuit (not shown), and an N + region g8 is formed. Form it.

  Before forming the source / drain regions, in order to avoid an increase in leakage current due to hot carriers and fluctuations in characteristics, a P-well LDD (Lightly Doped Drain) region formation mask g1 and an N-type well LDD region The LDD region g6 may be formed using the formation mask g2.

  The elements of the pattern generation circuit 21 and the elements of the pattern detection circuit 24 are not shown in FIG. 4, but are formed in the circuit element region 36 in step 2.

  (Step 3) In order to connect the element of the pattern generation circuit 21 and the element (not shown) of the pattern detection circuit 24 formed in the circuit element region 36 in Step 2 to the back shield wiring 16 Contacts 30a and 30b are formed. Further, when forming the surface shield wiring, contacts 30c and 30d for connecting the element of the pattern generation circuit 21 and the element (not shown) of the pattern detection circuit 24 and the surface shield wiring 15 are formed.

  Specifically, as shown in FIG. 4H, after forming the interlayer insulating film h3, the contact hole h2 is formed using the contact hole formation mask h1, and a conductor material such as tungsten is deposited. Thus, contacts 30a, 30b, 30c, and 30d are formed.

  Next, as shown in FIG. 4I, using the first wiring formation mask i1, the element (not shown) of the pattern generation circuit 21, one end of the well b2, and the element of the pattern detection circuit 24 are used. A first wiring i2 for connecting (not shown) and the other end of the well b2 is formed. Further, when forming the surface shield wiring, the element (not shown) of the pattern generation circuit 21 and one end of the surface shield wiring 15 and the element (not shown) of the pattern detection circuit 24 and the surface shield wiring 15 are formed. A first wiring i2 for connecting the other end is formed.

  (Step 4) Then, on the circuit element region 36, wiring necessary for connecting each circuit element in the region 36 is formed.

  (Step 5) Thereafter, when further forming the surface shield wiring, the surface shield wiring 15 is formed in the uppermost layer after all the necessary wirings are formed.

  Specifically, as shown in FIG. 4 (j), after forming an interlayer insulating film of (n-1) layers (n> 2), each of these is used using a via hole formation mask (not shown). By repeating the operation of forming vias for connecting the wirings formed on the interlayer insulating film, the interlayer insulating films j5 and j6, the (n-1) th wiring j4, the via j3 connected to the contacts 30c and 30d, etc. Then, an nth wiring j2 corresponding to the surface shield wiring 15 is formed on the interlayer insulating film j5 as the uppermost layer using the nth wiring formation mask j1.

  As described above, according to the second embodiment, the well region b2 is formed on the substrate 13 so as to cover the lower side of the integrated circuit formed on the semiconductor substrate 13, and the formed well region b2 is formed. An integrated circuit including a pattern generation circuit 21 that generates an arbitrary pattern signal and a pattern detection circuit 24 that detects a signal from the pattern generation circuit 21 is formed on one end of the well region b2 and the pattern generation circuit. 21, the other end of the well region b2 and the pattern detection circuit 24, and the pattern generation circuit 21 and the pattern detection circuit 24 are connected to manufacture the semiconductor integrated circuit device 10. Manufactures a semiconductor integrated circuit device 10 having a back shield wiring that protects the integrated circuit against attacks such as processing by the FIB or tampering from the back surface or tampering. Rukoto can.

  Furthermore, if a surface shield wiring connected to the pattern detection circuit 24 and the pattern generation circuit 21 is formed on the uppermost layer, processing such as processing by the FIB or the like from the surface of the integrated circuit, tampering, etc. The semiconductor integrated circuit device 10 further including a surface shield wiring for protecting the integrated circuit against an attack can be manufactured.

  INDUSTRIAL APPLICABILITY The present invention is useful as a security LSI that can counter an attack such as data falsification or illegal reading from the outside on a semiconductor integrated circuit device.

1 is a diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. 1 is a circuit diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. 1 is a schematic diagram showing in detail a semiconductor integrated circuit device according to a first embodiment of the present invention. It is a figure which shows an example of the STI formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention. It is a figure which shows an example of the deep N type well formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention. It is a figure which shows an example of the deep P type well formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention. It is a figure which shows an example of the N type well formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention. It is a figure which shows an example of the P-type well formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention. It is a figure which shows an example of the gate formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention. It is a figure which shows an example of the source / drain / N + area | region formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention. It is a figure which shows an example of the contact hole formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention. It is a figure which shows an example of the 1st wiring formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention. It is a figure which shows an example of the nth wiring formation process in the manufacturing method of the semiconductor integrated circuit device of Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit device 11 Integrated circuit area | region 12 Deep well layer 13 Semiconductor substrate 14 Protection integrated circuit area | region 15 Surface shield wiring 16 Back surface shield wiring 21 Pattern generation circuit 22, 23 Comparison reference signal line 24 Pattern detection circuit 30a, 30b, 30c, 30d contact 31 STI
32a, 32b, 32c, 32d P-type well 33 N-type well 34a, 34b N + region 35 Deep P-type well 36 Circuit element region a1 Active region formation mask a2 STI
a3 Nitride film a4 Oxide film a5 Semiconductor substrate b1 Deep N type well formation mask b2 Deep N type well c1 Deep P type well formation mask c2 Deep P type well d1 N type well formation mask d2 N type well e1 P type well formation mask e2 P-type well f1 P-type well channel dope forming mask f2 N-type well channel dope forming mask f3 Gate forming mask f4 Gate g1 P-type well LDD region forming mask g2 N-type well LDD region forming mask g3 P-type well Source / drain region formation mask g4 N-type source / drain region formation mask g5 Side wall g6 LDD region g7 Source / drain region g8 N + region h1 Contact hole formation mask h2 Contact hole h3, j5, j6 Film i1 first wiring forming mask i2 first wiring j1 n th wiring forming mask j2 n-th wiring j3 via j4 (n-1) -th wires s11, s21 comparison reference signal s12, s22 attack detection signal

Claims (5)

A semiconductor substrate;
An integrated circuit provided on the semiconductor substrate;
A back shield wiring composed of one or a plurality of wells formed on the semiconductor substrate so as to cover a lower portion of the integrated circuit;
A pattern generation circuit for backside shield wiring that generates an arbitrary pattern signal connected to one end of the backside shield wiring;
The back shield wiring pattern generation circuit includes the back shield wiring and a back shield wiring pattern detection circuit connected via a reference signal line different from the back shield wiring,
The back shield wiring pattern generation circuit inputs the generated pattern signal to the back shield wiring pattern detection circuit via the back shield wiring and the reference signal line,
The back shield wiring pattern detection circuit detects coincidence / mismatch between a signal input via the back shield wiring and a signal input via the reference signal line;
A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1,
One or more surface shield wirings formed on the surface of the integrated circuit so as to cover the upper side of the integrated circuit;
A pattern generation circuit for surface shield wiring that generates an arbitrary pattern signal connected to one end of the surface shield wiring;
The surface shield wiring pattern generation circuit, further comprising: the surface shield wiring, and a surface shield wiring pattern detection circuit connected via a reference signal line different from the surface shield wiring,
The surface shield wiring pattern generation circuit inputs the generated pattern signal to the surface shield wiring pattern detection circuit via the surface shield wiring and the reference signal line,
The surface shield wiring pattern detection circuit detects a match / mismatch between a signal input via the surface shield wiring and a signal input via the reference signal line.
A semiconductor integrated circuit device. A semiconductor substrate;
An integrated circuit provided on the semiconductor substrate;
A back shield wiring composed of one or a plurality of wells formed on the semiconductor substrate so as to cover a lower portion of the integrated circuit;
One or more surface shield wirings formed on the surface of the integrated circuit so as to cover the upper side of the integrated circuit;
A pattern generating circuit for generating an arbitrary pattern signal connected to one end of the back shield wiring and one end of the front shield wiring;
A pattern detection circuit connected to the pattern generation circuit via a reference signal line different from the back shield wiring, the front shield wiring, and both shield wirings,
The pattern generation circuit inputs the generated pattern signal to the pattern detection circuit via the back shield wiring, the front shield wiring, and the reference signal line,
The pattern detection circuit includes a signal input via the back shield wiring, a match / mismatch of the signal input via the reference signal line, and a signal input via the front shield wiring, Detects match / mismatch of signals input from the reference signal line,
A semiconductor integrated circuit device. The semiconductor integrated circuit device according to any one of claims 1 to 3,
The back shield wiring is composed of a plurality of layers.
A semiconductor integrated circuit device. Forming a well consisting of one region or a plurality of regions on the substrate so as to cover the lower side of the integrated circuit formed on the semiconductor substrate;
A pattern generation circuit for generating an arbitrary pattern signal on the formed well, and a pattern signal input from the pattern generation circuit via the well and a pattern signal input from the pattern generation circuit Forming an integrated circuit including a pattern detection circuit for detecting a mismatch;
Connecting the one end of the well and the pattern generation circuit, the other end of the well and the pattern detection circuit, and the pattern generation circuit and the pattern detection circuit;
A method of manufacturing a semiconductor integrated circuit device.

Images