JP2008198700A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for avoiding attack by condensed light. <P>SOLUTION: A plurality of photodetectors (2) are used to detect the irradiated lights. The plurality of photodetectors are scattered in arrangement on the semiconductor integrated circuit device. Each photodetector includes a photodetecting element (23) of the thyristor structure that is made conductive using a leak current generated by irradiation of light to a well boundary on the semiconductor substrate as a trigger. The photodetector of such a structure can be formed in a small region and many photodetectors can be uniformly arranged on the semiconductor chip. Therefore, attack of the condensed lights can be avoided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique that is effective when applied to prevention of reverse engineering of an encryption key or the like possessed by a semiconductor integrated circuit such as an IC card microcomputer.

  With the development of semiconductor technology, it has become common to make secure and reliable settlement by incorporating IC (Integrated Circuits) into credit cards, securities, etc., and encrypting information for communication. This method using an IC is more difficult for counterfeiting and impersonation than a method using a conventional magnetic recording, and has advantages for both end users and service providers.

  Research on cryptographic algorithms has been conducted for many years, and it is very difficult to estimate a cryptographic key or the like from a signal intercepted on a communication path, and this risk is so small that it can be virtually ignored. The problem is an attempt to directly read internal information and an encryption key on the IC by opening the IC and performing reverse engineering.

  Conventionally, an IC card is abnormally operated by supplying a clock with an illegal frequency to the IC card, a power supply voltage is suddenly increased or decreased, or a strong electromagnetic wave is irradiated, and internal information and an encryption key are read. Was devised. On the other hand, the IC side can prevent reading out the internal information and the encryption key by detecting these abnormal states.

  For example, Patent Document 1 describes a technique in which an unsealing sensor is provided in an IC chip for an IC card, and when the unsealing is detected, the CPU performs an erasing operation on the memory to increase security against security.

  In Patent Document 2, a small window is formed in a part of a package that seals and shields a circuit configuration so that light is irradiated only to a light detection sensor unit, and operates normally in a light detection state. In this case, when performing illegal analysis, the package is opened and analysis is performed in the dark to avoid the adverse effects of light. Therefore, a technique is described in which operation analysis cannot be performed and illegal reading of stored information is impossible.

  In Patent Document 3, a plurality of light receiving elements are integrated in a distributed manner in an IC, and each of the plurality of light receiving elements is connected to a connection line connected to a nonvolatile memory cell, a connection line connected to a logic circuit, or a logic element. Connected to any of the connected lines, the connection line is interrupted, and the IC is opened by interrupting the normal operation of the circuit related to the connection line by conducting or connecting to the ground line. Disclose technology to protect internal information when

  However, these documents do not take into account new card hacking in which a malfunction is actively induced by light irradiation and analysis is attempted by a statistical method.

  On the other hand, Patent Document 4 discloses a semiconductor integrated circuit capable of defending against card hacking in which erroneous operation is actively induced by light irradiation to illegally acquire security protection information.

Japanese Patent Laid-Open No. 10-320293 JP 2000-216345 A (paragraphs 0009 to 0011) JP-A-11-102324 Japanese Patent Laid-Open No. 2004-206680

  A chip manufacturer aims to improve tamper resistance by mounting a circuit for detecting a leakage current generated at a junction between a P-type semiconductor and an N-type semiconductor when irradiated with light on a semiconductor integrated circuit. Since this photodetector has a large area, the number of photodetectors that can be mounted in an LSI, which is limited to mounting one or two in the chip surface, is as small as about one to two. Avoided with light. For example, a case has been reported in which a laser light source and an optical microscope are used in combination, and high-energy light is condensed to about several hundreds μm to succeed in an attack while avoiding a photodetector. In addition, it is difficult to reduce the cost of a plurality of photodetectors because the chip area increases remarkably. Furthermore, since the current photodetector is an analog circuit, it does not follow the standard cell scaling rule, and there is a limit to reducing the chip area even if the chip is shrunk in the future.

  The objective of this invention is providing the technique for avoiding the attack by the condensed light.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a plurality of photodetectors each capable of detecting the irradiated light are dispersedly arranged in the semiconductor integrated circuit device. At this time, each of the photodetectors includes a photodetector having a thyristor structure that conducts using a leakage current caused by light irradiation to the well boundary on the semiconductor substrate as a trigger. According to such a configuration, the photodetector can be formed in a small area, and a large number of photodetector elements can be dispersedly arranged in the semiconductor chip.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to avoid an attack due to the collected light by disposing a large number of light detection elements in the semiconductor chip.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor integrated circuit device (1) according to a typical embodiment of the present invention includes a plurality of photodetectors (2) each capable of detecting irradiated light, and the plurality of photodetectors are Dispersively arranged in the semiconductor integrated circuit device, each of the photodetectors includes a thyristor-structured photodetector (23) that conducts with a leakage current caused by light irradiation to the well boundary on the semiconductor substrate as a trigger. .

According to the above configuration, it can be formed in a small region of, for example, about 100 μm ² (10 μm × 10 μm), and many photodetecting elements can be uniformly arranged in the semiconductor chip. For this reason, it becomes difficult to avoid light detection even when, for example, a laser light source and an optical microscope are used together and high-energy light is condensed to about several hundred μm.

  [2] At this time, the photodetector can be configured to include a latch circuit (24) capable of holding a logic state transitioned by conduction of the photodetector element.

  [3] According to another aspect, the semiconductor integrated circuit device (1) includes a plurality of photodetectors (2) each capable of detecting irradiated light, and the plurality of photodetectors are the semiconductor integrated circuit. Each of the photodetectors dispersedly arranged in the apparatus includes a photodetection element (23) having a thyristor structure that conducts with a leakage current caused by light irradiation to the well boundary on the semiconductor substrate as a trigger. A latch circuit (24) is arranged in the photodetection range, and the latch circuit is connected to the photodetection element so as to be able to hold a logic state transitioned by conduction of another photodetection element arranged at a different position. Made up.

[4] The photodetecting element includes an N well, a P well adjacent to the N well, a P ⁺ type region formed in the N well, and an N ⁺ type region formed in the P well. The thyristor structure includes a leakage current caused by light irradiation to the boundary between the N-well and the P-well, and can be configured to conduct as a trigger.

  [5] Further, the formation position of the light detection element can be determined in consideration of the light detection range for each of the light detection elements and the light irradiation range assumed to be an attack.

2. Next, the embodiment will be described in more detail.

  FIG. 1 shows a configuration example of a semiconductor integrated circuit device according to the present invention.

  The semiconductor integrated circuit device 1 is not particularly limited, and is a microcomputer or the like that is cut from a wafer by dicing (referred to as “semiconductor chip”). The semiconductor integrated circuit device 1 is provided with a plurality of photodetectors 2 for detecting light that is undesired for the purpose of reverse engineering. Each of the photodetectors 2 has a predetermined detection area 3, and when the detection area 3 is irradiated with light, it is detected by the corresponding photodetector 2. When any of the photodetectors 2 detects light, a logic circuit (not shown) in the semiconductor integrated circuit device 1 is reset.

  FIG. 2 shows a configuration example of the photodetector 2.

A p-channel type MOS transistor 21 coupled to the high potential side power source Vdd and an n channel type MOS transistor 22 coupled to the low potential side power source Vss are connected in series to form an inverter. A photodetecting element 23 is provided between the output node 26 of the inverter and the low potential side power source Vss. Further, a latch circuit 24 capable of holding the logic state of the output node 26 is coupled to the output node 26. A logic circuit (not shown) such as a central processing unit in the semiconductor integrated circuit device 1 is reset at the subsequent stage of the latch circuit 24 based on the output signal of the latch circuit 24. The photodetecting element 22 has a thyristor structure that conducts using a leakage current caused by light irradiation to the well boundary on the semiconductor substrate as a trigger. Specifically, for example, as shown in FIG. 3, an N well (Nwell) and a P well (Pwell) are formed on a semiconductor substrate via an isolation region (NiSO). An N ⁺ type region and a P ⁺ type region are formed in the N well and the P well. Here, the thyristor is configured by joining the P ⁺ type region, the N well, the P well, and the N ⁺ type region. In this case, the anode 31 is withdrawn from the P ⁺ -type region, the cathode is withdrawn from the N ⁺ -type region. Since this thyristor can be formed in a small region of, for example, about 100 μm ² (10 μm × 10 μm), many photodetecting elements 23 are arranged uniformly without affecting the logic circuit originally present in the semiconductor chip. be able to.

In the above configuration, when light irradiation such as laser light is performed on the boundary between the N well and the P well, a leakage current flows due to the irradiation. In the thyristor structure including the P ⁺ -type region, the N well, the P well, and the N ⁺ -type region, the leakage current becomes a trigger and becomes conductive, and a large current can flow from the anode 31 toward the cathode 32. Therefore, in the configuration shown in FIG. 2, when light such as laser light is not irradiated to the boundary between the N well and the P well, the output node 26 of the inverter is set to the high level. When the thyristor is turned on by irradiating laser light or the like to the boundary between the P well and the P well, the charge at the output node 26 of the inverter is transferred to the low potential side power supply Vss side via the light detecting element 23. As a result, the output node 26 of the inverter is changed from the high level to the low level. This low level is latched by the latch circuit 24, and a logic circuit (not shown) in the semiconductor integrated circuit device 1 is reset based on the latched low level. Thereby, reverse engineering is prevented.

  According to the above example, the following effects can be obtained.

(1) The thyristor shown in FIG. 3 can be formed in a small region of, for example, about 100 μm ² (10 μm × 10 μm), so that it can detect a lot of light without affecting the logic circuit originally existing in the semiconductor chip. The elements 23 can be arranged uniformly. For this reason, for example, even when a high-energy light is condensed to about several hundred μm using a laser light source and an optical microscope in combination, it is difficult to avoid light detection, and light detection is performed.

  (2) Since the tamper resistance can be improved by the effect of (1) above, it is possible to prevent reverse engineering of encryption keys held by a semiconductor integrated circuit such as a microcomputer for an IC card. it can.

  FIG. 4 shows another configuration of the photodetector 2. The photodetector 2 shown in FIG. 4 is greatly different from that shown in FIG. 2 in that the n-channel MOS transistor 22 is omitted. The p-channel MOS transistor 21 is turned on when the gate is at a low level, and functions as a pull-up resistor. Even in such a configuration, when light such as laser light is applied to the boundary between the N well and the P well, a leakage current flows due to this, and in the thyristor structure, the leakage current triggers the conduction state. Thus, since a large current can flow from the anode 31 to the cathode 32 (see FIG. 3), the same effect as that shown in FIG. 2 can be obtained.

  Next, another arrangement example of the photodetector 2 will be described.

  For example, as shown in FIG. 5, the photodetector 2 is arranged in the central portion of a main block formation region such as a central processing unit (CPU) or a coprocessor (COP) in a semiconductor integrated circuit device such as a microcomputer. be able to. In this case, the light detection range 3 of the light detector 2 covers a main block formation region such as a central processing unit (CPU) or a coprocessor (COP). Thereby, when light irradiation is performed on a main block in a semiconductor integrated circuit device such as a microcomputer, a logic circuit (not shown) in the semiconductor integrated circuit device 1 can be reset. In the configuration shown in FIG. 5, the number of photodetectors 2 can be reduced as compared with the arrangement shown in FIG.

  2 and 4, the light detection element 23 and other elements can be arranged separately. In that case, when there is a slender empty area, in order to use it effectively, for example, as shown in FIG. 6 (a), slender light detection is performed using a slender boundary between the P well and the N well. The element (thyristor) 23 may be configured. In this way, the light detection range 3 of the elongated photodetecting element 23 has an elliptical shape corresponding to the elongated photodetecting element 23 as shown in FIG. 6B.

  Further, as shown in FIG. 7A, a plurality of light detection elements (thyristors) 23 can be connected in parallel. In this case, even if the current that can be tolerated by the individual light detection elements 23 is not sufficient, the allowable current can be increased by using a plurality of light detection elements 23 connected in parallel.

As shown in FIG. 8, by arranging a plurality of photodetectors 2 so that an equilateral triangle is formed by a line (shown by a broken line) connecting the photodetectors 2 adjacent to each other, the arrangement of the photodetectors 2 Can be optimized. For example, the irradiation range of the laser beam assuming an attack is L1, the radius of the light detection range 3 for each light detector 2 is D1, the central portions of the light detectors 2 adjacent to each other are A, B, and A , B is a plurality of photodetectors 2 arranged so that the following formula is satisfied. Thereby, the some photodetector 2 can be arrange | positioned efficiently. Reference numeral 80 denotes a region where light irradiation is desired to be detected.
| A−B | ≦ √3 (L1 + D1)
In the arrangement of the photodetector 2, the detection capability of the detection element and the irradiation range of the laser light that is assumed to be an attack are taken into consideration. Compared to the case shown in FIG. 8, when the irradiation range of the laser light that assumes an attack is narrow, as shown in FIG. 9, the arrangement density of the plurality of photodetectors 2 may be increased.

  Further, there may be a case where the latch circuit 24 malfunctions due to laser light irradiation. If the light detection element 23 constituting the light detector 2 and the latch circuit 24 for latching the detection result are arranged close to each other, the light detection element 23 detects the irradiation of the laser beam. Nevertheless, the malfunction of the latch circuit 24 makes it impossible to properly latch the light detection result. In order to avoid this, as shown in FIG. 10, it is conceivable to take a predetermined distance between the light detection element 23 and the latch circuit 24 for latching the detection result. That is, the latch circuit 24 arranged in the vicinity of the light detection element 23 and in the light detection range of the light detection element 23 is changed by conduction of the light detection element 23 arranged at a position different from the light detection element 23. Routed to latch the logic state generated. By doing so, it is possible to prevent malfunction of the latch circuit that latches the light detection result in the light detection element 23, so that the reliability of light detection can be improved. Furthermore, if the latch circuit 24 is covered with a wiring layer, the laser light applied to the latch circuit 24 can be attenuated, so that the malfunction prevention of the latch circuit 24 can be enhanced.

  The detection result of one photodetecting element 23 may be latched by a plurality of latch circuits. In addition, a single latch circuit 24 may be shared by a plurality of light detection elements 23 so that the detection results of the plurality of light detection elements 23 are received by one latch circuit 24. As shown in FIG. 11, a plurality of photodetecting elements 23 may be cascade-connected.

  The detection range 3 of the light detection element 23 can be approximated to a rectangular shape, and in this case, as shown in FIG. 12 or FIG. 13, a plurality of light detection elements 23 can be arranged in a lattice shape.

  When there is a direction that is easy to detect as a characteristic of the photodetector 2, or when there is a direction in which a current easily flows in the characteristic of the manufactured semiconductor integrated circuit device, the equilateral triangle shown in FIG. 8 is shown in FIG. Can be deformed. In the example shown in FIG. 14, as the characteristics of the individual photodetectors 2, the direction of the arrow X is easily detected, and accordingly, the number of the photodetectors 2 is reduced accordingly.

  In the example shown in FIGS. 8 and 9, a plurality of photodetectors 2 are arranged so that equilateral triangles are formed by lines (shown by broken lines) connecting the photodetectors 2 adjacent to each other. As shown, a plurality of photodetectors 2 may be optimized so that a regular hexagon is formed by a line (shown by a broken line) connecting the photodetectors 2 adjacent to each other. As shown, a plurality of photodetectors 2 may be optimized so that a regular square is formed by a line (shown by a broken line) connecting the photodetectors 2 adjacent to each other.

  Next, another configuration example of the photodetector 2 and the periphery thereof will be described.

  As shown in FIG. 17A, an OR circuit 171 obtains an OR logic of the outputs of the plurality of photodetectors 2, and a reset generation circuit 172 resets the entire system based on the OR logic result. A reset signal may be generated.

  As shown in FIG. 17B, an OR logic of the outputs of the plurality of photodetectors 2 is obtained by the OR circuit 171, and based on the OR logic result, the interrupt generation circuit 173 determines a predetermined value for the central processing unit. An interrupt signal for making an interrupt request may be generated.

  As shown in FIG. 17C, the OR logic of the outputs of the plurality of photodetectors 2 may be obtained by the OR circuit 171, and the OR logic result may be latched by the latch circuit 174. In this case, the latch information of the latch circuit 174 is read by the central processing unit to analyze the situation.

  As shown in FIG. 17 (d), by disposing a corresponding interrupt generation circuit 175 for each photodetector 2, it is analyzed where undesired light irradiation is performed in the semiconductor integrated circuit device. You may make it do.

  In the example shown in FIGS. 17A to 17C, the OR logic of the outputs of the plurality of photodetectors 2 is obtained, for example, compared with a case where a reset circuit is prepared for each photodetector. Thus, the area required for light detection can be reduced. As a result, by disposing a large number of photodetectors on the chip, it is possible to improve the light detection accuracy and suppress an increase in the chip area, and to provide a chip with high security. .

  As shown in FIG. 18A, the OR logic of the outputs of the plurality of photodetectors 2 is obtained by the OR circuit 171, and the detection signal is generated by the detection signal generation circuit 181 based on the output of the OR circuit 171. be able to. In addition to outputting this detection signal to a central processing unit or the like, the counter 182 counts the number of detections. If this count exceeds a predetermined value, it is determined that undesired light irradiation is frequently performed, and a transition to the reset state or sleep / standby state further increases the possibility of program malfunction. Can be reduced.

  Further, as shown in FIG. 18B, the signal transmitted to the subsequent circuit can be limited to the output signal of the counter 182.

  Furthermore, as shown in FIG. 18C, the outputs of the plurality of detectors 2 may be individually counted by a counter 182.

  Note that the output signal of the OR circuit 171 may be counted by the counter 182 as indicated by broken lines in FIGS. 18 (a) and 18 (b).

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

It is explanatory drawing of the example of photodetector arrangement | positioning in the microcomputer which is an example of the semiconductor integrated circuit device concerning this invention. It is a circuit diagram of a configuration example of a photodetector in the microcomputer. It is explanatory drawing of the structural example of the photon detection element contained in the photon detector in the said microcomputer. It is explanatory drawing of the structural example of the photon detection element contained in the photon detector in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. It is explanatory drawing of another example of photodetector arrangement | positioning in the said microcomputer. FIG. 5 is a circuit diagram illustrating another configuration example of the photodetector and the periphery thereof. FIG. 5 is a circuit diagram illustrating another configuration example of the photodetector and the periphery thereof.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2 Photodetector 3 Photodetection range 21 p channel type MOS transistor 22 n channel type MOS transistor 23 Photodetection element 24 Latch circuit

Claims (5)

Including a plurality of photodetectors each capable of detecting irradiated light,
A semiconductor integrated circuit device formed so as to be resettable based on detection results of the plurality of photodetectors,
The plurality of photodetectors are distributed in the semiconductor integrated circuit device,
Each of the photodetectors comprises a photodetector having a thyristor structure that conducts with a leakage current caused by light irradiation to a well boundary on a semiconductor substrate as a trigger.   2. The semiconductor integrated circuit device according to claim 1, wherein the photodetector includes a latch circuit capable of holding a logic state transitioned by conduction of the photodetector element. Including a plurality of photodetectors each capable of detecting irradiated light,
A semiconductor integrated circuit device formed so as to be resettable based on detection results of the plurality of photodetectors,
The plurality of photodetectors are distributed in the semiconductor integrated circuit device,
Each of the photodetectors includes a photodetector having a thyristor structure that conducts with a leakage current caused by light irradiation to the well boundary on the semiconductor substrate as a trigger,
A latch circuit is disposed in the light detection range of the light detection element,
2. The semiconductor integrated circuit device according to claim 1, wherein the latch circuit is connected so as to be able to hold a logic state transitioned by conduction of another photodetection element arranged at a different position from the photodetection element. The photodetecting element includes an N well,
A P well adjacent to the N well;
A P ⁺ -type region formed in the N-well;
An N ⁺ -type region formed in the P-well,
4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device conducts by using a leakage current caused by light irradiation to the boundary between the N well and the P well as a trigger.   4. The semiconductor integrated circuit device according to claim 1, wherein a formation position of the light detection element is determined in consideration of a light detection range for each of the light detection elements and a light irradiation range assuming an attack.

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