JPH04370969A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form each cell region of a semiconductor integrated circuit with a ROM, which does not rewrite cell information, and an EPROM, which can rewrite cell information, by a common process. CONSTITUTION:An EPROM cell region 12, which can rewrite cell information, and a ROM cell region 11, in which cell information is fixed, are formed onto the same semiconductor substrate, and a large number of storage cells constituting the ROM cell region 11 are composed of cell transistors Tc having the same constitution as cell transistors organizing the EPROM cell region 12 and switches S selecting whether or not the sources of the cell transistors Tc are connected to a power supply Vss on the low potential side.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which a normal ROM and an EPROM in which cell information is rewritable are formed on the same semiconductor substrate. In recent years, semiconductor integrated circuits have become highly integrated and multifunctional, and semiconductor integrated circuits in which a normal ROM and an EPROM are formed on the same substrate have also been developed.

0002

[Prior Art] FIG. 5 shows an example of a semiconductor integrated circuit equipped with a normal ROM and an EPROM in which cell information can be rewritten.
To explain, the CPU 1 controls the RAM 3, ROM 4, EPROM 5, and other various circuits 6 via the address bus 2, writes and reads data to and from the RAM 3 via the data bus 7, and writes data to the ROM 4. A read operation is performed, and data write and read operations are performed on the EPROM 5. The data read to the data bus 7 and the control signal output to the address bus 2 are then output to an external circuit via the input/output port circuit 8, or from the external circuit via the input/output port circuit 8 to the data bus. Data is input to address bus 7, and a control signal is input to address bus 2.

[0003] The R built in such a semiconductor integrated circuit
An example of the specific configuration of OM4 will be explained according to FIG.
A large number of memory cells C constituting the ROM4 are, for example, a large number of depletion type N-channel MOS transistors and one enhancement type N-channel MOS transistor connected in series, and each memory cell C has word lines W1 to Wn.
When one specific word line is selected from among them, all the transistors connected in series are turned on and it becomes possible to output cell information of "0", and when other word lines are selected It becomes possible to output cell information of "1". Then, by selecting any one of the bit lines B1 to Bn, "0" is output from any one of the memory cells C.
Alternatively, cell information of “1” is read out via the sense amplifier 8.

On the other hand, an example of a specific configuration of the EPROM 5 will be explained with reference to FIG. 7. A memory cell Tc composed of an EPROM cell transistor has a gate connected to the word line WE1
~WEn, and the drain is connected to bit line B
It is connected to any one of L1 to BLn, and its source is connected to the low potential side power supply Vss. Then, the address decoder on the row side selects one of the word lines WE1 to WEn, and the address decoder 9 on the column side selects one of the bit lines BL1 to BLn. By selecting one of the memory cells Tc, the memory cell Tc is selected.
The read and write operations of cell information are performed by the sense amplifier and write circuit 10 for c.

[0005]

However, in the semiconductor integrated circuit including the ROM4 and EPROM5 as described above, the ROM4 and EPROM5 are formed as independent blocks, and the sense amplifier 8 and EPROM of the ROM4 are
Since the sense amplifier and write circuit 10 of the ROM 5 also need to be formed independently in each block, there is a problem that the chip area increases. That is, R.O.
If you try to share the bit line of M4 and EPROM5 and share the sense amplifier 8 of ROM4 and the sense amplifier and write circuit 10 of EPROM5, the RO read out by the sense amplifier during the read operation of cell information of ROM4
This is because a soft write may occur in which the cell information of M4 is erroneously written to the memory cell Tc of EPROM5 via the bit line.

Furthermore, since the transistors constituting the memory cell C of the ROM4 and the transistor constituting the memory cell Tc of the EPROM5 have different configurations, they must be formed in separate processes, making the manufacturing process complicated and complicated. There is a problem with that. The purpose of this invention is to
To provide a semiconductor memory device which is equipped with a ROM whose cell information is not rewritten and an EPROM whose cell information is rewritable, and whose memory cells can be formed in a common process, and whose chip area can be reduced.

[0007]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In other words, an EP with rewritable cell information
A ROM cell region 12 and a ROM cell region 11 in which cell information is fixed are formed on the same semiconductor substrate, and the RO
A large number of memory cells constituting the M cell area 11 are EPROMs.
A cell transistor Tc having the same configuration as the cell transistor constituting the cell region 12, and the cell transistor Tc
and a switch S for selecting whether or not to connect the source of the source to the low potential side power supply Vss.

[0008]

[Operation] The cell information read from the memory cells in the ROM cell area 11 and the cell information read from the memory cells in the EPROM cell area 12 are at the same voltage level, making it possible to use a common sense amplifier. ,
The ROM cell region 11 and the EPROM cell region 12 can be formed by a common manufacturing process.

[0009]

[Example] An example embodying this invention is shown below in Figure 2.
~Explained according to FIG. 4. Figure 4 shows ROM and EPROM
This shows the configuration of a ROM and an EPROM of a semiconductor integrated circuit equipped with a ROM cell area 11 and an EPROM.
A large number of memory cells are formed in each cell region 12,
The memory cells have a common address decoder 13 and a common control circuit 14 driven by the address decoder 13.
Selected by The sense amplifier and write circuit 15 driven by the control circuit 16 performs a read operation on the selected ROM cell, and the sense amplifier and write circuit 15 performs write and read operations on the EPROM cell. be exposed.

The specific structure of each of the cell regions 11 and 12 will be explained with reference to FIG. 2. In the EPROM cell region 12, each memory cell Tc is composed of an EPROM cell transistor as in the conventional example, and the word lines WE1 to WEn and By selecting bit lines BL1 to BLn, any one memory cell Tc is selected, and the selected memory cell T
The sense amplifier and write circuit 15 performs write and read operations for the signal C.

Each of the memory cells C11 to Cnn constituting the ROM cell area 11 has an EPROM cell transistor Tc constituting the memory cell of the EPROM and a transistor T
The gate of the transistor Tc is connected to one of the word lines WR1 to WRn, and the gate of the transistor Tc is connected to one of the word lines WR1 to WRn.
The drain is connected to one of the bit lines BL1 to BLn common to the EPROM cell region 12.

The structure of the cell transistor Tc and the switch S in the ROM cell region 11 will be explained with reference to FIG. and a gate 19 formed on the top of the aluminum wiring 20 connected to the ground GND.
For example, by connecting the memory cell C1 to the source 18,
One closed switch S is formed, and by not connecting the aluminum wiring 20 to the source 18, for example, an open switch S of the memory cell Cnn is formed. In addition,
The aluminum wiring 21 connected to the drain 17 is a bit line.

The cell transistor Tc in the ROM cell region 11 and the switch S in the closed or open state are formed in the same process as the cell transistor Tc in the EPROM cell region 12, and the ROM is processed based on the sense amplifier and write circuit 15. If cell information of "1" is written to all the cell transistors Tc in the cell area 11, the cell information of "1" will be written only to the cell transistor Tc whose source is connected to the switch S in the closed circuit state. Cell information can be read by the sense amplifier and write circuit 15.

Now, in the ROM and EPROM configured as described above, the cell transistor Tc constituting the ROM cell area 11 and the EPROM cell area 12 is composed of a common transistor, and is connected to the cell transistor Tc within the ROM cell area 11. The switch S connected to the ground G
The aluminum wiring 20 connected to ND is connected to the cell transistor T.
The ROM is configured depending on whether it is connected to the source of c.
The memory cells of the cell region 11 and the EPROM cell region 12 can be formed in the same process. And ROM
When initial setting is performed to write cell information of "1" to each memory cell C in the cell area 11, cell information based on the open or closed state of the switch S is set.

When writing and reading operations are performed on such ROMs and EPROMs, word lines WR1 to WRn are connected to memory cells C in the ROM cell area 11.
By selecting bit lines BL1 to BLn one by one, cell information is read from the selected memory cell C to the sense amplifier and write circuit 15 via the selected bit line. Then, the ROM cell area 11 and the EPROM
Both the cell region 12 and the EPROM cell transistor T
Therefore, even if cell information is read from the ROM cell area 11 via the bit lines BL1 to BLn common to the EPROM cell area 12 and the common sense amplifier 15, the level of the cell information is the same as that of the EPROM cell area 12.
Since it is at the same level as the cell information read from RO
A read operation from the M cell area 11 will not cause erroneous writing in the memory cell Tc in the EPROM cell area 12 due to soft write.

On the other hand, for the memory cell Tc in the EPROM cell area 12, the word line WE1 is connected as in the conventional example.
By selecting ~WEn and bit lines BL1 to BLn one by one, one memory cell Tc is selected, and the sense amplifier and write circuit 15 can write or read cell information into the memory cell Tc. Become.

Therefore, the read operation to the ROM cell area 11 and the write and read operations to the EPROM cell area 12 can be performed by the common sense amplifier and write circuit 15, so that the chip area can be reduced. In addition, the ROM cell area 11 and the EPRO
By configuring both the memory cells of M cell region 12 and EPROM cell transistors, both cell regions 11 and 1
Since the two operation tests can be performed in the same test process, the test time can also be shortened.

[0018]

Effects of the Invention As described in detail above, the present invention includes a ROM in which cell information is not rewritten and an EPROM in which cell information is rewritable, and enables the formation of these memory cells in a common process, and This provides an excellent effect of providing a semiconductor integrated circuit whose area can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a memory cell of a ROM according to one embodiment.

FIG. 4 is a block diagram showing a ROM configuration of one embodiment.

FIG. 5 is a block diagram showing a semiconductor integrated circuit including a ROM and an EPROM.

FIG. 6 is a circuit diagram showing a normal ROM.

FIG. 7 is a circuit diagram showing an EPROM.

[Explanation of symbols]

11 ROM cell area 12 EPROM cell area Tc cell transistor Vss Low potential side power supply S switch

Claims (1)

[Claims] [Claim 1] EPRO with rewritable cell information
A semiconductor integrated circuit in which an M cell region (12) and a ROM cell region (11) in which cell information is fixed are formed on the same semiconductor substrate, and a large number of memory cells forming the ROM cell region (11). is a cell transistor (Tc) having the same configuration as the cell transistor constituting the EPROM cell region (12), and a switch (Tc) for selecting whether or not to connect the source of the cell transistor (Tc) to the low potential side power supply (Vss). A semiconductor integrated circuit comprising: