CN101499449A - Semiconductor packaging construction on pin for wafer - Google Patents
Semiconductor packaging construction on pin for wafer Download PDFInfo
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- CN101499449A CN101499449A CN 200810006401 CN200810006401A CN101499449A CN 101499449 A CN101499449 A CN 101499449A CN 200810006401 CN200810006401 CN 200810006401 CN 200810006401 A CN200810006401 A CN 200810006401A CN 101499449 A CN101499449 A CN 101499449A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention relates to a semiconductor packaging structure with a wafer on a pin, comprising a plurality of lead frame pins which have a plurality of bearing strips, a plurality of bonding fingers, a plurality of connecting lines which connect the bearing strips and the playing lines. A wafer has a back surface for being attached on the bearing strips and electrically connected with the bonding fingers by a plurality of welding lines, wherein, at least one welding line crosses at least one connecting line which has no electrical connecting relationship. An insulating tape is pasted on the connecting lines, therefore, a routing short circuit packaged by COL can be avoided. Therefore, convenience is provided for the bearing strip configuration with the pins below the wafer in the COL package, and a wafer bearing can be further omitted or the size of the wafer bearing can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to a kind of wafer (Chip-On-Lead, semiconductor packaging structure COL) on pin.
Background technology
In the conventional semiconductor packages structure, the lead frame pin can be used as chip carrier and electrically switching, the encapsulation kenel mainly can be divided into two classes: pin is (Lead-On-Chip on wafer, LOC) or wafer (Chip-On-Lead on pin, COL), wherein so-called " pin is on the wafer " is pin to be attached on wafer be formed with on the active surface of integrated circuit; So-called " wafer is on pin " then attaches to the back side of wafer one section of pin.And electrically connect wafers and lead frame pin by a plurality of bonding wires that routing forms.Usually the bonding wire in " wafer is on pin " COL encapsulation can be longer on length with respect to the bonding wire in " pin is on wafer " LOC encapsulation, thus bonding wire be subjected to mould miscarry living displacement can be bigger.In addition, COL encapsulates employed lead frame pin, and the problem of supportive deficiency is easily arranged, thus still need at present by the both sides wafer holder with auxiliary supportive wafer, and then influenced the configuration space of lead frame pin under wafer.
See also Figure 1 and Figure 2, existing COL semiconductor packaging structure 100 comprises a plurality of lead frame pins 110, a wafer 120, a plurality of bonding wire 130 and an adhesive body 150.Those lead frame pins 110 respectively by the limit, two opposite sides of this adhesive body 150 toward interior extension, and the length of those lead frame pins 110 is asymmetric, wherein the lead frame pin 110 of long side is in order to this wafer 120 that is sticked.Those lead frame pins 110 have a plurality of routings and refer to 112 and a plurality of outer pin 114, and those outer pins 114 pass the side of this adhesive body 150 and extend bending outward, for to outer engagement.This wafer 120 has an active surface 121 and an opposing backside surface 122, and this active surface 121 is provided with a plurality of weld pads 123.This wafer 120 is to utilize pasting of a glutinous brilliant adhesive tape 160, makes this back side 122 of this wafer 120 can be arranged on those lead frame pins 110.Those bonding wires 130 electrically connect those weld pads 123 to those routings and refer to 112.This mould adhesive body 150 refers to 112 and those bonding wires 130 in order to seal this wafer 120, those routings, but appears those outer pins 114 of those lead frame pins 110.See also Figure 1 and Figure 2, because those lead frame pins 110 that are provided with this wafer 120 are hanging shape, lack enough supports, so need set up a plurality of wafer holders 170 to promote supportive to this wafer 120, avoid this wafer 120 in successive process, to produce the problem of displacement or inclination, make the configuration space of those lead frame pins 110 under this wafer 120 dwindle relatively.In addition, please consult shown in Figure 2 again, those weld pads 123 of this wafer 120 must corresponding arrangement with the arrangement position of those lead frame pins 110, roughly align with the bearing of trend of those lead frame pins 110 with the routing direction of guaranteeing those bonding wires 130, thus existing COL semiconductor packaging structure 100 not only the configuration space of those lead frame pins 110 under this wafer 120 dwindle and it innerly must extend the weld pad that is aligned to wafer.When the bond pad locations of wafer changed, the routing direction of bonding wire can produce the angle of inclination with the bearing of trend of lead frame pin, made that bonding wire is easy to the lead frame pin of the contiguous nothing electric connection of false touch and causes electric short circuit in routing and mould envelope process.
Summary of the invention
Main purpose of the present invention is, overcome the defective that prior art exists, and provide a kind of novel semiconductor packaging structure of wafer on pin, technical problem to be solved is to make it can avoid the routing short circuit of COL encapsulation, make things convenient for the carrier strip configuration of pin under wafer in the COL encapsulation, and then can omit wafer holder or the size of dwindling wafer holder, be very suitable for practicality.
Another object of the present invention is to, a kind of novel semiconductor packaging structure of wafer on pin is provided, technical problem to be solved is to make it can stop that glutinous brilliant glue refers to the routing of avoiding polluting to COL lead frame pin, so can adopt glutinous cheaply brilliant material, with the reduction packaging cost, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.The semiconductor packaging structure of a kind of wafer on pin according to disclosed mainly comprises a plurality of lead frame pins, a wafer, a plurality of bonding wire, an insulating tape and an adhesive body.The connecting line that those lead frame pins have that a plurality of carrier strip, a plurality of routing refer to, those carrier strip of a plurality of connection and those routings refer to.This wafer has an active surface and a back side, and this active surface is provided with a plurality of weld pads, and this back side is attached at those carrier strip of those lead frame pins.Those bonding wires connect those weld pads and those routings refer to, wherein a bonding wire strides across the connecting line of at least one no electrical connection.This insulating tape is covered on those connecting lines.Those routings that this adhesive body seals this wafer, those bonding wires, this insulating tape and those lead frame pins refer to and those connecting lines.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In aforesaid semiconductor packaging structure, this insulating tape can trim in those routings and refer to and be parallel with a side that this wafer is adjacent to those weld pads.
In aforesaid semiconductor packaging structure, can comprise a glutinous brilliant glue in addition, with this back side of sticking together this wafer to those carrier strip.
In aforesaid semiconductor packaging structure, this insulating tape can not be higher than this wafer.
In aforesaid semiconductor packaging structure, those lead frame pins can have more a plurality of outer pins, and it connects those carrier strip and is extended outward by this adhesive body by this wafer.
In aforesaid semiconductor packaging structure, can include a plurality of external terminals in addition, it is arranged under those carrier strip.
In aforesaid semiconductor packaging structure, this wafer can be a uncut wafer set.
In aforesaid semiconductor packaging structure, this insulating tape can be strip and has the single face stickiness.
By technique scheme, the semiconductor packaging structure of wafer of the present invention on pin has following advantage and beneficial effect at least:
1, the present invention can avoid the routing short circuit of COL encapsulation, makes things convenient for the carrier strip configuration of pin under wafer in the COL encapsulation, and then can omit wafer holder or the size of dwindling wafer holder.
2, Ben Fa can stop that glutinous brilliant glue refers to the routing of avoiding polluting to COL lead frame pin, thus can adopt glutinous cheaply brilliant material, to reduce packaging cost.
In sum, the present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and have the outstanding effect of enhancement than prior art, thus be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1: the schematic cross-section of existing semiconductor packaging structure.
Fig. 2: the schematic top plan view of existing semiconductor packaging structure lead frame pin before sealing.
Fig. 3: according to first specific embodiment of the present invention, the schematic cross-section of the semiconductor packaging structure of a kind of wafer on pin.
Fig. 4: according to first specific embodiment of the present invention, the schematic top plan view of this semiconductor packaging structure lead frame pin before sealing.
Fig. 5: according to first specific embodiment of the present invention, the sectional perspective schematic diagram of this semiconductor packaging structure lead frame pin before sealing.
Fig. 6: according to first specific embodiment of the present invention, the local schematic top plan view of this semiconductor packaging structure lead frame pin before sealing.
Fig. 7: according to first specific embodiment of the present invention, the schematic partial cross-sectional view of this semiconductor packaging structure before sealing.
Fig. 8: according to second specific embodiment of the present invention, the schematic cross-section of the semiconductor packaging structure of another kind of wafer on pin.
Fig. 9: according to second specific embodiment of the present invention, the schematic top plan view of lead frame pin in this semiconductor packaging structure.
Figure 10: according to second specific embodiment of the present invention, the schematic top plan view of this semiconductor packaging structure lead frame pin before sealing
100: semiconductor packaging structure 110: the lead frame pin
112: routing refers to 114: outer pin
120: wafer 121: active surface
122: the back side 123: weld pad
130: bonding wire 150: adhesive body
160: glutinous brilliant adhesive tape 170: wafer holder
200: semiconductor packaging structure 210: the lead frame pin
211: carrier strip 212: routing refers to
213: connecting line 213A: the connecting line of no electrical connection
214: outer pin 220: wafer
221: active surface 222: the back side
223: weld pad 230: bonding wire
230A: 231: the first ends of bonding wire
250: adhesive body 260: glutinous brilliant glue
300: semiconductor packaging structure 310: the lead frame pin
311: carrier strip 312: routing refers to
313: connecting line 313A: the connecting line of no electrical connection
314: outer connection pad 320: wafer
321: active surface 322: the back side
323: weld pad 330: bonding wire
330A: bonding wire 340: insulating tape
350: adhesive body 360: glutinous brilliant glue
370: external terminal
Embodiment
Reach technological means and the effect that predetermined goal of the invention institute standing grain is got for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of the semiconductor packaging structure of wafer on pin, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
According to first specific embodiment of the present invention, disclose a kind of wafer (chip on lead, semiconductor packaging structure COL) on pin.Wherein, be meant that at this indication " wafer is on pin " back side one surface of wafer active surface (promptly with respect to) of wafer is attached at the pin of lead frame, to reach the fixing of wafer.See also shown in Figure 3ly, the semiconductor packaging structure 200 of a kind of wafer on pin mainly comprises a plurality of lead frame pins 210, a wafer 220, a plurality of bonding wire 230, an insulating tape 240 and an adhesive body 250.
See also shown in Figure 4ly, those lead frame pins 210 are to be taken from same lead frame and to have that a plurality of carrier strip 211, a plurality of routing refer to 212, those carrier strip 211 of a plurality of connection refer to 212 connecting line 213 with those routings.Those carrier strip 211 are meant the section of those lead frame pins 210 below this wafer 220, extend to this wafer 220 toward in by the same side of this adhesive body 250, for this wafer 220 of carrying.And the interior pin that those carrier strip 211 are passed this wafer 220 comprises those connecting lines 213 and refers to 212 with those routings.See also shown in Figure 4, the width of those carrier strip 211 can refer to 212 width greater than those routings, providing this wafer 220 preferable Area of bearing, and can increase the wafer steadiness of this wafer 220 in fabrication steps such as follow-up routing step and/or sealing step, increase the product yield.In the present embodiment, those lead frame pins 210 can have more a plurality of outer pins 214, it connects those carrier strip 211 and passes the side of this adhesive body 250 (as shown in Figure 3) and extension bending outward, for being engaged to an external printed circuit board (not drawing among the figure).Those outer pin 214 bendables are converted into sea-gull pin (gull lead), or bendable is converted into other shapes, as I shape or J-shaped.
See also shown in Figure 3ly, this wafer 220 has an active surface 221 and a back side 222, and this active surface 221 is provided with a plurality of weld pads 223, and this back side 222 is attached at those carrier strip 211 of those lead frame pins 210.Those weld pads 223 are arranged in the single side of this wafer 220, and those routings refer to that 212 are adjacent to those weld pads 223, so as to shortening the length of wire bonding of those bonding wires 230.Particularly, this semiconductor packaging structure 200 can comprise a glutinous brilliant glue 260 in addition, with this back side 222 of sticking together this wafer 220 to those carrier strip 211.Preferably, as shown in Figure 7, by stopping of this insulating tape 240, this glutinous brilliant glue 260 can be selected from one of them of B rank colloid and liquid glue, to reduce packaging cost.Therefore, do not need to use existing wafer holder just can provide preferable supportive, more can make those lead frame pins 210 configuration space below this wafer 220 bigger, the design of those carrier strip 211 more has to be selected and variation widely.See also Fig. 5 and shown in Figure 6, first end, 231 those weld pads 223 of connection of those bonding wires 230 and second end 232 are connected in those routings and refer to 212, and wherein a bonding wire 230A strides across the connecting line 213A of at least one no electrical connection.See also shown in Figure 5ly, first end 231 of each bonding wire 230 can be initiating terminal, and this second end 232 then is a clearing end, and this wafer 220 to those routings of promptly serving as reasons refer to the forward routing of 212 (lead frame pins).But without restriction, those bonding wires 230 those routings of also can serving as reasons refer to that 212 (lead frame pins) are connected to the reverse routing of this wafer 220.
See also Figure 6 and Figure 7, this insulating tape 240 is covered on those connecting lines 213, can prevent that the above-mentioned bonding wire 230A that strides across pin is because of being subjected to the mould miscarriage and giving birth to displacement or saggingly causing and be positioned at its below and do not have the problem that the connecting line 213A of electrical connection is short-circuited.In the present embodiment but without restriction, this insulating tape 240 is for strip and have the single face stickiness and get final product, to attach to those connecting lines 213.Particularly, this insulating tape 240 can trim in those routings and refer to 212 and be parallel with a side that this wafer 220 is adjacent to those weld pads 223, can stop that this glutinous brilliant glue 260 pollutes to those routings to refer to 212.Preferably, this insulating tape 240 can reach the better glue effect of overflowing that prevents a little more than this glutinous brilliant glue 260.See also shown in Figure 7ly, this insulating tape 240 can not be higher than this wafer 220, not influence the camber of those bonding wires 230.See also shown in Figure 3, those routings of this adhesive body 250 these wafers 220 of sealing, those bonding wires 230, this insulating tape 240 and those lead frame pins 210 refer to 212 with those connecting lines 213, be subjected to the pollution of environmental contaminants to avoid said elements.
Therefore, those carrier strip 211 of this lead frame pin 210 can suitably be widened on demand to increase the Area of bearing of this wafer 220, and those connecting lines 213 of this lead frame pin 210 can be done suitable bending or inclination according to the demand of the wafer of different weld pads configuration, make things convenient for the COL encapsulation those lead frame pins 210 those carrier strip 211 be configured to the size omitting wafer holder or dwindle wafer holder.In addition, can effectively prevent the connecting line 213A of contiguous the no electrical connection of this bonding wire 230A false touch by the design of this insulating tape 240, with the routing short circuit of avoiding COL to encapsulate.In addition, can select for use the glutinous brilliant glue 260 of liquid state or the thick attitude of glue not have this glutinous brilliant glue 260 to reduce packaging cost pollutes to those routings and refers to 212 problem.
In second specific embodiment of the present invention, disclose the semiconductor packaging structure of another kind of wafer on pin, see also shown in Figure 8ly, this semiconductor packaging structure 300 mainly comprises a plurality of lead frame pins 310, a wafer 320, a plurality of bonding wire 330, at least one insulating tape 340 and an adhesive body 350.See also shown in Figure 9ly, those lead frame pins 310 have that a plurality of carrier strip 311, a plurality of routing refer to 312, those carrier strip 311 of a plurality of connection refer to 312 connecting line 313 with those routings.The inner of those lead frame pins 310 is extended by the limit, two opposite sides of this adhesive body 350 center line toward the back side 322 of this wafer 320 respectively, and those routings refer to 312 the inners away from those lead frame pins 310.Those lead frame pins 310 more can have a plurality of outer connection pads 314 (as shown in Figure 9), and it is formed at the non-bearing face of those carrier strip 311.Be meant that at this indication " non-bearing face " those carrier strip 311 are in order to attach another apparent surface of this wafer 320.See also shown in Figure 8ly, this wafer 320 has an active surface 321 and a back side 322, and this active surface 321 is provided with a plurality of weld pads 323, and this back side 322 is attached at those carrier strip 311 of those lead frame pins 310.See also shown in Figure 10ly, in the present embodiment, those weld pads 323 are arranged in the limit, two opposite sides of this wafer 320 respectively.Preferably, this wafer 320 can be a uncut wafer set, has comprised two or more but uncut integrated circuit (IC) wafer (dashed middle line of this wafer 320 is uncut wafer Cutting Road as shown in figure 10).This wafer 320 can utilize glutinous sticking together of brilliant glue 360 that this back side 322 of this wafer 320 is pasted to those carrier strip 311.Should glutinous brilliant glue 360 can be pre-formed this back side 322 in this wafer 320, for example (Die Attach Material, DAM), this glutinous brilliant glue 360 can produce adhesion to the crystalline substance of semi-solid preparation back of the body adhesive glue material when heating.Under suitable pressing pressure and heating-up temperature, these glutinous brilliant glue 360 energy gluings are to those carrier strip 311, so that this wafer 320 is attached at those carrier strip 311.
See also shown in Figure 10ly, those bonding wires 330 connect those weld pads 323 and refer to 312 with those routings, and wherein a bonding wire 330A strides across the connecting line 313A of at least one no electrical connection.This insulating tape 340 is covered on those connecting lines 313, and is contiguous and do not have the connecting line 313A of electrical connection and cause short circuit to avoid this bonding wire 330A false touch.See also shown in Figure 8, those routings of this adhesive body 350 these wafers 320 of sealing, those bonding wires 330, this insulating tape 340 and those lead frame pins 310 refer to 312 with those connecting lines 313.See also Fig. 8 and shown in Figure 9, this semiconductor packaging structure 300 can include a plurality of external terminals 370 in addition, and it is arranged at those outer connection pads 314 of those carrier strip 311.Therefore, the present invention can make things convenient for the configuration of the pin carrier strip 311 of COL encapsulation, electrically connecting the effect of the wafer that different weld pads arrange, and can avoid the routing short circuit of COL encapsulation.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (10)
1, the semiconductor packaging structure of a kind of wafer on pin is characterized in that it comprises:
A plurality of lead frame pins, the connecting line that have a plurality of carrier strip, a plurality of routing refers to and those carrier strip of a plurality of connection and those routings refer to;
One wafer has an active surface and a back side, and this active surface is provided with a plurality of weld pads, and this back side is attached at those carrier strip of those lead frame pins;
A plurality of bonding wires connect those weld pads and those routings refer to, wherein a bonding wire strides across the connecting line of at least one no electrical connection;
One insulating tape is covered on those connecting lines; And
One adhesive body, those routings that seal this wafer, those bonding wires, this insulating tape and those lead frame pins refer to and those connecting lines.
2, the semiconductor packaging structure of wafer according to claim 1 on pin is characterized in that this insulating tape wherein trims in those routings and refers to and be parallel with a side that this wafer is adjacent to those weld pads.
3, the semiconductor packaging structure of wafer according to claim 1 and 2 on pin is characterized in that it comprises a glutinous brilliant glue in addition, with this back side of sticking together this wafer to those carrier strip.
4, the semiconductor packaging structure of wafer according to claim 3 on pin is characterized in that wherein should sticking one of them that brilliant glue can be selected from B rank colloid and liquid glue.
5, the semiconductor packaging structure of wafer according to claim 3 on pin is characterized in that wherein should being brilliant back of the body adhesive glue material by glutinous brilliant glue.
6, the semiconductor packaging structure of wafer according to claim 1 on pin is characterized in that wherein this insulating tape is not higher than this wafer.
7, the semiconductor packaging structure of wafer according to claim 1 on pin is characterized in that wherein those lead frame pins have more a plurality of outer pins, and it connects those carrier strip and is extended outward by this adhesive body by this wafer.
8, the semiconductor packaging structure of wafer according to claim 1 on pin is characterized in that it includes a plurality of external terminals in addition, and it is arranged under those carrier strip.
9, the semiconductor packaging structure of wafer according to claim 1 on pin is characterized in that wherein this wafer is a uncut wafer set.
10, the semiconductor packaging structure of wafer according to claim 1 on pin is characterized in that wherein this insulating tape is strip and has the single face stickiness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810006401 CN101499449A (en) | 2008-02-02 | 2008-02-02 | Semiconductor packaging construction on pin for wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810006401 CN101499449A (en) | 2008-02-02 | 2008-02-02 | Semiconductor packaging construction on pin for wafer |
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| CN101499449A true CN101499449A (en) | 2009-08-05 |
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| CN 200810006401 Pending CN101499449A (en) | 2008-02-02 | 2008-02-02 | Semiconductor packaging construction on pin for wafer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800642A (en) * | 2011-05-25 | 2012-11-28 | 力成科技股份有限公司 | Multi-chip encapsulation structure with lead frame type contact finger |
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2008
- 2008-02-02 CN CN 200810006401 patent/CN101499449A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800642A (en) * | 2011-05-25 | 2012-11-28 | 力成科技股份有限公司 | Multi-chip encapsulation structure with lead frame type contact finger |
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