CN101499143B - Clock generating method in radio frequency identity recognition label - Google Patents
Clock generating method in radio frequency identity recognition label Download PDFInfo
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- CN101499143B CN101499143B CN2009100472124A CN200910047212A CN101499143B CN 101499143 B CN101499143 B CN 101499143B CN 2009100472124 A CN2009100472124 A CN 2009100472124A CN 200910047212 A CN200910047212 A CN 200910047212A CN 101499143 B CN101499143 B CN 101499143B
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Abstract
The invention provides a clock generating method in a RF identification label which includes steps as follows: (a) using the clock generator for generating a first clock frequency; (b) using a transducer according with the first clock frequency for generating a second clock frequency, wherein, the second clock frequency is higher than the first clock frequency. The clock frequency needed by an decoding counter and BLF generator must satisfy RFID agreement requirement, so the frequency is higher than the clock frequency needed by a state machine and other digital circuit. A label circuit using the clock generating method uses an oscillator with low frequency, and generates more clock signal by using a frequency multiplier. The label circuit using the clock generating method provided by the invention has lower power consumption.
Description
Technical field
The label that the present invention relates to the clock generating method in a kind of radio frequency identification tag and utilize clock generating method relates in particular to a kind of clock generating method that two kinds of different clocks are provided.
Background technology
(Radio Frequency Identification, RFID) technology is widely used in the application such as logistic track, authentication radio frequency identification.As shown in Figure 1, existing radio frequency identification system generally includes tag read-write equipment and label.Read write line is through its day alignment label data-signal of giving an order, and label receives the order data signal through its antenna and the order that receives is handled, afterwards through its day the alignment read write line postback data.
Common tag circuit comprises that the PAD, voltage doubling rectifing circuit, data recovery circuit, the data that link to each other with antenna postback circuit, clock generating circuit, digital circuit and memory circuitry.Voltage doubling rectifing circuit obtains the required energy of tag circuit to the induced voltage rectification that electromagnetic field produces on antenna.Data recovery circuit is handled to the received signal, removes the noise in the signal, obtains better signal waveform, further to handle.Data postback circuit and modulate the data that postback that digital circuit produces, and postback read write line through antenna.The clock generating circuit clocking offers digital circuit and uses with other circuit.Digital circuit is handled according to receiving order accordingly, and like the switch labels state, reading and writing memory data produces and postbacks data etc.Storer is used for the corresponding data in the storage tags circuit, can be EEPROM.
Received signal comprises read write line-label calibrating signal (RTcal), read write line-label calibrating signal (RTcal), data 0 signal and data 1 signal etc.Tag circuit comprises that also a decoding counter counts the length of these signals, and obtains corresponding count value.The decoding counter adopts the clock generating circuit clocking as clock signal.
Postback in the circuit in data, label is to be confirmed by the rate (DR) of removing in the order of the inquiry (Query) in TRcal signal and the radio frequency identification agreement to the link frequency (BLF) that postbacks of read write line.The count value of TRcal signal obtains the BLF count value divided by the rate of removing.Tag circuit also comprises a BLF maker, and it becomes the BLF signal to the clock signal frequency division that clock generating circuit generates according to the BLF count value.
As shown in Figure 2, oscillator 73 clockings 74 of existing 1.92MHz.All circuit that clock signal 74 offers in the digital circuit 10 use, and comprise decoding counter 54, BLF generator 55 and other digital circuit 53.
Yet RF identification identification agreement is stipulated communication data form and frequency between read write line and the label.The frequency of decoding counter and the employed clock signal of BLF generator need meet the regulation of RF identification identification agreement.Yet the used clock signal of other digital circuit in the tag circuit but need not satisfy the requirement of RF identification identification agreement.Therefore, when all circuit in the label all use the clock signal with a kind of frequency, can there be such problem; That is, when the frequency of the clock signal that clock generating circuit generated in the label is too low, possibly be discontented with the requirement of football association's view; And when the frequency of the clock signal that clock generating circuit generated in the label is too high; The power consumption of tag circuit is too high, cause that tag performance descends, thereby the performance of radio frequency identification system descends.
Therefore, how to reach RF identification identification agreement defined terms, reducing power consumption simultaneously is the problem that presses for solution.
Summary of the invention
Because the above-mentioned defective of prior art; The purpose of this invention is to provide a kind of radio frequency identification tag circuit power consumption that reduces and increase decoding allowance and the clock generating method that postbacks the link frequency allowance simultaneously; Make the data of correctly decoding tag circuit read write line sending to label to produce the link frequency that postbacks that satisfies the radio frequency identification protocol requirement, correctly postback data to read write line; Control the power consumption of label simultaneously; Improve the reading/writing distance of label, and bigger decoding allowance is arranged and postback the link frequency allowance, make tag circuit better robustness arranged noise.
For realizing above-mentioned purpose, the invention provides the clock generating method in a kind of radio frequency identification tag, comprise the steps: that (a) uses clock generator to generate first clock frequency; (b) use frequency converter to generate the second clock frequency according to said first clock frequency; Wherein, the frequency of said second clock frequency is higher than the frequency of said first clock frequency.
Preferable, said second clock frequency is used for the decoding counter and the BLF generator of said label, and said first clock frequency is used for other digital circuits of said label.
Preferable, said first clock frequency is 1.28MHz.
Preferable, said frequency converter is a varactor doubler.
Preferable, said frequency converter is a quadrupler.
Clock generation method of the present invention adopts frequency multiplier and obtains the frequency doubling clock signal that frequency is one times of the clock signal that produces of oscillator; Supply decoding counter and BLF generator to use, and the clock signal that state machine and other digital circuits still use oscillator to produce.Thus, adopt the oscillator of the tag circuit employing lower frequency of clock generating method of the present invention, adopt frequency multiplier to generate higher clock signal again.Therefore, adopt the tag circuit power consumption of clock generating method of the present invention to economize
Description of drawings
With reference to the description and the accompanying drawing of hereinafter preferred embodiment, can understand the present invention and purpose and advantage best, wherein:
Fig. 1 is the structural representation of radio frequency identification system;
Fig. 2 is the synoptic diagram of single clock generation circuit in the prior art;
Fig. 3 is the structural drawing of tag circuit of the present invention;
Fig. 4 is the coded format synoptic diagram of read write line to the data-signal of label;
Fig. 5 is the synoptic diagram of frame synchronizing signal;
Fig. 6 is the synoptic diagram of targeting signal;
Fig. 7 is a querying command form synoptic diagram;
Fig. 8 is the synoptic diagram of length counting to received signal;
Fig. 9 is for generating the synoptic diagram that postbacks link frequency;
Figure 10 is the synoptic diagram of clock generating circuit of the present invention;
Figure 11 is the synoptic diagram of digital circuit of the present invention;
Figure 12 is the synoptic diagram of frequency multiplier circuit structure;
Figure 13 is the synoptic diagram of decoding allowance;
Figure 14 is a kind of allowance synoptic diagram that postbacks link frequency;
Figure 15 is the another kind of allowance synoptic diagram that postbacks link frequency.
Embodiment
With reference to the accompanying drawing that the embodiment of the invention is shown, hereinafter will be described the present invention in more detail.
Circuit structure according to label 2 of the present invention is as shown in Figure 3, and they PAD5, voltage doubling rectifing circuit 6, data recovery circuit 7, data that comprise that antenna links to each other postback circuit 8, clock generating circuit 9, digital circuit 10 and memory circuitry 11.The induced voltage rectification that 6 pairs of electromagnetic fields of voltage doubling rectifing circuit produce on this antenna obtains the required energy of tag circuit.Data recovery circuit 7 is handled to the received signal, removes the noise in the signal, obtains better signal waveform, further to handle.Data postback circuit 8 and modulate the data that postback that digital circuit 10 produces, and postback read write line 1 (not shown) through this antenna.Digital circuit 10 comprises decoding counter 26 (not shown)s relevant with receiving signal decoding, BLF generator 28 (not shown)s and other digital circuit 27 (not shown)s relevant with BLF.Clock generating circuit 9 clockings offer digital circuit 10 and use.Digital circuit 10 is handled according to receiving order accordingly, postbacks data etc. like switch labels state, read-write memory 11 data, generation.Eeprom memory 11 is used for the corresponding data in the storage tags.
Read write line 1 can send start signal earlier usually when label 2 sends order, and then sends order data such as data 0,1, and these start signals are used for order is carried out synchronously or transmitted some link parameters, like frame synchronizing signal and targeting signal.Communicating by letter between read write line 1 and the label 2 based on standard length Tari 15.Fig. 4 shows the data of communicating by letter 0 signal 12 and the form of data 1 signal 13 between read write line 1 and the label 2.
Fig. 5 is the synoptic diagram of the frame synchronizing signal 16 in a kind of radio frequency identification agreement, and it comprises 18, one read write lines of 17, one data of a placeholder signal, 0 signal-label calibrating signal (RTcal) 19.
Fig. 6 is the synoptic diagram of the targeting signal 20 in a kind of radio frequency identification agreement, and it comprises a placeholder signal 17, data 0 signal 18, read write line-19 and labels of label calibrating signal (RTcal)-read write line calibrating signal (TRcal) 21.
Read write line among Fig. 5 and Fig. 6-label calibrating signal (RTcal) is used for distinguishing the length of data 0 and data 1, and the order data signal is decoded.Tag circuit need calculate pivot=RTcal/2.According to the comparative result of the length of the length of the data-signal that receives and pivot, the said data-signal of decoding.If said data length signal less than pivot, so just is decoded as 0; If data length greater than pivot, just is decoded as 1.
Label among Fig. 6-read write line calibrating signal (TRcal) is used for confirming that label 2 postbacks link frequency to read write line 1, BLF also with the radio frequency identification agreement in inquiry (Query) order 22 in DR (DevideRate removes rate) parameter 24 relevant.Targeting signal among Fig. 6 is the start signal of Query (inquiry) order in the radio frequency identification agreement.Frame synchronizing signal among Fig. 5 is the start signal of other order except that the Query order in the radio frequency identification agreement.The form of querying command 22 is as shown in Figure 7, and it comprises command code 23, DR parameter 24 and other parameter 25.The value of DR24 possibly be 8 or 64/3.The relation of BLF and TRcal and DR is:
As shown in Figure 8, decoding counter 26 receives the signal 58 that comprises RTcal signal 19, TRcal signal 21, data 0 signal 12 and data 1 signal 13 etc.Clock generating circuit 9 clockings 29 of label 2 are as the clock signal of decoding counter 26.Decoding counter 26 is counted the length of these signals, and obtains corresponding count value.The count value of RTcal signal 19 is stored in the RTcal register 191.The count value of TRcal signal 21 is stored in the TRcal register 211.Count value in the RTcal register 191 is used for calculating pivot.Count value in the TRcal register 211 is used for calculating BLF count value 58, and computing method are shown below:
As shown in Figure 9, BLF maker 28 is according to BLF count value 58, and clock signal 29 frequency divisions that generate clock generating circuit 9 become BLF signal 28.
Shown in figure 10, clock generating circuit 9 comprises that frequency is oscillator 91 and the frequency multiplier 92 of 1.28MHz.Oscillator 91 generating clock signals 30.Clock signal 30 produces frequency doubling clock signal 29 through frequency multiplier 92.The frequency of frequency doubling clock signal 29 is twices of the frequency of clock signal 30.The frequency doubling clock signal 29 that frequency multiplier 92 produces offers decoding counter 26 and the clock signal of BLF generator 28 as them.The clock signal 30 that oscillator 91 produces is as the clock signal of other digital circuit 27.Oscillator 91 is the example of clock generator, and frequency multiplier 92 is the example of frequency converter.
The structure of frequency multiplier 92 is shown in figure 11.Clock signal 30 obtains delay clock signals 71 after handling through delay circuit 70.Clock signal 30 and delay clock signals 71 carry out through XOR circuit 72 obtaining frequency doubling clock signal 30 after the XOR.
As the technician in present technique field should understand, the concrete numerical value in the present embodiment only is illustrative, limits protection scope of the present invention absolutely not.For example, oscillator 91 clockings 56 can be the required clock frequency 1/4 of decoding counter 54 and BLF generator 55, and adopt quadrupler that its conversion is used for decoding counter 54 and BLF generator 55.
The existing work of describing digital circuit 10 according to Figure 12.
Shown in figure 12, comprise decoding counter 54 in the digital circuit 10.Decoding counter 54 58 length is to received signal counted.Receive signal 58 and comprise RTcal signal 19, TRcal signal 21, data 0 signal 12, data 1 signal 13 etc.The count results of the length of 58 pairs of RTcal signals 19 of decoding counter is a RTcal count value 63.RTcal count value 63 is obtained pivot count value 62 divided by 2.The count results of the length of 58 pairs of data-signals of decoding counter (possibly be data 0 signal 12 or data 1 signal 13) is a data-signal count value 60.Comprise comparer 61 in the digital circuit 10.Comparer 61 is pivot count value 62 and data-signal count value 60 relatively.If the data-signal count value less than pivot count value 62, just is decoded into data 0 to data-signal; If data-signal count value 60 greater than pivot count value 62, just is decoded into data 1 to data-signal.The a plurality of data 0 of coming out of decoding are successively formed data 0/1 stream 65 with data 1.Data 0/1 stream 65 is sent to state machine and other digital circuit 27.State machine carries out handled with other digital circuit 27 according to data 0/1 stream 65, postbacks data 59 etc. like execution of command operations, redirect tag state, read-write memory 11 and generation.Comprise querying command 22 if receive in the signal 58, state machine can be from data 0/1 stream 65 from extracting DR parameter 66 with other digital circuit 27.The count results of the length of 58 pairs of TRcal signals 21 of decoding counter is a TRcal count value 64.Digital circuit 10 is calculated 69 circuit according to DR parameter 66 and TRcal count value 64 through BLF and is calculated BLF count value 51 through the method for Figure 10.Comprise BLF generator 55 in the digital circuit 10.BLF generator 55 carries out frequency division according to 51 pairs of frequency doubling clock signals of BLF count value 57 and produces BLF signal 68.BLF signal 68 offers state machine and other digital circuit 27 and is used for producing and postbacks data 59.State machine possibly carry out read-write operation to storer 11 with other digital circuit 27.Decoding counter 54 in the digital circuit 10 adopts frequency doubling clock signal 57 with BLF generator 55.State machine in the digital circuit 10 adopts clock signal 56 with other digital circuit 27.
In order to satisfy the requirement of radio frequency identification agreement, the frequency of the clock signal 30 that the frequency ratio of the clock signal 74 that the oscillator 73 in the existing tag circuit shown in Figure 2 produces oscillator 91 shown in Figure 10 produces is high.In the present embodiment, the frequency of the clock signal 30 that oscillator 91 produces is 1.28MHz.Therefore the digital circuit power consumption of the tag circuit of existing 1.92MHz is higher than the power consumption of 1.28MHz digital circuit, and this is because the power consumption and the clock frequency of digital circuit are directly proportional.Thus, oscillator 73 is higher than the power consumption of oscillator 91.This makes the tag circuit ratio that adopts oscillator 73 shown in Figure 2 adopt the poor performance of the tag circuit of oscillator 91 shown in Figure 10.
The performance that Figure 13,14 and 15 shows tag circuit that uses oscillator 91 of the present invention and the tag circuit that uses existing oscillator 73 relatively can compare.Solid line among Figure 13 is the decoding allowance of the tag circuit of use oscillator 91 of the present invention, and dotted line is for using the decoding allowance of the tag circuit that has oscillator 73 now.Solid line among Figure 14 is for using the BLF allowance of tag circuit when DR=8 of oscillator 91 of the present invention, and dotted line is for using the BLF allowance of tag circuit when DR=8 of existing oscillator 73.Solid line among Figure 15 is for using the BLF allowance of tag circuit when DR=64/3 of oscillator 91 of the present invention, and dotted line is for using the BLF allowance of tag circuit when DR=64/3 of existing oscillator 73.Can know by Figure 13,14 and 15, obtain the frequency doubling clock signal that frequency is one times of the clock signal that produces of oscillator owing to clock generating method of the present invention adopts frequency multiplier, for decoding counter and the use of BLF generator.Therefore the clock frequency of counter and BLF generator of decoding is 2.56MHz, greater than the 1.92Mhz that uses in the prior art.Thus, use decoding allowance and the BLF allowance of tag circuit of oscillator 91 of the present invention bigger, the noise of tag circuit is had better robustness than the tag circuit that uses existing oscillator 73.
Present embodiment has following advantage.
(1) clock generation method of the present invention adopts frequency multiplier and obtains the frequency doubling clock signal that frequency is one times of the clock signal that produces of oscillator; Supply decoding counter and BLF generator to use, and the clock signal that state machine and other digital circuits still use oscillator to produce.Thus, adopt the oscillator of the tag circuit employing lower frequency of clock generating method of the present invention, adopt frequency multiplier to generate higher clock signal again.Therefore, adopt the tag circuit power consumption of clock generating method of the present invention to economize.
(2) clock generation method of the present invention adopts frequency multiplier and obtains the frequency doubling clock signal that frequency is one times of the clock signal that produces of oscillator, for decoding counter and the use of BLF generator.Therefore the clock frequency of counter and BLF generator of decoding is 2.56MHz, greater than the 1.92Mhz that uses in the prior art.Therefore, adopt the tag circuit of clock generation method of the present invention bigger decoding allowance to be arranged and postback the link frequency allowance.
(3) because the power consumption of clock generation method of the present invention is lower, therefore adopt the reading/writing distance of the tag circuit of clock generation method of the present invention to be increased.
(4) clock generation method of the present invention adopts frequency multiplier and obtains the frequency doubling clock signal that frequency is one times of the clock signal that produces of oscillator; Use for decoding counter and BLF generator, and the clock signal that state machine and other digital circuits still use oscillator to produce.Because two frequencys multiplication than the less easy realization of expense, have therefore further been saved power consumption.
The technician in present technique field should be understood that the present invention can not break away from spirit of the present invention and scope with many other concrete forms realizations.All technician in the art all should be in claim protection domain of the present invention under this invention's idea on the basis of existing technology through the available technical scheme of logical analysis, reasoning, or a limited experiment.
Claims (9)
1. the clock generating method in the radio frequency identification tag is characterized in that, comprises the steps:
(a) use clock generator to generate first clock frequency;
(b) use frequency converter to generate the second clock frequency according to said first clock frequency;
Wherein, The frequency of said second clock frequency is higher than the frequency of said first clock frequency; And said second clock frequency is used for the decoding counter of said label and postbacks the link frequency generator, and said first clock frequency is used for other digital circuits of said label.
2. clock generating method as claimed in claim 1 is characterized in that, said first clock frequency is 1.28MHz.
3. clock generating method as claimed in claim 1 is characterized in that, said frequency converter is a varactor doubler.
4. clock generating method as claimed in claim 1 is characterized in that, said frequency converter is a quadrupler.
5. label that adopts the said clock generating method of claim 1; Comprise that the pad cell, voltage multiplying rectifier unit, digital circuit unit, memory cell, clock generation unit and the data that link to each other with antenna postback the unit; Wherein said voltage multiplying rectifier unit obtains the required energy of said label to the induced voltage rectification that electromagnetic field produces on said antenna; Said digital circuit unit comprise the decoding counter relevant with receiving signal decoding, with postback link frequency relevant postback link frequency generator and other digital circuit unit, said digital circuit unit basis receives order and handles accordingly; Said data postback the unit and modulate the data that postback that said digital circuit unit produces, and postback through said antenna; Said clock generation unit clocking offers said digital circuit unit; Corresponding data in the said memory cell stores label,
Said label is characterised in that said clock generation unit comprises clock generator and frequency converter,
Wherein, said clock generator generates first clock frequency;
Said frequency converter generates the second clock frequency according to said first clock frequency; And
Said second clock frequency is higher than said first clock frequency.
6. label as claimed in claim 5 is characterized in that, said second clock frequency is used for the decoding counter of said digital circuit unit and postbacks the link frequency generator, and said first clock frequency is used for other digital circuits of said digital circuit unit.
7. label as claimed in claim 5 is characterized in that, said clock generator is the oscillator of 1.28MHz.
8. label as claimed in claim 5 is characterized in that, said frequency converter is a varactor doubler.
9. label as claimed in claim 5 is characterized in that, said frequency converter is a quadrupler.
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| CN2009100472124A CN101499143B (en) | 2009-03-06 | 2009-03-06 | Clock generating method in radio frequency identity recognition label |
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| CN2009100472124A CN101499143B (en) | 2009-03-06 | 2009-03-06 | Clock generating method in radio frequency identity recognition label |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102156899B (en) * | 2011-04-25 | 2013-08-14 | 广州中大微电子有限公司 | Clock management unit of RFID tag chip |
| CN105389612A (en) * | 2015-11-09 | 2016-03-09 | 中国人民解放军国防科学技术大学 | Circuit and method for realizing reverse link frequency in electronic tag chip |
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| US20050225434A1 (en) * | 2004-04-13 | 2005-10-13 | Diorio Christopher J | Method and system to generate modulator and demodulator clock signals within an RFID circuit utilizing a multi-oscillator architecture |
| CN1793067A (en) * | 2006-01-11 | 2006-06-28 | 张国财 | Cultivating non maggot fly kind large white larva by livestock poultry excrement and biological flowers organic manure thereof |
| CN1965324A (en) * | 2004-04-08 | 2007-05-16 | 3M创新有限公司 | Variable frequency radio frequency identification (RFID) tags |
| US20070273485A1 (en) * | 2006-05-08 | 2007-11-29 | Texas Instruments Incorporated | Systems and methods for low power clock generation |
| CN101346734A (en) * | 2005-12-22 | 2009-01-14 | Lg伊诺特有限公司 | RFID system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1965324A (en) * | 2004-04-08 | 2007-05-16 | 3M创新有限公司 | Variable frequency radio frequency identification (RFID) tags |
| US20050225434A1 (en) * | 2004-04-13 | 2005-10-13 | Diorio Christopher J | Method and system to generate modulator and demodulator clock signals within an RFID circuit utilizing a multi-oscillator architecture |
| CN101346734A (en) * | 2005-12-22 | 2009-01-14 | Lg伊诺特有限公司 | RFID system |
| CN1793067A (en) * | 2006-01-11 | 2006-06-28 | 张国财 | Cultivating non maggot fly kind large white larva by livestock poultry excrement and biological flowers organic manure thereof |
| US20070273485A1 (en) * | 2006-05-08 | 2007-11-29 | Texas Instruments Incorporated | Systems and methods for low power clock generation |
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