CN101488503B - Operating method for non-volatile storage element - Google Patents
Operating method for non-volatile storage element Download PDFInfo
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- CN101488503B CN101488503B CN2009100062632A CN200910006263A CN101488503B CN 101488503 B CN101488503 B CN 101488503B CN 2009100062632 A CN2009100062632 A CN 2009100062632A CN 200910006263 A CN200910006263 A CN 200910006263A CN 101488503 B CN101488503 B CN 101488503B
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Abstract
The invention relates to an operation method of a nonvolatile memory element. The memory element comprises a substrate, a grid, an insulating layer, a charge storage layer and a multilayer tunneling dielectric construction. The substrate is provided with a pair of source/drain electrode region divided by channel region. The grid is arranged on the substrate. The insulating layer is arranged on the channel region. The charge storage layer is arranged on the insulating layer. The multilayer tunneling dielectric construction is arranged between the charge storage layer and the grid. By applying negative bias on the grid, a plurality of first type carriers enter the charge storage layer via the multilayer tunneling dielectric construction by tunneling from the grid; and by applying forward bias on the grid, a plurality of second type carriers enter the charge storage layer via the multilayer tunneling dielectric construction by tunneling from the grid.
Description
This case is that application number is 200610090051.3 divisions in first to file
Technical field
The invention relates to a kind of method of operation of memory element, and particularly relevant for a kind of method of operation that can non-volatile memory device.
Background technology
Nonvolatile memory (Non-volatile memory, " NVM ") be a kind of can be after removing power supply the semiconductor memory of stored information constantly still.NVM comprises the mask read only memory (Mask ROM), programmable read only storage (PROM), the erasable programmable read only memory (EPROM), can remove programmable read only storage (EEPROM) and flash memory (Flash memory) by electricity.Nonvolatile memory is widely used for semi-conductor industry and research and development prevent one type of memory that programming data is lost.Usually, can require programme, read and/or wipe based on the final use of equipment to nonvolatile memory, and store both program data for a long time.
Flash memory generally includes the memory cell array that is arranged in the ranks shape.Each memory cell comprises a golden oxygen half (MOS) transistor, and MOS transistor has grid, drain electrode, source electrode and by the raceway groove that defines between drain electrode and the source electrode.Grid is corresponding to word line, and drain/source is corresponding to the bit line of memory array.At present the grid of flash memory is generally double-grid structure, has comprised grid and floating grid, and wherein, floating grid is clipped between the two layers of dielectric layer and resistance falls into carrier such as electronics, with " stylizing " this memory cell.In other words, tunneling oxide layer is to be formed on the raceway groove in conventional memory cells; Floating grid is formed on the tunneling oxide layer; Dielectric layer is formed on the floating grid between lock; And grid is formed between lock on the dielectric layer again.
When stylizing, on selected word line and bit line, apply one group of bias voltage that stylizes.One or more memory cell corresponding to selected word line and bit line are imposed bias voltage under the state of stylizing.With regard to single memory cell, its source electrode has applied different bias voltages with drain electrode, and has formed electric field along its raceway groove, makes electronics obtain enough energy by this to wear tunnel first dielectric layer, and the entering floating grid also is stored in wherein.Owing to stored electronics in the floating grid, changed the threshold voltage of memory cell, therefore, can learn by the change of threshold voltage whether memory cell is stylized.
Reading cells will apply and read bias voltage, and reads the electric current through memory cell by sensing element.If memory cell is stylized, or have electronics to be stored among its floating grid, then its size of current can be different from those memory cell that is stylized.Therefore, according to the size of current that measures, sensing element just can be learnt the state of each memory cell.
Desire to wipe the message in the flash memory cell, need apply it and wipe bias voltage, the electronics that forces storage is worn tunnel through known mechanism like FN, in floating grid, wears tunnel and goes out.
Because the tunneling oxide layer in the present nonvolatile memory is formed on the raceway groove, the beak phenomenon that shallow slot isolation structure caused has a strong impact on tunneling oxide layer, makes the reliability of element descend, and therefore, element is difficult for miniaturization.On the other hand, present nonvolatile memory lures that stylizing of electrons tunnel or erase operation need high voltage into, therefore very power consumption, and also speed has to be hoisted.
Therefore, in the technology of the element of memory cell design and memory cell array, need to avoid the method for the operation store unit of the problems referred to above.
Summary of the invention
The objective of the invention is to propose a kind of method of operation of memory element, the beak phenomenon that its memory element can avoid shallow slot isolation structure to cause is fast for influence and its service speed that reliability caused.
The present invention includes the method for operation of memory element, this memory element comprises substrate, grid, insulating barrier, electric charge storage layer and multilayer tunneling dielectric construction.Substrate has two sources/drain region, separates through channel region.Grid is arranged on the substrate.Insulating barrier is arranged on the channel region.Electric charge storage layer is arranged on the insulating barrier.Wearing the tunnel dielectric structure is arranged between electric charge storage layer and the grid.Be pressed on grid through applying negative bias; Make a plurality of first type carriers wear tunnel via multilayer tunneling dielectric construction and get into electric charge storage layer from grid; And, make a plurality of second type carriers wear tunnel via the multilayer tunneling dielectric construction grid and get into electric charge storage layer from grid through applying forward bias in grid.
Said according to the embodiment of the invention, above-mentioned back bias voltage is-16 to-20 volts; Above-mentioned positive bias is 14 to 16 volts.
Said according to the embodiment of the invention, the above-mentioned tunnel dielectric structure of wearing comprises that the first ability rank, second can rank and the 3rd ability rank.The first ability rank are positioned at the primary importance near grid, and are lower than the valence band ability rank of grid.The second ability rank are positioned at the second place apart from grid 8-30 dust, and when not applying bias voltage, the second ability rank are between the valence band ability rank of the first ability rank and grid.The 3rd ability rank, one the 3rd position between said second position and above-mentioned charge storage layer, and when not applying bias voltage, the 3rd ability rank are lower than the valence band ability rank of above-mentioned grid and are lower than the valence band ability rank of above-mentioned charge storage layer.
Said according to the embodiment of the invention, the above-mentioned tunnel dielectric structure of wearing is for wearing the tunnel dielectric structure.
Said according to the embodiment of the invention, above-mentioned multilayer tunneling dielectric construction comprises three layers of monoxide/nitride/oxide.
Said according to the embodiment of the invention, above-mentioned multilayer tunneling dielectric construction comprises three layers of silicon monoxide/three layers of nitrogenize silicon/oxidative silicons or silicon monoxide/alumina/silica.
Said according to the embodiment of the invention, the material of above-mentioned insulating barrier comprises silica or aluminium oxide.
Said according to the embodiment of the invention, the material of above-mentioned charge storage layer comprises silicon nitride, silicon oxynitride, HfO
2, HfSi
xO
yOr Al
2O
3
The invention provides a memory element comprising a substrate, a gate insulating member, a charge storage layer and the FN tunneling member.Substrate has two sources/drain region and separates through channel region.Grid is arranged on the substrate.Insulating component is arranged on the substrate, electric charge is mended caught between layer and substrate to insulate, with the tunnel of wearing in restriction electronics and hole.Electric charge storage layer is arranged between insulating component and the grid, and electric charge storage layer is mended a threshold voltage of catching electric charge decision memory element.FN wears the tunnel member and is arranged between electric charge storage layer and the grid, under positive bias, through+FN hole wearing tunnel mechanism; Make the hole wear tunnel to electric charge storage layer from grid; To be reduced in the threshold voltage in programming or the erase operation, and under back bias voltage, wear tunnel mechanism through-FN; Make electronics wear tunnel to this electric charge storage layer, with the threshold voltage in another operation that is increased in programming or wipes from this grid grid.
Said according to the embodiment of the invention, the material of above-mentioned charge storage layer comprises silicon nitride, silicon oxynitride, HfO
2, HfSi
xO
yOr Al
2O
3
For let above-mentioned and other purposes of the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended graphicly, elaborates as follows.
Description of drawings
Fig. 1 is the generalized section according to the memory cell that the embodiment of the invention illustrated.
Fig. 2 carries out-generalized section of FN operation according to memory cell that the embodiment of the invention illustrated.
Fig. 3 carries out-threshold voltage and the time relation figure of FN operation according to memory cell that the embodiment of the invention illustrated.
Fig. 4 carries out+generalized section of FN operation according to memory cell that the embodiment of the invention illustrated.
Fig. 5 carries out+threshold voltage and the time relation figure of FN operation according to memory cell that the embodiment of the invention illustrated.
Fig. 6 is the theoretical energy band diagram of each layer under low electric field according to the memory cell that the embodiment of the invention illustrated.
Fig. 7 is the theoretical energy band diagram of each layer under high electric field according to the memory cell that the embodiment of the invention illustrated.
Fig. 8 illustrates PMOS storage element under 10000 P/E circulation, the stylize threshold voltage and the time relation figure of state and erase status.
Fig. 9 illustrate the PMOS storage element 10000 times, 1000 times, 100 times with 1 P/E circulation under stylize state and erase status read voltage V
GWith electric current I
DGraph of a relation.
Figure 10 illustrates NMOS storage element under 10000 P/E circulation, the stylize threshold voltage and the time relation figure of state and erase status.
Figure 11 illustrate the NMOS storage element 10000 times, 1000 times, 100 times with 1 P/E circulation under stylize state and erase status read voltage V
GWith electric current I
DGraph of a relation.
Figure 12 is the top view according to the memory array that the embodiment of the invention illustrated.
Figure 13 illustrates along the profile of the partial array of the orientation I-I tangent line of Figure 12.
Figure 14 illustrates the profile of the partial array of channel width dimension II-II tangent line in Figure 12.
Figure 15 illustrates the equivalent circuit diagram according to a memory array of the present invention's one preferred embodiment.
Figure 16,17,18 is respectively the equivalent circuit diagram of stylizing, wiping of p raceway groove NAND array structure of the present invention and read operation.
Figure 19,20,21 is respectively the equivalent circuit diagram of stylizing, wiping of n raceway groove NAND array structure of the present invention and read operation.
100,400: memory cell
101,401: Semiconductor substrate
102,402: diffusion region, source/drain regions
104,404: diffusion region, source/drain regions
106,406: channel region
140,440: insulating barrier
150,450: charge storage/immersed layer
160,460: multilayer tunneling dielectric construction
162,462: the first tunneling dielectric layers
164,464: tunnel energy barrier layer is worn in low positive hole
166,466: the second tunneling dielectric layers
170,470: grid
180,480: stack layer
490: shallow trench isolation
Embodiment
At present will be in detail with reference to the present invention and preferred embodiment thereof, instance of the present invention has been described in the accompanying drawing.It should be noted that accompanying drawing is to be extremely the form simplified and not according to accurate scale.In any possibility part, same reference numbers can be used in institute's drawings attached, censures identical or similar portions.According to the disclosure of this paper, be merely convenience and clear for the purpose of, for accompanying drawing service orientation term, for example top, bottom, left and right, upper and lower, top, below ... under, rear portion and front portion, be usefulness corresponding to accompanying drawing.To the description of accompanying drawing, attach any way that does not clearly propose in claims after should not be construed as and limit category of the present invention below this type direction term combines.Although the disclosure of this paper is with reference to some illustrative example; But should be appreciated that; These embodiment are not to be in order to restriction as instance; And processing procedure described herein and structure do not comprise the complete manufacturing process of making whole IC, but under can combining in the field multiple IC manufacturing technology known or that developing put into practice the present invention.
The invention provides a kind of utilization and wear tunnel mechanism, make electronics/positive hole flow into charge storage layer, cause the threshold voltage rising/decline of memory cell, carry out stylizing or erase operation of memory cell from the grid of memory cell by-FN/+FN.This memory element can comprise the memory array that contains p raceway groove/n channel memory cell matrix.Memory array has comprised that with the p raceway groove of NAND (and not b gate type) construction/n raceway groove NVM unit according to the memory of method operation of the present invention, the application that can supply flash memory has the very high disposal ability that stylizes.
Fig. 1 illustrates the cellular construction according to a kind of illustrative memory cell 100 of the present invention's one preferred embodiment.Please, Semiconductor substrate 101 is provided, has two diffusion regions 102,104 in this substrate 101 with reference to Fig. 1.Semiconductor substrate 101 can comprise any conventional semiconductor material, for example silicon.In one embodiment, substrate 101 is the n conductivity type; And diffusion region 102,104 is the p conductivity type.In another embodiment, substrate 101 is the p conductivity type; And diffusion region 102,104 is the n conductivity type.In one embodiment, substrate 101 is the p conductivity type, and has formed n conductivity type wellblock (not illustrating) in the substrate 101, and diffusion region 102,104 then is the p conductivity type and is formed in the n conductivity type wellblock.In another embodiment, substrate 101 is the n conductivity type, and has formed p conductivity type wellblock (not illustrating) in the substrate 101, and diffusion region 102,104 then is the n conductivity type and is formed in the p conductivity type wellblock.Diffusion region 102, the Semiconductor substrate between 104 101 are channel region 106.Forming stack layer 180 on the channel region 106.Stack layer 180 comprises insulating barrier 140, charge storage layer 150, multilayer tunneling dielectric construction 160 and grid 170.Insulating barrier 140 is preferable can to comprise silicon dioxide.The charge storage layer 150 preferable layer charges that comprise are absorbed in material, for example are silicon nitrides.It has comprised that first tunneling dielectric layer 162, low positive hole wear the tunnel energy barrier layer 164 and second tunneling dielectric layer 166 multilayer tunneling dielectric construction 160.Low positive hole wear tunnel energy barrier layer (small hole tunneling barrier height layer) 164 for positive hole wear tunnel energy barrier value less than or approximate the material layer of silicon dioxide.The material that the tunnel energy barrier is worn in low positive hole preferably less than or approximate 4.5eV person.The material that the tunnel energy barrier is worn in better low positive hole is to be less than or equal to 1.9eV person.Preferable multilayer tunneling dielectric construction 160 can comprise ultra-thin oxide-nitride thing-oxide (ONO) structure.Grid 170 can comprise polysilicon, metal, metal silicide or above-mentioned combination.Memory element 100 comprises diffusion region 102,104 and grid 170, and to constitute MOS transistor, wherein the diffusion region 102,104, in order to the source/drain regions as MOS transistor.
Comprised Semiconductor substrate 101 according to memory cell of the present invention.Any substrate material that is suitable for being used in semiconductor element can be used.In a plurality of preferred embodiments of the present invention, Semiconductor substrate 101 comprises the silicon material.Through the Silicon Wafer that standard technique is prepared, can use as substrate 101.For instance, can prepare suitable silicon chip by following technology: from being called the small crystal growth silicon of crystal seed; From the hyperpure silicon of fusion, regain to produce column crystal with rotation mode lentamente; Then be sliced into thin dish; And after the section that it is levigate, polishing (as smooth as the mirror) and cleaning.
Insulating barrier 140, charge storage layer 150, multilayer tunneling dielectric construction 160 can be to be formed at least on the channel region 106 of substrate 101 with grid 170.
The material of insulating barrier 140 can silica or aluminium oxide, and its thickness is about 30 dust to 100 dusts.In one embodiment, insulating barrier 140 is 54 dusts or thicker silicon oxide layer.The formation method of silicon oxide layer can adopt thermal oxidation method.
The material of charge storage layer 150 is silicon nitride, silicon oxynitride, HfO for example
2, HfSi
xO
yOr Al
2O
3, its thickness is about 30 dust to 100 dusts.In one embodiment, charge storage layer 150 is the right silicon nitride layers of 80 Izods.The formation method of silicon nitride layer can adopt Low Pressure Chemical Vapor Deposition.
Multilayer tunneling dielectric construction 160 allows that positive hole in the wiping/stylize when operation of memory element, wears tunnel to charge storage layer 150 from grid 170.At non-volatile memory cells of the present invention, the electric charge of preferable multilayer tunneling dielectric construction 160 is absorbed in usefulness almost can be out in the cold, more preferably is, can be when storage operation, and resistance falls into electric charge.Multilayer tunneling dielectric construction 160 is preferably and comprises that tunnel energy barrier layer 164 is worn in the low positive hole of one deck and double team hangs down first tunneling dielectric layer 162 and second tunneling dielectric layer 166 that tunnel energy barrier layer 164 is worn in positive hole.At this; Have the material of wearing tunnel energy barrier layer 164 in low positive hole and be meant suitable dielectric material, it can allow when electric field exists and wear tunnel, but when not imposing bias voltage; Can prevent directly to wear tunnel; And can be enough thin with depositing, making itself can not become charge immersing layer, for example is silicon nitride or aluminium oxide.The valence band of the material of first tunneling dielectric layer 162 and second tunneling dielectric layer 166 can be worn the valence band ability rank of tunnel energy barrier layer 164 greater than hanging down positive hole in rank, and the conduction band of the material of first tunneling dielectric layer 162 and second tunneling dielectric layer 166 ability rank can rank less than hanging down the conduction band of wearing tunnel energy barrier layer 164 in positive hole.In some preferred embodiments of the present invention, it for example is nitride such as silicon nitride layer that tunnel energy barrier layer 164 is worn in low positive hole; And first tunneling dielectric layer 162 and second tunneling dielectric layer 166 that tunnel energy barrier layer 164 is worn in the low positive hole of double team for example are oxide such as silicon oxide layer, and promptly multilayer tunneling dielectric construction 160 comprises the ONO structure.Because the positive hole energy barrier very low (about 1.9eV) of general silicon nitride under high electric field, may make positive hole to penetrate.In this simultaneously, wear the gross thickness of tunnel dielectric, like the ONO structure, that can prevent electronics under the low electric field directly wears tunnel.In one example, this effect makes memory element not only can provide fast positive hole to wear tunnel and wipes, can also during preservation reduce or remove the escape of electric charge.
In some preferred embodiments of the present invention, the thickness of wearing first tunneling dielectric layer 162 in the tunnel dielectric structure 160 is 10 dust to 30 dusts; The thickness that tunnel energy barrier layer 164 is worn in low positive hole is 15 dust to 30 dusts; The thickness of second tunneling dielectric layer 166 is 8 dust to 30 dusts.In a particular instance, wear tunnel dielectric structure 160 and be bottom oxide/middle silicon nitride layer/top silicon oxide layer (O/N/O) three-decker, wherein the thickness of end silicon oxide layer is 20 dusts; The thickness of middle silicon nitride layer is 25 dusts; The thickness of top silicon oxide layer is 15 dusts.
Multilayer tunneling dielectric construction 160 can prepare with multiple mode.In a particular instance; Multilayer tunneling dielectric construction 160 is bottom oxide/middle silicon nitride layer/top silicon oxide layer (O/N/O) three-decker; Wherein end silicon oxide layer can utilize the oxidizing process of any convention to form; Comprise thermal oxidation method, free radical (ISSG) oxidizing process, electric slurry oxide method and chemical vapor deposition process, but be not limited thereto.Middle silicon nitride layer can pass through chemical vapor deposition process, perhaps, starches the excessive bottom oxide of nitrogenize by electricity.The top oxide layer can form by oxidizing process or chemical vapour deposition technique.
In some embodiments of the invention, grid 170 can comprise having work function greater than N
+The material of polysilicon.In some embodiments of the invention, the material of this kind high work function grid can comprise metal, like platinum, iridium, tungsten and other precious metals.More preferably, the grid material has the work function more than or equal to about 4.5eV in these embodiment.In certain preferred embodiment, the material of grid comprises the metal with high work function, for example is platinum or iridium.In addition, preferable high work function material comprises P
+Polysilicon, but be not limited thereto, and metal nitride, for example be titanium nitride and tantalum nitride.In the certain preferred embodiment of the present invention, the grid material comprises platinum.
The rete of above-mentioned described suitable material, any known or developing method can be used for depositing or formation tunneling dielectric layer, charge storage layer and/or insulating barrier.Suitable method comprises like hot method of formation and chemical vapour deposition technique.
Please with reference to Fig. 2 and 3; Grid 170 at memory element 100 applies back bias voltage; And make to float in source/drain region 102,104, ground connection or be made as 0 volt; Wear tunnel mechanism by-FN, make electronics wear tunnel multilayer tunneling dielectric construction 160 back iunjected charge accumulation layers 150, cause the threshold voltage of memory element to rise from the grid 170 of memory element.Along with the increase of time, the electronics of part can't hinder to be trapped in the charge storage layer 150 and can pass through insulating barrier 140, and therefore, the threshold voltage of memory element can reach capacity, and can not rise by straight line.Result shown in Figure 3 then is to apply-17 volts ,-18 volts and-19 volts respectively and source/drain region 102,104 is made as 0 volt result at grid 170.Result by Fig. 3 shows: apply three kinds of different back bias voltages and all can make threshold voltage rise, and reach capacity over time.
Please with reference to Fig. 4 and 5; Grid 170 at memory element applies positive bias; And make to float in source/drain region 102,104, ground connection or be made as 0 volt; Wear tunnel mechanism by+FN, make positive hole wear tunnel multilayer tunneling dielectric construction 160 back iunjected charge accumulation layers 150, cause the threshold voltage of memory element to descend from the grid 170 of memory element.When tunnel multilayer tunneling dielectric construction 160 iunjected charge accumulation layers 150 are worn from the grid 170 of memory element in positive hole; The raceway groove injected electrons also can be worn tunnel insulating barrier 140 and iunjected charge accumulation layer 150; Therefore; Along with the increase of time, the threshold voltage of memory element is convergence (self-converging) certainly, and can not descend by straight line.Result shown in Figure 5, be apply respectively at grid 170+14 volts ,+15 volts and+16 volts bias voltage and the result who is floated in source/drain region 102,104.Result by Fig. 5 shows: applies three kinds of different positive biases and all can make threshold voltage rise, and over time from convergence.
The present invention wears tunnel mechanism by+FN, makes positive hole wear theoretical energy band diagram such as Fig. 6 and shown in Figure 7 of tunnel multilayer tunneling dielectric construction 160 (O2/N2/O3) back iunjected charge accumulation layer 150 (N1) from the grid 170 of memory element.Fig. 6 is for applying low electric field, i.e. theoretical energy band diagram between storage life; Fig. 7 is the theoretical energy band diagram that applies high electric field.Please with reference to Fig. 6; Wearing tunnel multilayer tunneling dielectric construction 160 is to have (O2/N2/O3) structure that is less than or equals 30 dusts for every layer; In the time of during preservation; Suppress that tunnel is directly worn in positive hole under low electric field and electronics can't hinder sunken (de-trap) problem at charge storage layer, therefore, have good data preservation characteristic.Fig. 7, wear tunnel multilayer tunneling dielectric construction 160 for every layer for to have (O2/N2/O3) structure that is less than or equals 30 dusts, can under high electric field, carry out high efficiency positive hole and wear tunnel.This possibly be because can be with that compensation (band offset) can impel effectively that positive hole overcomes O3 wear the tunnel energy barrier.So, can provide fast positive hole to stylize/wipe according to element of the present invention, avoid the NROM element to carry out the positive hole of heat that erase operation causes and bring out the phenomenon of destruction, and can exempt the preservation problem of convention SONOS element by the valence band-positive hole of conduction band heat mechanism.
Aforesaid operations of the present invention can be applied to PMOS memory element and NMOS memory element.
At first, situation when aforesaid operations of the present invention is applied to the PMOS memory element is described.Please with reference to Fig. 2; When aforesaid operations of the present invention is applied to the PMOS memory element; When stylizing, can apply back bias voltage at the grid 170 of memory element, and floated in the source/drain region 102,104 of P type, ground connection or be made as 0 volt; Make source/drain region 102, the channel region between 104 106 of P type form exhaustion region; And wear tunnel mechanism by-FN, and make electronics wear tunnel multilayer tunneling dielectric construction 160 back iunjected charge accumulation layers 150 from the grid 170 of memory element, cause the threshold voltage of memory element to rise.
Please with reference to Fig. 4; When being carried out at the PMOS memory cell erase; Grid 170 at memory element applies positive bias, and make to float in source/drain region 102,104, ground connection or be made as 0 volt, wear tunnel mechanism by+FN; Make positive hole wear tunnel multilayer tunneling dielectric construction 160 back iunjected charge accumulation layers 150, cause the threshold voltage of memory element to descend from the grid 170 of memory element.
According to element of the present invention, show splendid stylizing/erase cycles tolerance equally.Please with reference to Fig. 8, illustrate PMOS storage element under 10000 P/E circulations, the stylize threshold voltage and the time relation figure of state and erase status.As shown in Figure 8, after 10000 circulations, the change of threshold voltage is also not obvious.Please with reference to Fig. 9, illustrate the PMOS storage element 10000 times, 1000 times, 100 times with 1 P/E circulation under stylize state and erase status read voltage V
GWith electric current I
DGraph of a relation.As shown in Figure 9, after 10000 circulations, electric current I
DChange and not obvious.
Then, situation when aforesaid operations of the present invention is applied to the NMOS memory element is described.Please with reference to Fig. 4; When aforesaid operations of the present invention is applied to the NMOS memory element; When stylizing, apply positive bias at the grid 170 of memory element, and make to float in source/drain region 102,104, ground connection or be made as 0 volt; Make source/drain region 102, the channel region between 104 106 of N type form exhaustion region; And wear tunnel mechanism by+FN, and make positive hole wear tunnel multilayer tunneling dielectric construction 160 back iunjected charge accumulation layers 150 from the grid 170 of memory element, cause the threshold voltage of memory element to descend.
Please with reference to Fig. 2; When carrying out the wiping of NMOS memory element; Can apply back bias voltage at the grid 170 of memory element, and floated in the source/drain region 102,104 of N type, ground connection or be made as 0 volt, wear tunnel mechanism by-FN; Make electronics wear tunnel multilayer tunneling dielectric construction 160 back iunjected charge accumulation layers 150, cause the threshold voltage of memory element to rise from the grid 170 of memory element.
According to element of the present invention, show splendid stylizing/erase cycles tolerance equally.Please with reference to Figure 10, illustrate NMOS storage element under 10000 P/E circulations, the stylize threshold voltage and the time relation figure of state and erase status.Shown in figure 10, after 10000 circulations, the change of threshold voltage is also not obvious.Please with reference to Figure 11, illustrate the NMOS storage element 10000 times, 1000 times, 100 times with 1 (P/E) circulation that stylizes/wipe under stylize state and erase status read voltage V
GWith electric current I
DGraph of a relation.Shown in figure 11, after 10000 circulations, electric current I
DChange and not obvious.
In an embodiment of the present invention, grid 170 is corresponding to the word line of memory array, and source electrode 102 and drain electrode 104 (or conversely, source electrode 104 and drain electrode 102) are corresponding to the bit line of memory array.Therefore, each memory cell has a corresponding word lines and a pair of corresponding bit lines, or claims first bit line and second bit line.In some better embodiment of the present invention, grid 170 is corresponding to a word line of memory array; Source electrode 102 and drain electrode 104 (or conversely, source electrode 104 and drain electrode 102) are corresponding to two adjacent diffusion regions of a discontinuous bit line in the array.
Well known is, the MOS structure is symmetry normally, and source electrode and drain electrode can be intercoursed on function.Therefore, in above-mentioned and following narration and in the arbitrary embodiment of the present invention, the source electrode of memory cell and drain electrode, perhaps first and second bit line of array under the function that does not influence unit of the present invention, array or scope, can be intercoursed.In other words, in a discrete cell, the usefulness of source electrode or drain electrode can be used as in a specific diffusion region, and it is looked closely the voltage that is applied and decides, this for be familiar with this art known.
According to preferred embodiment of the present invention, illustrative memory array is illustrated in Figure 12,13 and 14.Figure 12 illustrates memory construction, and it has many discontinuous bit lines (vertical) and many word lines (level).Figure 13 is the profile along the partial array of the I-I tangent line of the orientation of Figure 12.Figure 14 is the profile of the partial array of the II-II tangent line of channel width dimension in Figure 12.
Please with reference to Figure 12,13 and 14, memory construction has most diffusion regions (S/D) 402,404 can be used as source electrode and drain electrode use.Diffusion region 402,404 is formed in the substrate 401, and is positioned at substrate 401 zones of word line below.Two of same discontinuous bit line adjacent diffusion regions 402, defined most channel regions 406 between 404.Shallow trench isolation 490 in the substrate 401 is used to make transistor area separated from one another.The irrigation canals and ditches degree of depth can be to be about 100 to 400 rice how.Lg has represented channel length.Ls is the distance (space) between each memory cell.W is a channel width, and Ws is the width of shallow trench isolation (STI).The stack layer 480 of substrate 401 comprises insulating barrier 440, charge storage layer 450, multilayer tunneling dielectric construction 460 and grid 470, wherein multilayer tunneling dielectric construction 460 it comprised that first tunneling dielectric layer 462, low positive hole wear the tunnel energy barrier layer 464 and second tunneling dielectric layer 466.
Figure 15 illustrates the equivalent circuit diagram according to a memory array of the present invention's one preferred embodiment.Intersecting of every word line (WL) and two adjacent word lines (BL ' s) comprises a transistor.
Then be noted that operation according to the memory cell array of different embodiments of the invention.
Figure 16,17,18 is respectively the equivalent circuit diagram of stylizing, wiping of p raceway groove NAND array structure of the present invention and read operation.
Please,, the pairing word line of a selected memory cell is applied back bias voltage, with the operation that stylizes according to the embodiment of the invention with reference to Figure 16.Particularly, to the pairing word line WL of selected memory cell A
7Impose the bias voltage of pact-16V, be preferably pact-18V to pact-20V; Other word line then imposes the bias voltage of pact-10V; And the pairing bit line BL of selected memory cell A
1Then impose the bias voltage of about 0V; Other bit line BL
2Then impose the bias voltage of pact-7V; Source electrode line SL then floats.Select transistor (SLT and BLT) optionally to exist, be connected in memory array.Selection transistor SLT near source electrode line SL imposes the 0V bias voltage; Selection transistor BLT away from source electrode line SL then imposes-bias voltage of 10V.Thus, word line WL
7Conveniently formed a vertical highfield down.Under this highfield, wear tunnel mechanism by-FN, can make electronics flow into charge storage layer via multilayer tunneling dielectric construction from the grid of storage unit A, cause the threshold voltage V of memory cell
ThRise.The interference that this operation is caused for adjoining memory cell B, C, D within the acceptable range.
Please with reference to Figure 17,, the word line of memory cell is applied positive bias, to carry out erase operation according to the embodiment of the invention.Particularly, all word lines are imposed the bias voltage of pact+14V to pact+16V, be preferably pact+15V; And float source electrode line SL and all bit lines.Selection transistor SLT and BLT approaching and away from source electrode line SL all impose the 0V bias voltage.Wear tunnel mechanism by+FN, make positive hole flow into charge storage layer via multilayer tunneling dielectric construction, cause the threshold voltage of each memory cell to descend, to reach the purpose of wiping from the grid of each memory cell.
Please,, memory cell is carried out read operation according to the embodiment of the invention with reference to Figure 18.Particularly, the selected pairing bit line of storage unit A is imposed-bias voltage of 1V; Float other word line; And impose the bias voltage of 0V at source electrode line SL.And, to the selected pairing word line WL of storage unit A
7Impose V
WL7Bias voltage; Other word line, selection transistor SLT and BLT approaching and away from source electrode line SL all impose V
PassBias voltage.Outside sensor circuit (not illustrating) meeting is because of the bias difference between source electrode and the drain electrode, and induction is through the electric current of raceway groove.By the electric current of the storage unit A of flowing through of responding to gained, can learn then whether storage unit A is stylized.
Figure 19,20,21 is respectively the equivalent circuit diagram of stylizing, wiping of n raceway groove NAND array structure of the present invention and read operation.
Please,, the pairing word line of a selected memory cell is applied positive bias, with the operation that stylizes according to the embodiment of the invention with reference to Figure 19.Particularly, to the pairing word line WL of selected memory cell A
7Impose the bias voltage of pact+14V, be preferably pact+15V to pact+16V; Other word line then imposes the bias voltage of pact+9V; And the pairing bit line BL of selected memory cell A
1Then impose the bias voltage of about 0V; Other bit line BL
2Then impose the bias voltage of pact+7V; Source electrode line SL then floats.Select transistor (SLT and BLT) optionally to exist, be connected in memory array.Selection transistor SLT near source electrode line SL imposes the 0V bias voltage; Selection transistor BLT away from source electrode line SL then imposes+bias voltage of 9V.Thus, word line WL
7Conveniently formed a vertical highfield down.Under this highfield, wear tunnel mechanism by+FN, can make positive hole flow into charge storage layer via multilayer tunneling dielectric construction from the grid of storage unit A, cause the threshold voltage V of memory cell
ThDescend.The interference that this operation is caused for adjoining memory cell B, C, D within the acceptable range.
Please with reference to Figure 20,, the word line of memory cell is applied back bias voltage, to carry out erase operation according to the embodiment of the invention.Particularly, all word lines are imposed the bias voltage of pact-16V to pact-20V, be preferably pact-18V; And float source electrode line SL and all bit lines.Selection transistor SLT and BLT approaching and away from source electrode line SL all impose the 0V bias voltage.Wear tunnel mechanism by-FN, make electronics flow into charge storage layer via multilayer tunneling dielectric construction, cause the threshold voltage of each memory cell to rise, to reach the purpose of wiping from the grid of each memory cell.
Please,, memory cell is carried out read operation according to the embodiment of the invention with reference to Figure 21.Particularly, the selected pairing bit line of storage unit A is imposed+bias voltage of 1V; Float other bit line; And impose the bias voltage of 0V at source electrode line SL.And, to the selected pairing word line WL of storage unit A
7Impose V
WL7Bias voltage; Other word line, selection transistor SLT and BLT approaching and away from source electrode line SL are all imposed V
PassBias voltage.Outside sensor circuit (not illustrating) can be because of the bias difference between source electrode and the drain electrode, and induction is through the electric current of raceway groove.By the electric current of the storage unit A of flowing through of responding to gained, can learn then whether storage unit A is stylized.
Element of the present invention reads electric current to be estimated, and is applicable to the application of flash memory.Grid in the PMOS memory element imposes+and 15V or impose-bias voltage of 18V in the NMOS memory element, can accomplish wiping of wellblock within 10msec.
Because tunneling oxide layer is not to directly overlay on the raceway groove, and is formed on the charge storage layer on the insulating barrier, therefore; The beak phenomenon that tunneling oxide layer receives shallow slot isolation structure hardly and caused influences; So, the effective reliability of lift elements, and element is easy to miniaturization.And, do not need too high voltage can accomplish stylizing of element fast or wipe, therefore, be a kind of low power consumption and method of operation fast.In addition, because main carrier stream is the multilayer tunneling dielectric construction via the grid below, rather than the insulating barrier on the raceway groove, therefore, through after the stylizing/wiping repeatedly, the degradation phenomena of element is still very little.
Though the present invention discloses as above with embodiment; Right its is not in order to limiting the present invention, anyly has the knack of this art, do not breaking away from the spirit and scope of the present invention; When can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (9)
1. memory element is characterized in that comprising:
One substrate has a pair of two sources/drain region, and separate through a channel region aforementioned source/drain region;
One grid is arranged on this substrate;
One insulating barrier is arranged on this channel region;
One electric charge storage layer is arranged on this insulating barrier; And
One multilayer tunneling dielectric construction is arranged between this electric charge storage layer and this grid, and wherein above-mentioned multilayer tunneling dielectric construction comprises:
One first tunneling dielectric layer is positioned on this this electric charge storage layer, and thickness is 10 dust to 30 dusts, has the 3rd ability rank;
Tunnel energy barrier layer is worn in one low positive hole, is positioned on this first tunneling dielectric layer, and thickness is 15 dust to 30 dusts, has the second ability rank;
One second tunneling dielectric layer is positioned at this low positive hole and wears on the tunnel energy barrier layer, and thickness is 8 dust to 30 dusts, has the first ability rank;
These first ability rank are positioned at the primary importance near above-mentioned grid, and are lower than the valence band ability rank of above-mentioned grid;
These second ability rank are positioned at the second place apart from above-mentioned grid 8-30 dust, and when not applying bias voltage, the second ability rank are between the valence band ability rank of above-mentioned first ability rank and above-mentioned grid; And
The 3rd ability rank, the 3rd position between said second position and above-mentioned charge storage layer, and when not applying bias voltage, the 3rd ability rank are lower than the valence band ability rank of above-mentioned grid and are lower than the valence band ability rank of above-mentioned charge storage layer,
Wherein be pressed on this grid through applying a negative bias; Make a plurality of electronics wear tunnel and get into above-mentioned electric charge storage layer via the above-mentioned tunnel dielectric structure of wearing from this grid; And be pressed on above-mentioned grid through applying a positively biased, make a plurality of holes wear tunnel and get into above-mentioned electric charge storage layer via the above-mentioned tunnel dielectric structure of wearing from above-mentioned grid.
2. memory element according to claim 1 is characterized in that wherein above-mentioned back bias voltage is-16 to-20 volts.
3. memory element according to claim 1 is characterized in that wherein above-mentioned positive bias is 14 to 16 volts.
4. memory element according to claim 1 is characterized in that wherein above-mentioned multilayer tunneling dielectric construction comprises three layers of monoxide/nitride/oxide.
5. memory element according to claim 1 is characterized in that wherein above-mentioned multilayer tunneling dielectric construction comprises three layers of silicon monoxide/three layers of nitrogenize silicon/oxidative silicons or silicon monoxide/alumina/silica.
6. memory element according to claim 1 is characterized in that wherein the material of above-mentioned insulating barrier comprises silica or aluminium oxide.
7. memory element according to claim 1 is characterized in that wherein the material of this electric charge storage layer comprises silicon nitride, silicon oxynitride, HfO
2, HfSi
xO
yOr Al
2O3.
8. memory element is characterized in that comprising:
One substrate has pair of source, and separate through a channel region aforementioned source/drain region;
One grid is arranged on the above-mentioned substrate;
One insulating component is arranged on the above-mentioned substrate, makes between an electric charge storage layer and above-mentioned substrate to insulate, with the tunnel of wearing in restriction electronics and hole;
This electric charge storage layer be arranged between above-mentioned insulating component and the above-mentioned grid, and electric charge that above-mentioned electric charge storage layer is caught determines a threshold voltage of above-mentioned memory element; And
One multilayer FN wears the tunnel member, is arranged between above-mentioned electric charge storage layer and the above-mentioned grid, and wherein above-mentioned multilayer FN wears the tunnel member and comprises:
One first tunneling dielectric layer is positioned on this this electric charge storage layer, and thickness is 10 dust to 30 dusts, has the 3rd ability rank;
Tunnel energy barrier layer is worn in one low positive hole, is positioned on this first tunneling dielectric layer, and thickness is 15 dust to 30 dusts, has the second ability rank;
One second tunneling dielectric layer is positioned at this low positive hole and wears on the tunnel energy barrier layer, and thickness is 8 dust to 30 dusts, has one first ability rank;
These first ability rank are positioned at the primary importance near above-mentioned grid, and are lower than the valence band ability rank of above-mentioned grid;
These second ability rank are positioned at the second place apart from above-mentioned grid 8-30 dust, and when not applying bias voltage, the second ability rank are between the valence band ability rank of above-mentioned first ability rank and above-mentioned grid; And
The 3rd ability rank, the 3rd position between said second position and above-mentioned charge storage layer, and when not applying bias voltage, the 3rd ability rank are lower than the valence band ability rank of above-mentioned grid and are lower than the valence band ability rank of above-mentioned charge storage layer,
Under positive bias; Wear tunnel mechanism through+FN hole, make the hole wear tunnel to above-mentioned electric charge storage layer, to be reduced in the threshold voltage in a programming or the erase operation from above-mentioned grid; And under back bias voltage; Wear tunnel mechanism through-FN, make electronics wear tunnel to above-mentioned electric charge storage layer, to be increased in the threshold voltage in another operation that a programming or wipes from above-mentioned grid.
9. memory element according to claim 8 is characterized in that wherein the material of above-mentioned electric charge storage layer comprises silicon nitride, silicon oxynitride, HfO
2, HfSi
xO
yOr Al
2O
3
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