CN101483656B - IP soft-core for MVB interface - Google Patents

Abstract

The invention relating to the field of train vehicular network system control technology discloses a MVB (multifunctional vehicle bus) interface IP (intellectual property) soft core. The MVB interface IP soft core comprises a link layer control unit module, a coder module, a decoder module, a sending caching module, a receiving caching module, a traffic memory module and an address arbitration module; the link layer control unit module determines receiving data from MVB network or sending data to the MVB network; the coder module and decoder module are respectively used for coding and decoding of MVB data; the sending caching module and the receiving caching module respectively perform temporary storage when data is sent or received; the traffic memory module is in charge with the data switching between the MVB network and an application processor; the address arbitration module is used for deciding that the application processor reads or writes data address of the traffic memory. The invention provides an MVB interface function for the IP soft core designed by using a current SOPC technique, therefore, development and application of train vehicular devices become more flexible.

Description

The soft nuclear of a kind of MVB interface IP

Technical field

The invention belongs to train-installed network system control technology field, relate in particular to the soft nuclear of a kind of MVB interface IP.

Background technology

The application of TCN is to guarantee that Train Control validity, fail safe and passenger's comfortableness are necessary, and the networked control system of the train technology has become one of indispensable technology of bullet train, EMUs.Train communication network is coupling together between each level of whole train Control System of Microcomputer and each unit of each level, as system information exchange and the channel shared, realizes the information exchange under the full train environment.The application of train communication network makes train control system really become a dcs, and lays the foundation for the informationization of train system.

Stipulate TCN (Train Communication Network in the IEC 61375-1 standard; TCN) by MVB (Multifunctional Vehicle Bus; MVB) and WTB (TwistedTrain Bus, wired train bus) two-stage bus constitute.MVB is the TCN element, is used for realizing the data communication between the standard device of the different vehicle of same vehicle or fixed-interlock.It provides two kinds of connections: the one, and the interconnection between the programmable device, the 2nd, with these equipment and their transducer and actuator's interconnection.MVB be automatic realization, the message of many functions (like gate, braking, air-conditioning, passenger information, seat reservation, illumination etc.) of each equipment in the compartment transmission, resource share and each equipment between reasonable cooperation provide reliably, passage smoothly.The multipotency of MVB is addressed to 4095 equipment, wherein can have 256 to be the station that can participate in message communicating.A type Manchester's code is adopted in the MVB digital coding, and transmission rate is 1.5Mbit/s.

The MVB bus control unit is a Primary Component of realizing the MVB bus functionality, is responsible for visit MVB bus, and the communication interface with microprocessor is provided, and realizes transfer of data.At present exploitation TCN equipment mainly contains two kinds of methods, and a kind of is that to utilize MVBC (Multifunctional Vehicle Bus Controller, MVB controller) chip be that core is developed; Another kind is to utilize FPGA (FieldProgrammable Gate Array, field programmable gate array) and embedded system to develop.Comparatively speaking; Use MVBC chip development TCN equipment relatively easy; MVBC is the Equipment Control chip of a MVB; The related communication function of train communication network has cured in the MVBC chip, so only need add the exploitation that peripheral circuit just can be accomplished the train communication web network equipment.The network equipment portability of exploitation is not strong in this way, and the communication function of MVBC has cured, and can not make amendment according to user's needs.

FPGA is a kind of programmable logical device, and the logic function that its is realized can be made corresponding change according to user's needs, and FPGA is widely used, and development technique is ripe, uses flexibly.Therefore, selecting for use FPGA to carry out the TCN development of equipments is trend of the times.At present, obtained very extensive studies around realization based on the MVB network interface of FPGA.

U.S. Dataquest consulting firm is with IP (the Intellectual Property of semiconductor industry; IP core) is defined as the circuit function module that defines in advance among ASIC (Application Specific Integrated Circuit, application-specific integrated circuit (ASIC)) or the FPGA/CPLD.Using IP in the sheet is the key property of SoC (System OnChip, SOC(system on a chip)).IP is divided into soft IP, solid IP and hard IP.Soft IP kernel: with the functional block of hardware description language (HDL) description; Gu IP kernel: accomplished comprehensive functional block, bigger projected depth is arranged, submitted to the client with the form of net meter file and use; Hard IP kernel: it is mask that the terminal stage product of design is provided.

Obviously, at concrete realization means and the still undetermined logic design phase of technology, soft nuclear has maximum flexibility, is easy to be combined as a whole by EDA synthesis tool and other external logics.By contrast, Gu the flexibility that nuclear and stone and other external logics are combined as a whole is very different.When needs put out a new product, SoC developer can transfer to original IP on the new embedded system, perhaps only needed the change sub-fraction, just can satisfy the needed functional requirement of product.The recycling of Here it is IP kernel so as to shortening the Products Development cycle, reduces complexity of developing.

The immediate development achievement of microelectric technique is that the realization of SoC provides number of ways.For through verifying and having System on Chip/SoC in batches, can make application-specific integrated circuit (ASIC) (ASIC) and a large amount of production.And be merely the SoC that the development phase was used or be in to small lot for some, and if having high input large-scale production at once, then need drop into more fund, bear bigger trial-production risk.

SOPC (System on a Programmable Chip, programmable system on the sheet) technology provides another kind of effective solution, promptly realizes the function of SoC with large-scale FPGA, be a kind of more flexibly, SoC solution efficiently.SOPC has combined the advantage of SoC and FPGA, accomplishes the main logic function of system by entire chip, has the design flexible mode again, can reduce, extendible, scalable.32 flush bonding processors of core processor NIOS II series have very big flexibility in the SOPC technology, can be provided with in the combination in multiple systems and select, and reach performance, characteristic and cost objective.

The SOPC technology is that U.S. altera corp proposed in 2000 the earliest, and has released corresponding development environment simultaneously.Compare with the solution of ASIC, SOPC system and development technique thereof have more characteristic, and the formation scheme has following several kinds of approach:

1) embeds the SOPC system of IP stone based on FPGA

2) embed the SOPC system of the soft nuclear of IP based on FPGA

3) based on the technological SOPC system of HardCopy

Wherein, with the IP stone directly implant solution among the FPGA exist on the high side, can't the customized processor structure, can't the cutting hardware resource etc. deficiency.Utilize the soft nuclear energy of IP to overcome above-mentioned unfavorable factor effectively.

The Avalon interface specification is that the exploitation for peripheral hardware under the SOPC environment designs, for the designer of peripheral hardware provide a description main peripheral hardware and from peripheral hardware based on the basis of address read/write interface, peripheral hardwares such as microprocessor, memory, UART, timer for example.Interface specification has defined the transfer of data between peripheral hardware and the Avalon switch interconnect architecture (AvalonSwitch Fabric).Do not having main or under the situation of interface priori, the interconnected strategy of standard allows any main peripheral hardware to be connected to from peripheral hardware.The Avalon interface has been described a configurable interconnected strategy, allows the designer of peripheral hardware to limit the required signal type of certain specific transmission of support.

Summary of the invention

The object of the present invention is to provide the soft nuclear of a kind of MVB interface IP, solve and adopt the SOPC art designs to meet in the MVB product of IEC61375-1 standard at present, the soft nuclear of IP does not have the problem of MVB interface.

Technical scheme of the present invention is, the soft nuclear of a kind of MVB interface IP comprises link layer control unit module, coder module, decoder module, transmission buffer module, receives buffer module, communication memory module and address arbitration modules, it is characterized in that,

Said link layer control unit module judges whether to receive Frame according to the Status Flag of decoder; After receiving Frame, read in Frame, judge the operation that to carry out according to this Frame from receiving buffering; If this Frame is a prime frame; Then according to its function code and address; Judgement is to need to send Frame or need to wait for that reception from frame, if will send Frame then from communication memory module sense data, writes the transmission buffer module; Send to coder module then and send order, the beginning data are sent; If will wait for reception from frame, then to decoder specify that desire receives from frame sign, receive behind frame, write the communication memory module from receiving the buffer module sense data; This module overtime judgement that also will communicate simultaneously, refresh and the timer of process data port are safeguarded;

Said coder module is sent data according to the MVB data frame format to the MVB network from sending the buffer module sense data under the control of link layer control unit module;

Said decoder module is obtained Frame according to the receiving data frames length of link layer control unit module appointment from the MVB bus, deposits the Frame that receives in the reception buffer module;

Said transmission buffer module is stored the link layer control unit module temporarily and is desired to send to the Frame on the MVB network;

The Frame that the interim storage decoder module of said reception buffer module is obtained from the MVB network;

Said communication memory module sends to the MVB network with the data of application processor under the control of link layer control unit module; Simultaneously, under the control of link layer control unit module, the MVB network data is sent to application processor;

Said address arbitration modules is used to determine the data address of application processor read-write communication memory.

Said communication memory module comprises type-scheme register module, device address register module, process data module, monitoring data module, message input fifo module and message output fifo module;

Wherein, said type-scheme register module is used for process data configuring ports and state refresh;

Said device address register module is used for representing the pairing mobile unit of application processor in the device address of MVB network, and this address has determined the transmitting-receiving of monitoring data and message data;

Said process data module is used to store the data of each port, and it is to send to the MVB network that this data based its type decides, and still receives from the MVB network;

Whether said monitoring data module decision is to MVB network transmitting monitoring data;

Said message output fifo module is stored the data that application processor sends to the MVB network temporarily;

The data that the interim store M VB network of said message input fifo module sends to application processor.

The soft nuclear of a kind of MVB interface IP provided by the invention; For the existing soft nuclear of IP of SOPC art designs that adopts provides MVB interface function; Thereby the soft nuclear energy of IP enough is applied in the train-installed development of equipments; And then making the chip of train-installed equipment have portable, reusable, the advantage that can also make amendment according to client's demand simultaneously finally makes train-installed development of equipments and application become more flexible.

Description of drawings

Fig. 1 is the soft nuclear general structure of MVB interface IP.

Fig. 2 is link layer control unit flow chart of data processing figure.

Fig. 3 is the Avalon interface definition circuit diagram of the soft nuclear of MVB interface IP.

Fig. 4 is the communication memory module distribution figure of the soft nuclear of MVB interface IP.

Fig. 5 is the implementation method block diagram of the soft nuclear of MVB interface IP.

Fig. 6 is the connection layout of soft nuclear of MVB interface IP and SOPC nucleus module.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment is elaborated.Should be emphasized that following explanation only is exemplary, rather than in order to limit scope of the present invention and application thereof.

Fig. 1 is the soft nuclear general structure of MVB interface IP.Among Fig. 1, the soft nuclear of MVB interface IP comprises link layer control unit module, coder module, decoder module, transmission buffer module, receives buffer module, communication memory module and address arbitration modules.Each functional module effect is following,

Decoder module: according to the link layer control unit module appointment want receiving data frames length, obtain Frame from the MVB bus, the Frame that receives is deposited in receives buffering.

Receive buffer module: comprised the Frame that decoder obtains from network.

Link layer control unit module: the Status Flag according to decoder judges whether to receive new data frame.After receiving new Frame, read in Frame, judge the operation that to carry out according to this Frame from receiving buffering.If prime frame then according to its function code and address, judges whether that needing to send Frame waits for that still reception is from frame.If will send Frame then from communication memory (Traffic Memory) sense data, write the transmission buffer module, to send to coder module then and send order, the beginning data are sent.If will wait for reception from frame, then to decoder specify that desire receives from frame sign, receive behind frame, write communication memory (Traffic Memory) from receiving the buffering sense data.This module overtime judgement that also will communicate simultaneously, the work such as refresh timer maintenance of process data port.

Send buffer module: comprised link layer control unit and desired to send to the Frame on the MVB network.

Coder module: under the control of link layer control unit, send data according to the MVB data frame format to network from sending the buffering sense data.

Communication memory module: under the control of link layer control unit module, the data of mobile unit are sent to the MVB network; Simultaneously, under the control of link layer control unit module, the MVB network data is sent to mobile unit.The communication memory module comprises type-scheme register module, device address register module, process data module, monitoring data module, message input fifo module and message output fifo module.Wherein, the type-scheme register module is used for process data configuring ports and state refresh; The device address register module is used for representing the device address of mobile unit at the MVB network, and this address has determined the transmitting-receiving of monitoring data and message data; The process data module is used to store the data of each port, and it is to send to the MVB network that this data based its type decides, and still receives from the MVB network; Whether the decision of monitoring data module is to MVB network transmitting monitoring data; Message output fifo module is stored the data that mobile unit sends to the MVB network temporarily; The data that the interim store M VB network of message input fifo module sends to mobile unit.

Address arbitration modules: be used to determine that application processor is the data address that will read and write communication memory (TrafficMemory).

Link layer control unit is that the key of this IP kernel is implemented part, the MVB bus control unit various piece that takes charge co-ordination.Whether main task is to confirm prime frame and from the corresponding relation of frame, correct to judge communication, produces the access control signal and the address signal of each memory, coordinates the exchanges data between buffering area and the communication memory (Traffic Memory).Link layer control unit receives processes such as timer, message data reception, transmission buffering and the access control of reception buffering by the prime frame monitoring, from frame detection, prime frame receiving and analyzing, transmission and forms.Fig. 2 is link layer control unit flow chart of data processing figure, and among Fig. 2, the data handling procedure of link layer control unit is following:

1, system power-on reset;

2, mobile unit gets into the prime frame state of waiting for;

3, simultaneously, the master controller that has the soft nuclear of MVB interface IP judges whether port need refresh when every millisecond of beginning; Refresh if desired, then obtain port arrangement; Judge whether port type is the place port, if, then at first obtain port refresh timer value, after the updating value, be written to port refresh timing register once more, get back to the prime frame state of waiting for afterwards;

4, after mobile unit is received prime frame, from receive buffering, read analytical capabilities sign indicating number and address to prime frame;

The master polls incident that if 5 these prime frames are this equipment to be expected, and incident suspension sign effectively, then at first empties incident suspension sign, representes that this incident takes place;

6, judge that according to the function code in the prime frame poll is process data poll, message data poll or monitoring data poll;

7 if the process data poll, then reads the port arrangement situation of specified address from the process data port type mode register of communication memory module; If this port attribute is a source port, then from the port data regional sensed data of communication memory module and write and send buffering, after to be sent being timed to, start encoder, send from frame; If this port attribute is the place port, then wait-for-response from frame, if in the time of appointment, meet with a response, then, write the corresponding region of communication memory module again from receive buffering, reading from frame from frame; If wait for from frame timeout, then continue to turn back to wait from frame state; If specified port is invalid port in the prime frame, also turn back to the prime frame state of waiting for;

8 if the message data poll judges whether the address of appointment in the prime frame is identical with the device address of this equipment; If identical, judged whether that then message data needs to send, if having then, write and send buffering, after to be sent being timed to, start encoder from message output queue sense data, send from frame; If do not have message data to need to send, then turn back to the prime frame state of waiting for; If the address in the prime frame is different with the device address of this mobile unit, then wait for receiving from frame; Receive behind frame, at first analyze the content from frame, see whether this message data issues this mobile unit, if then, write the message input rank from receiving the buffering sense data; Otherwise, abandon this message data, turn back to the prime frame state of waiting for; If wait for, also get back to the prime frame state of waiting for from the frame timeout situation;

9 if the monitoring data poll judges whether the address of appointment in the prime frame is identical with the device address of this mobile unit; If identical, then read monitoring data from the communication memory module, write and send buffering, to be sent being timed to starts encoder, sends from frame; If different, then turn back to the prime frame state of waiting for.

The soft nuclear of MVB interface IP of the present invention exists as the slave unit of Avalon bus; The address align mode adopts static alignment (Registers Mode) mode; Fig. 3 is the Avalon interface definition circuit diagram of the soft nuclear of MVB interface IP, has provided the external interface figure of the soft nuclear of this IP among Fig. 3.Table 1 has been listed the specific descriptions information of each interface signal.

Signal	Bit wide	Direction	Function
				ext_mvb_in	1	Input	The MVB input
ext_mvb_out	1	Output	MVB output
				mvb_outen	1	Input	MVB sends and enables
avaslv_rd_n	1	Input	Read to enable
				avaslv_wr_n	1	Input	Write and enable
avaslv_addr[12..0]	13	Input	The address
				avaslv_writedata[7..0]	8	Input	Write data
avaslv_readdata[7..0]	8	Output	Read data
				sys_clk	1	Input	System clock
sys_rst_n	1	Input	System reset
				pio_mqsnd_sclr	1	Input	Empty transmit queue
pio_mqrcv_almostempty	1	Output	It is empty receiving formation
				pio_mqsnd_almostfull	1	Output	Receive formation for full

A table mistake! Undefined pattern.1: based on the soft nuclear signal definition of MVB interface IP of Avalon

Communication memory (Traffic Memory) is the bridge that the MVB bus control unit is communicated by letter with application processor, and data wherein comprise process data, monitoring data, information such as message data and other port arrangement.DPRAM (Dual Port RAM is adopted in process data and monitoring data storage; Dual port RAM) realizes; Message queue adopts FIFO (First In First Out, FIFO) mode, and two kinds of memories of DPRAM and FIFO all can be realized through the inner memory module of FPGA.Fig. 4 is the communication memory module distribution figure of the soft nuclear of MVB interface IP.Among Fig. 4, have 255 logic ports, possess message data and monitoring data disposal ability.

Through the soft data of delivering to the MVB network of authorizing of MVB interface IP,,, reality to add verification sequence when sending in order to guarantee communication reliability.At receiving terminal, decoder also will calculate the verification sequence of the MVB data that receive, and compares with the verification sequence that receives, if conform to then show that Data Receiving is correct, otherwise failure.Data are protected with one or more 8 bit check sequences, and the content of data should be processed into 64 code word (to smaller data with 16 or 32), does not comprise start delimiter and stops delimiter.This code word and verification sequence subsequently should at first be sent as the highest active data position.

Fig. 5 is the implementation method block diagram of the soft nuclear of MVB interface IP.Provided the application process of the soft nuclear of IP among Fig. 5.In actual use, be configurations FPGA with the soft nuclear of this IP.Because the flexibility of Avalon EBI; This soft nuclear also can communicate with external independent processor; Therefore application processor can be to be positioned at the FPGA outside, also can promptly directly application processor be embedded into FPGA inside by the SOPC technology, thereby reach higher integrated level.

Fig. 6 is the connection layout of soft nuclear of MVB interface IP and SOPC nucleus module.Fig. 6 has provided employing SOPC when technology, and the line relation that the SOPC nucleus module connects through the Avalon bus with the soft nuclear of this IP is connected to FPGA sheet outer signal definition such as table 2 with the soft nuclear phase of this IP closes.

Signal	Bit wide	Direction	Function
				?ext_mvb_in	1	Input	The MVB input
?ext_mvb_out	1	Output	MVB output
				?mvb_outen	1	Input	MVB sends and enables
?sys_clk	1	Input	System clock, 24MHz
				?sys_rst_n	1	Input	System reset, low level is effective

Table 2: with the signal definition outside the FPGA sheet that is connected to of the soft nuclear phase of MVB interface IP pass

The SOPC nucleus module that Fig. 6 provides is a minimal configuration of using the SOPC system of the soft nuclear of this IP, in the process of practical application, will increase other necessary function as required.

The present invention provides MVB interface function for the existing soft nuclear of IP of SOPC art designs that adopts; Thereby the soft nuclear energy of IP enough is applied in the train-installed development of equipments; And then make the chip of train-installed equipment have portable, reusable; The advantage that can also make amendment according to client's demand simultaneously finally makes train-installed development of equipments and application become more flexible.

The above; Be merely the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; The variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.

Claims (2)

1. the soft nuclear of MVB interface IP comprises link layer control unit module, coder module, decoder module, transmission buffer module, receives buffer module, communication memory module and address arbitration modules, it is characterized in that,

Said link layer control unit module judges whether to receive Frame according to the Status Flag of decoder; After receiving Frame, read in Frame, judge the operation that to carry out according to this Frame from receiving buffering; If this Frame is a prime frame, then from receive buffering, read analytical capabilities sign indicating number and address to prime frame; The master polls incident that if this prime frame is this equipment to be expected; And incident suspension sign effectively, then at first empties incident suspension sign, representes that this incident takes place;

Judge that according to the function code in the prime frame poll is process data poll, message data poll or monitoring data poll;

If the process data poll, then read the port arrangement situation of specified address from the process data port type mode register of communication memory module; If this port attribute is a source port, then from the port data regional sensed data of communication memory module and write and send buffering, after to be sent being timed to, start encoder, send from frame; If this port attribute is the place port, then wait-for-response from frame, if in the time of appointment, meet with a response, then, write the corresponding region of communication memory module again from receive buffering, reading from frame from frame; If wait for from frame timeout, then continue to turn back to wait from frame state; If specified port is invalid port in the prime frame, also turn back to the prime frame state of waiting for;

If the message data poll judges whether the address of appointment in the prime frame is identical with the device address of this equipment; If identical, judged whether that then message data needs to send, if having then, write and send buffering, after to be sent being timed to, start encoder from message output queue sense data, send from frame; If do not have message data to need to send, then turn back to the prime frame state of waiting for; If the address in the prime frame is different with the device address of this mobile unit, then wait for receiving from frame; Receive behind frame, at first analyze the content from frame, see whether this message data issues this mobile unit, if then, write the message input rank from receiving the buffering sense data; Otherwise, abandon this message data, turn back to the prime frame state of waiting for; If wait for, also get back to the prime frame state of waiting for from the frame timeout situation;

If the monitoring data poll judges whether the address of appointment in the prime frame is identical with the device address of this mobile unit; If identical, then read monitoring data from the communication memory module, write and send buffering, to be sent being timed to starts encoder, sends from frame; If different, then turn back to the prime frame state of waiting for;

This module overtime judgement that also will communicate simultaneously, refresh and the timer of process data port are safeguarded;

Said coder module is sent data according to the MVB data frame format to the MVB network from sending the buffer module sense data under the control of link layer control unit module;

Said decoder module is obtained Frame according to the receiving data frames length of link layer control unit module appointment from the MVB bus, deposits the Frame that receives in the reception buffer module;

Said transmission buffer module is stored the link layer control unit module temporarily and is desired to send to the Frame on the MVB network;

The Frame that the interim storage decoder module of said reception buffer module is obtained from the MVB network;

Said communication memory module sends to the MVB network with the data of application processor under the control of link layer control unit module; Simultaneously, under the control of link layer control unit module, the MVB network data is sent to application processor;

Said address arbitration modules is used to determine the data address of application processor read-write communication memory.

2. the soft nuclear of a kind of MVB interface IP according to claim 1 is characterized in that said communication memory module comprises type-scheme register module, device address register module, process data module, monitoring data module, message input fifo module and message output fifo module;

Wherein, said type-scheme register module is used for process data configuring ports and state refresh;

Said device address register module is used for representing the pairing mobile unit of application processor in the device address of MVB network, and this address has determined the transmitting-receiving of monitoring data and message data;

Said process data module is used to store the data of each port, and it is to send to the MVB network that this data based its type decides, and still receives from the MVB network;

Whether said monitoring data module decision is to MVB network transmitting monitoring data;

Said message output fifo module is stored the data that application processor sends to the MVB network temporarily;

The data that the interim store M VB network of said message input fifo module sends to application processor.

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