CN104282054B - MVB (Multifunction Vehicle Bus) bus decoding and on-vehicle recording system based on SOPC technology - Google Patents
MVB (Multifunction Vehicle Bus) bus decoding and on-vehicle recording system based on SOPC technology Download PDFInfo
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Abstract
The invention relates to an MVB (Multifunction Vehicle Bus) bus decoding and on-vehicle recording system based on an SOPC technology. The system comprises an FPGA chip, an EPCS serial FLASH chip, an SDRAM chip, an SRAM chip, an SD card and an MVB level switching circuit, wherein the FPGA chip comprises an NIOS-II soft-core processor, a phase-locked loop frequency multiplier, an MVB decoder, an SRAM read/write controller, an SPI switching module and an SPI; the NIOS-II soft-core processor is connected with the EPCS serial FLASH chip, the SDRAM chip, the phase-locked loop frequency multiplier, the MVB decoder, the SRAM read/write controller and the SPI; the MVB decoder is connected with the phase-locked loop frequency multiplier, the MVB level switching circuit and the SRAM read/write controller; and the SPI switching module is connected with the SPI interface, the SRAM read/write controller and the SD card. Compared with the prior art, the MVB bus decoding and on-vehicle recording system disclosed by the invention has the advantages of software and hardware integration, high reliability, convenience in operation, high real-time property and the like.
Description
Technical field
The present invention relates to a kind of analysis of mvb bus data and memory technology, especially relate to a kind of based on sopc technology
Mvb bus encoding/decoding with car record system.
Background technology
With the development of high-speed railway and modern railway transportation technology, TCN (train communication
Network, tcn) become a kind of vehicle of main flow and train data communication system.The iec- of International Electrotechnical Commissio
61375 standards, TCN is divided into for connecting the hinge type train bus-line wtb (wire that each section can dynamically be organized into groups
Train bus) and for connecting MVB mvb (the multifunction vehicle of fixing equipment in vehicle
bus).Compared with the application ON TRAINS of other common field bus, mvb is in real-time, reliability, manageability, medium
The aspects such as access control method, addressing system and communication service species have bigger advantage.
With frame as base unit, message transmission rate is 1.5mbps to mvb bus data, and Frame employs Manchester
Code transmission, the baud rate after therefore encoding is 3mbaud.Encoder not only Manchester Code/decode to be completed, crc
The generation of sequence and verification, also will add simultaneously and identify frame head postamble to realize the synchronization of Frame.Two kinds of frames are had in mvb:
A kind of is the main equipment frame that can only be sent by bus master, referred to as " prime frame ", and prime frame content contains the equipment end of institute's inquiry
Slogan and function code；Another kind of for response prime frame by sending from equipment frame from equipment, referred to as " from frame ", from the length of frame and
Type is determined by function code.
Rail transit train under normal operating conditions, mvb bus can produce substantial amounts of data, and mvb data presses message
Type can be divided into process data, information data and monitor data.By collect train on mvb equipment status monitoring and
Failure diagnosis information, can analyze train and equipment reliability of operation and security, be that maintenance and the maintenance of train apparatus carries
For useful information.So-called mvb equipment refers to employ mvb communication control chip on rail transit train, can lead to according to mvb
News agreement carries out the equipment of data communication.Although traditional mvb communication controler chip enumerates mvb data link layer and application
The complete function of layer, but because of its cost intensive, using complexity, and by external company technique monopolization, be not appropriate for as autonomous
The first-selection of the mvb Bus analyzer of exploitation.
Content of the invention
The purpose of the present invention is exactly to overcome the defect of above-mentioned prior art presence to provide a kind of soft or hard combination, reliability
Property high, easy to operate, the mvb bus encoding/decoding based on sopc technology that real-time is good with car record system, for mvb number of buses
According to real-time analysis and Large Volume Data real-time storage.
The purpose of the present invention can be achieved through the following technical solutions:
A kind of mvb bus encoding/decoding based on sopc technology with car record system it is characterised in that include fpga chip,
Epcs serial flash chip, sdram chip, sram chip, sd card and mvb level shifting circuit, described fpga chip includes
Nios-ii soft-core processor, Phase Locked Loop Frequency Doubler, mvb decoder, sram read-write controller, spi interface switching module and spi
Interface, described nios-ii soft-core processor respectively with epcs serial flash chip, sdram chip, Phase Locked Loop Frequency Doubler,
Mvb decoder, sram read-write controller and spi interface connect, and described mvb decoder is electric with Phase Locked Loop Frequency Doubler, mvb respectively
Flat change-over circuit and sram read-write controller connect, and described mvb level shifting circuit is connected with mvb bus, and described spi connects
Mouth handover module is connected with spi interface, sram read-write controller and sd card respectively.
Epcs serial flash chip is as program storage, and the epcs controller that bootstrap is downloaded and loaded；
Sdram chip is as the internal memory of processor, and the sdram controller controlling memory read-write；
Phase Locked Loop Frequency Doubler (pll), provides the system work clock of high speed for the soft core of nios-ii, decode for mvb, simultaneously
Data memory module provides the work clock being several times as much as mvb code check；
Mvb decoder completes whole work of mvb data decoding, decodes the serial data obtaining at transformation from serial to parallel
After reason, sram chip caching is write by sram read-write controller；
Sram read-write controller, the input of caching is derived from the decoded data of mvb, exports and turns serial parallel and form turns
Die change block, eventually passes spi interface switching module write sd card；
Spi interface switching module, for controlling the decoding data stream caching in sram and being derived from nios-ii data flow
Sd card read-write switching.
The sram chip being connected with sram read-write controller, solves caching in the required fpga piece of high speed write sd card not enough
Problem.
Described mvb decoder include delimiter identification module, manchester decoder module, crc checker, timer,
Bus exception management unit and decoded stream process control unit, described delimiter identification module include prime frame frame head recognition unit,
From frame frame head recognition unit and postamble recognition unit, described decoding process control unit respectively with prime frame frame head recognition unit,
From frame frame head recognition unit, postamble recognition unit, manchester decoder module, crc checker, timer and bus exception management
Unit connects, and described bus exception management unit is connected with manchester decoder module, crc checker respectively；
Realize frame alignment by delimiter identification module, described manchester decoder module decodes prime frame, described
Crc checker verification data, determine after obtaining function code reply from frame format, then be decoded to from frame；
Described timer is used for the timing judging not responding from frame timeout；Bus exception management unit is used for collecting each list
The abnormal signal of unit's feedback simultaneously feeds back to decoding process control unit.
Described abnormal signal includes manchester decoder exception, crc assay mistake, frame length mistake and surpasses from frame
When do not respond.
Described mvb decoder adopts fsm (finite state machine, finite state machine) method same to carry out frame
Step and manchester decoder.
Described sram read-write controller includes:
But one is to realize caching read-write controller by hardware, is responsible for simple, repetition a large amount of, the data porter of high speed
Make；
Two is the method for data flow control employing ping-pong operation, and sram spatial cache is divided into two buffering areas, number
According to input is always continuous with output, alternate cycles are carried out in two buffering areas, realize the cache of data.
Described nios-ii soft-core processor runs sd card host-host protocol and fat32 file system protocol program, supports
Sd card read-write under fat32 file system.
The decoding data that sram read-write controller is cached by described spi interface switching module and the soft core of nios-ii are processed
The sd card host-host protocol of device and fat32 file system protocol program (include the bottoms such as sd card initialization, Read-write Catrol instruction to drive
Dynamic, fat32 file system reads sd card system boot sector, updates the operation such as file allocation table) produced by data flow when
Under the cooperation of sequence pass through spi interface, complete data real-time, store at high speed.
Also include the mvb DAS at pc end, for deriving, checking, analyze the initial data literary composition of record in sd card
Part, and data can be carried out with the process in later stage, software, under microsoft visual studio 2010 translation and compiling environment, uses
Pc end software write in c# language.Software function specifically includes:
According to the position definition of User Defined mvb device diagnostic word table or frame, the frame data of record are parsed, obtains
Mvb device name, logical address, device address, fault type, state change information, allow users to more intuitively analyze
The change of mvb equipment state and the fault being likely to occur during train operation.
The software and hardware function of present system divides: the mvb that processing data amount is big, algorithm is relatively single is responsible for by system hardware
Decoding function data caches, and relative complex, be not easy to hard-wired file system protocol and sd card host-host protocol then by
Nios-ii processor is completed in the way of software.Hardware components are write by hardware description language verilog, on fpga piece
Programmable logic resource is comprehensively realized；Software section is write by c language, runs in the soft core of the nios-ii on fpga chip.
Data analytical capabilities are completed by mvb decoder module, and mvb level shifter interface realizes the conversion of physical level.Data
Resolving is all realized by hardware, parses Frame at a high speed, in real time therefore, it is possible to meet.
Writing function is then completed by nios-ii processor, caching sram read-write controller, spi Interference fit.nios-ii
Operation is relative complex, be not easy to hard-wired fat32 (file allocation table) file system protocol and sd card passes
Defeated agreement, but caching read-write controller is responsible for simple, repetition a large amount of, the data carrying work of high speed, without processor
The extra intervention of kernel, nios-ii produces data flow and decodes the data flow obtaining under the cooperation of sequential through spi interface, writes
Enter sd card.Data in sd card is to remove frame head postamble, manchester decoder and verify confirmation data correct frame letter through crc
Breath, the bus data making data volume more original is greatly less.
Compared with prior art, the invention has the advantages that
1) soft or hard combination, reliability are high, and system takes full advantage of flush bonding processor kernel and PLD
Cooperative work of software and hardware advantage, system hardware is responsible for the mvb decoding function data that processing data amount is big, algorithm is relatively single and is delayed
Deposit, and relative complex, be not easy to hard-wired file system protocol and sd card host-host protocol then by nios-ii processor with soft
The mode of part completes.
2) easy to operate, real-time is good, and system is to install with car, in the way of in-service monitoring mvb bus, realize in real time,
For a long time, collect the condition monitoring and fault diagnosis information of the mvb equipment on train incessantly, for analysis train and equipment
Reliability of operation provides foundation with security.
Brief description
Fig. 1 is the mvb data decoding based on sopc technology and the system block diagram with car record system；
Fig. 2 is mvb decoder module built-in system block diagram；
Fig. 3 is identification and the corresponding state transfer schematic diagram of start delimiter.
Specific embodiment
The present invention is described in detail with specific embodiment below in conjunction with the accompanying drawings.
Embodiment
Fig. 1 is the mvb data decoding based on sopc technology and the system block diagram with car record system.Including:
The soft core of nios-ii, runs sd card host-host protocol and fat32 file system protocol program, for supporting fat32 file system
Sd card under system is read and write and is designed；
Epcs serial flash chip is as program storage, and the epcs controller that bootstrap is downloaded and loaded；
Sdram chip is as the internal memory of processor, and the sdram controller controlling memory read-write；
Phase Locked Loop Frequency Doubler (pll), provides the system work clock of high speed for the soft core of nios-ii；Decode for mvb, simultaneously
Data memory module provides the work clock being several times as much as mvb baud rate, and the work clock of decoding should be greater than the mvb of twice in theory
Baud rate, and multiple more high-resolution and fault-tolerance stronger, but be limited to frequency multiplication of phase locked loop output highest frequency, fpga device
Part performance and the principle as far as possible reducing power consumption, should consider stability, fault-tolerance and feasibility option suitable clock frequency
Rate (adopts the work clock of 24mhz, empirical tests are stable and reliable in work) in the design actual test；
Mvb decoder completes whole work of mvb data decoding, decodes the serial data obtaining at transformation from serial to parallel
After reason, sram chip caching is write by sram read-write controller；
Sram chip is61wv5128bll, 512k × 8bit high-speed asynchronous cmos static state ram, solves high speed write sd card
The not enough problem of caching in required fpga piece；
Sram read-write controller adopts the method for data flow control of ping-pong operation, will be divided into " buffering area in sram space
A " and " buffering area b ", the input of data is always continuous with output, alternate cycles are carried out in two buffering areas.The input of data
From the decoded data of mvb, data output, to turning serial and format converting module parallel, eventually passes spi interface switching mould
Block writes sd card.
Spi interface switching module, for controlling the decoding data stream caching in sram and being derived from nios-ii data flow
Sd card read-write switching.From the mass data of the decoding caching of sram, and the sd card initialization from nios, Read-write Catrol refer to
The bottom layer driving such as order, fat32 file system read sd card system boot sector, update number produced by the operation such as file allocation table
According to stream, pass through spi interface under the cooperation of sequential, complete the storage of data.
Fig. 2 is the inside composition frame chart of mvb decoder module, according to the top-down design concept of fpga system, by its point
Solve for delimiter identification (include prime frame frame head identification, from frame frame head identification, postamble identification), manchester decoder, crc verification,
Timer, bus exception management, decoding process control unit.
Decoding process control unit, enables, resetting decodes each submodule.The control flow of decoding: known by delimiter
Realizing frame alignment, manchester decoder module decodes prime frame, crc checker verification data to other module, obtains after function code really
Fixed reply from frame format, then be decoded to from frame.
Timer, for judging the timing not responded from frame timeout；
Bus exception management unit, for collecting the abnormal signal of each unit feedback, feeds back to decoding control unit.Bus
Exception include manchester decoder exception, crc assay mistake, frame length mistake, do not respond from frame timeout.
Fig. 3 is that fsm (finite state machine, finite state machine) method is realized from the detection of frame start delimiter
State transition diagram.Because mvb baud rate is 3mbaud, each code element time of staying in bus is 1/3us, makes in theory
Just signal can be reduced with the sample rate (i.e. 6mhz sample rate) of twice mvb baud rate, but in order to improve resolution ratio
And fault-tolerance, often adopt the high sample rate of any as far as possible；But it is limited to the highest frequency of frequency multiplication of phase locked loop output, fpga
Device performance and the principle as far as possible reducing power consumption, so it is suitable to consider stability, fault-tolerance and feasibility option
Clock frequency.
Below taking the sample rate of 24mhz as a example, the concrete steps applying fsm method to realize frame synchronization to be described.24mhz's
Sample rate, i.e. 8 sampled points of next code element of ideal situation correspondence.If to first code element from frame start delimiter in Fig. 3
Sampled, in figure designates the 1st to 10 sampling point position, 8 high level ideally should be detected, but due to channel
The impact of the factors such as noise can be slightly offset from the high level of 8 sampled points, and therefore we set 6～10 sampled points and as high level are
Judge that this code element is errorless as high level, that is, (i.e. the length of the code element of in figure indication) is 6～10 this symbol level duration
The time of sampled point.It is detected by low level if counting and being not up to 6 high level, or count full 10 high level still the 11st
If individual sampled point high level is detected then it is assumed that this code element of this symbol error is a code element of delimiter, return just
The state beginning re-starts detection (in practice except first code element of delimiter, next section illustrates)；If this code element is
One code element of Manchester's code, then it is assumed that Manchester's code mistake, produces an abnormal signal and feeds back to decoding process
Control unit simultaneously records.Obviously this is the processing method that two neighboring code element is when varying level, if two neighboring code element
For same level, then detect that the duration of same level is no longer 6～10 sampled points, but 12～20 sampled points (2
Times 6～10 sampled points), adjacent three code elements be same level situation can the like, in figure is with m～n sampling
Point unified representation.
So how said method to be realized by finite state machine？Initial state is set to s0 and works as it by us
When a high level is detected (the state transition condition ' 1 ' of in figure), it just enters state s1_1, is now first code element
First sampled point；If it detects low level always, rest on original state s0 always.Counting not up to 6
Before high level, it is the state that s1_1 is not up to level duration lower limit, when the high level reaching 6 sampled points
When (i.e. state transition condition m ' 1 ' of in figure), it just enters state s1_2 and reaches lower limit but not less than the upper limit
State, but in fact, the first of delimiter code element is more special, is probably one section of duration unknown bus before it
On acquiescence level, therefore it does not have the upper limit, as long as high level is detected, it is just always held at state s1_2；Positive reason
Under condition, for example, detect second state s2_2 of second code element, when the low level being consecutively detected is more than n, it should
Return to original state s0.The detection of ensuing each code element, including the detection of single code element, the adjacent code element of level identical
(m, n value certainly setting is different), all can analogize down according to the method, be finally reached when it redirects condition by these
During the state of low order end, illustrate that it has been completed the detection of last code element to delimiter so far, decompose from frame
Symbol identification module successfully identifies from frame frame head, the signal synchronous from frame is fed back to decoding control unit, and decoding controls single
Unit enables manchester decoder module and carries out follow-up decoding effort.The detection of other delimiters in the same manner, manchester decoder
Method is also to copy this thinking to be designed.
Derive, check, analyzing the raw data file of record in sd card for convenience, needing supporting corresponding host computer
Data is carried out with the process in later stage.Using under microsoft visual studio 2010 translation and compiling environment in exploitation, use
Pc end software write in c# language.
The function of software includes the position definition according to User Defined mvb device diagnostic word table or frame, the frame number to record
According to being parsed, obtain the information such as mvb device name, logical address (port numbers), device address, fault type, state change,
The change of mvb equipment state and the fault being likely to occur when allowing users to more intuitively analyze train operation.
As follows with the concrete operation step of car in-service monitoring mvb bus using the system:
Step 1: need to for mvb data real-time decoding record system provide 5v power supply power, by the mvb interface of system connect to
The mvb bus of train, after system electrification, initializes to sd card first, and reads sd card file system information, confirms sd card
It is formatted as fat32 file system；Now system starts the data in bus to be carried out decode in real time, incessantly, and
Recorded on sd card.
Step 2: when needing to check data, need to take off being inserted in sd card in system sd draw-in groove, if selecting jumbo
, it is assumed that system 24 hours is incessantly to mvb bus monitoring, decoded data amount is pressed for the sd card of sd card, such as 32g
100kbyte/s counts, then can store the data of 3.79 days.If exceeding the time limit not change sd card, new data will cover old number
According to.
Step 3: the sd taking off card is connected to pc machine, by supporting corresponding software, the function one of software is permissible
Derive the data file of record in sd card, check and remove frame head postamble, the data after crc verification, manchester decoder；Two are
User further can be solved to the data that these record by the position definition of self-defined mvb device diagnostic word table or frame
Analysis, obtains the information such as mvb device name, logical address (port numbers), device address, fault type, state change, enables users to
The change of mvb equipment state and the fault being likely to occur during enough more intuitively analysis train operations.
Whole system can be installed with car, keeps long-time, monitors mvb bus incessantly, carry out reality to bus data
When ground decoding, storage.The DAS at supporting pc end, facilitates and extracts further, analyzes status information and fault message,
And the classification of information and preservation.Condition monitoring and fault diagnosis information to the mvb equipment on train and analysis, permissible
For analyzing and ensureing the offer foundation of train and equipment reliability of operation and security.
Claims (4)
1. a kind of mvb bus encoding/decoding based on sopc technology with car record system it is characterised in that include fpga chip,
Epcs serial flash chip, sdram chip, sram chip, sd card and mvb level shifting circuit, described fpga chip includes
Nios-ii soft-core processor, Phase Locked Loop Frequency Doubler, mvb decoder, sram read-write controller, spi interface switching module and spi
Interface, described nios-ii soft-core processor respectively with epcs serial flash chip, sdram chip, Phase Locked Loop Frequency Doubler,
Mvb decoder, sram read-write controller and spi interface connect, and described mvb decoder is electric with Phase Locked Loop Frequency Doubler, mvb respectively
Flat change-over circuit and sram read-write controller connect, and described mvb level shifting circuit is connected with mvb bus, and described spi connects
Mouthful handover module is connected with spi interface, sram read-write controller and sd card respectively, described sram read-write controller and sram core
Piece connects；
Mvb decoder completes whole work of mvb data decoding, decodes the serial data obtaining and processes through transformation from serial to parallel
Afterwards, sram chip caching is write by sram read-write controller；
Sram read-write controller, the input of caching is derived from the decoded data of mvb, exports and turns serial and form modulus of conversion parallel
Block, eventually passes spi interface switching module write sd card；
Spi interface switching module, for controlling the decoding data stream of caching and the sd from nios-ii data flow in sram
Card read-write switching；
Also include the mvb DAS at pc end, for deriving, checking, analyze the raw data file of record in sd card, and
Data can be carried out with the process in later stage, specifically include:
According to the position definition of User Defined mvb device diagnostic word table or frame, the frame data of record are parsed, obtains mvb
Device name, logical address, device address, fault type, state change information, allow users to more intuitively analyze train
The change of mvb equipment state and the fault being likely to occur during operation.
2. with car record system, its feature exists a kind of mvb bus encoding/decoding based on sopc technology according to claim 1
Include delimiter identification module, manchester decoder module, crc checker, timer, bus in, described mvb decoder different
Often administrative unit and decoded stream process control unit, described delimiter identification module includes prime frame frame head recognition unit, from frame frame
Head recognition unit and postamble recognition unit, described decoding process control unit respectively with prime frame frame head recognition unit, from frame frame
Head recognition unit, postamble recognition unit, manchester decoder module, crc checker, timer and bus exception management unit are even
Connect, described bus exception management unit is connected with manchester decoder module, crc checker respectively；
Realize frame alignment by delimiter identification module, described manchester decoder module decoding prime frame, described crc school
Test device verification data, determine after obtaining function code reply from frame format, then be decoded to from frame；
Described timer is used for the timing judging not responding from frame timeout；Bus exception management unit is used for collecting each unit anti-
The abnormal signal of feedback simultaneously feeds back to decoding process control unit.
3. with car record system, its feature exists a kind of mvb bus encoding/decoding based on sopc technology according to claim 2
Include manchester decoder exception, crc assay mistake, frame length mistake and from frame timeout not in, described abnormal signal
Response.
4. with car record system, its feature exists a kind of mvb bus encoding/decoding based on sopc technology according to claim 1
Decoding data sram read-write controller being cached in, described spi interface switching module and the sd of nios-ii soft-core processor
Card host-host protocol and data flow produced by fat32 file system protocol program pass through spi interface under the cooperation of sequential, complete
Data real-time, store at high speed.
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