CN101461140A - 循环冗余校验码的可配置并行计算 - Google Patents

循环冗余校验码的可配置并行计算 Download PDF

Info

Publication number
CN101461140A
CN101461140A CNA2007800208084A CN200780020808A CN101461140A CN 101461140 A CN101461140 A CN 101461140A CN A2007800208084 A CNA2007800208084 A CN A2007800208084A CN 200780020808 A CN200780020808 A CN 200780020808A CN 101461140 A CN101461140 A CN 101461140A
Authority
CN
China
Prior art keywords
data
error detection
crc error
detection code
configurable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007800208084A
Other languages
English (en)
Chinese (zh)
Inventor
萨吉尔·塞泽尔
塞伦·托艾尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Queens University of Belfast
Original Assignee
Queens University of Belfast
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Queens University of Belfast filed Critical Queens University of Belfast
Publication of CN101461140A publication Critical patent/CN101461140A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091Parallel or block-wise CRC computation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6508Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6575Implementations based on combinatorial logic, e.g. Boolean circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041Arrangements at the transmitter end
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0061Error detection codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Logic Circuits (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
CNA2007800208084A 2006-04-22 2007-04-13 循环冗余校验码的可配置并行计算 Pending CN101461140A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0607976.8A GB0607976D0 (en) 2006-04-22 2006-04-22 Apparatus and method for computing an error detection code
GB0607976.8 2006-04-22

Publications (1)

Publication Number Publication Date
CN101461140A true CN101461140A (zh) 2009-06-17

Family

ID=36581070

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007800208084A Pending CN101461140A (zh) 2006-04-22 2007-04-13 循环冗余校验码的可配置并行计算

Country Status (10)

Country Link
US (1) US8321751B2 (https=)
EP (1) EP2013975B1 (https=)
JP (1) JP2009534895A (https=)
KR (1) KR20090008263A (https=)
CN (1) CN101461140A (https=)
AT (1) ATE531129T1 (https=)
GB (1) GB0607976D0 (https=)
IL (1) IL194807A0 (https=)
RU (1) RU2008145087A (https=)
WO (1) WO2007122384A1 (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101847999A (zh) * 2010-05-28 2010-09-29 清华大学 一种用循环冗余校验码进行并行校验的方法
CN101702639B (zh) * 2009-11-23 2012-12-19 成都市华为赛门铁克科技有限公司 循环冗余校验的校验值计算方法及装置
CN102891685A (zh) * 2012-09-18 2013-01-23 国核自仪系统工程有限公司 基于fpga的并行循环冗余校验运算电路
CN105099466A (zh) * 2015-08-17 2015-11-25 中国航天科技集团公司第九研究院第七七一研究所 一种用于128位并行数据的crc校验矩阵生成方法
CN113994719A (zh) * 2019-06-07 2022-01-28 梭纳斯株式会社 通信系统、通信方法及通信装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8161365B1 (en) * 2009-01-30 2012-04-17 Xilinx, Inc. Cyclic redundancy check generator
CN101795175B (zh) * 2010-02-23 2014-03-19 中兴通讯股份有限公司 数据的校验处理方法及装置
CN102546089B (zh) * 2011-01-04 2014-07-16 中兴通讯股份有限公司 循环冗余校验crc码的实现方法及装置
US10838799B2 (en) * 2018-08-20 2020-11-17 Micron Technology, Inc. Parallel error calculation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4712215A (en) * 1985-12-02 1987-12-08 Advanced Micro Devices, Inc. CRC calculation machine for separate calculation of checkbits for the header packet and data packet
JPH0795096A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd プログラマブル並列crc生成装置
JP3256517B2 (ja) * 1999-04-06 2002-02-12 インターナショナル・ビジネス・マシーンズ・コーポレーション 符号化回路、回路、パリティ生成方法及び記憶媒体
US6631488B1 (en) * 2000-06-30 2003-10-07 Agilent Technologies, Inc. Configurable error detection and correction engine that has a specialized instruction set tailored for error detection and correction tasks
US7171604B2 (en) * 2003-12-30 2007-01-30 Intel Corporation Method and apparatus for calculating cyclic redundancy check (CRC) on data using a programmable CRC engine

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101702639B (zh) * 2009-11-23 2012-12-19 成都市华为赛门铁克科技有限公司 循环冗余校验的校验值计算方法及装置
CN101847999A (zh) * 2010-05-28 2010-09-29 清华大学 一种用循环冗余校验码进行并行校验的方法
CN101847999B (zh) * 2010-05-28 2012-10-10 清华大学 一种用循环冗余校验码进行并行校验的方法
CN102891685A (zh) * 2012-09-18 2013-01-23 国核自仪系统工程有限公司 基于fpga的并行循环冗余校验运算电路
CN102891685B (zh) * 2012-09-18 2018-06-22 国核自仪系统工程有限公司 基于fpga的并行循环冗余校验运算电路
CN105099466A (zh) * 2015-08-17 2015-11-25 中国航天科技集团公司第九研究院第七七一研究所 一种用于128位并行数据的crc校验矩阵生成方法
CN105099466B (zh) * 2015-08-17 2018-04-17 中国航天科技集团公司第九研究院第七七一研究所 一种用于128位并行数据的crc校验矩阵生成方法
CN113994719A (zh) * 2019-06-07 2022-01-28 梭纳斯株式会社 通信系统、通信方法及通信装置
CN113994719B (zh) * 2019-06-07 2024-04-02 梭纳斯株式会社 通信系统、通信方法及通信装置

Also Published As

Publication number Publication date
GB0607976D0 (en) 2006-05-31
EP2013975B1 (en) 2011-10-26
ATE531129T1 (de) 2011-11-15
EP2013975A1 (en) 2009-01-14
IL194807A0 (en) 2009-09-22
JP2009534895A (ja) 2009-09-24
KR20090008263A (ko) 2009-01-21
WO2007122384A1 (en) 2007-11-01
US20100058154A1 (en) 2010-03-04
RU2008145087A (ru) 2010-05-27
US8321751B2 (en) 2012-11-27

Similar Documents

Publication Publication Date Title
CN101461140A (zh) 循环冗余校验码的可配置并行计算
US7613991B1 (en) Method and apparatus for concurrent calculation of cyclic redundancy checks
KR102068384B1 (ko) 모듈식 및 스케일러블 순환 중복 검사 계산 회로
EP0823161B1 (en) Method and apparatus for detection of errors in multiple-word communications
KR101721449B1 (ko) 프로그래머블 crc 유닛
US8332721B2 (en) Enhanced error detection in multilink serdes channels
US8225187B1 (en) Method and apparatus for implementing a cyclic redundancy check circuit
US7809050B2 (en) Method and system for reconfigurable channel coding
US4712215A (en) CRC calculation machine for separate calculation of checkbits for the header packet and data packet
US20080168323A1 (en) Pipelined Cyclic Redundancy Check for High Bandwith Interfaces
WO2011103741A1 (zh) 数据的校验处理方法及装置
US6848072B1 (en) Network processor having cyclic redundancy check implemented in hardware
US7363573B1 (en) Method and apparatus for a dedicated cyclic redundancy check block within a device
US20030041300A1 (en) Universal device for processing Reed-Solomon forward error-correction encoded messages
US8984385B1 (en) Systems and methods for cyclic redundancy check implementation
US9312883B1 (en) Hierarchical cyclic redundancy check circuitry
Parthasarathy et al. A simplified design of fast error correction module using Reed-Solomon code
Murade et al. The Design and Implementation of a Programmable Cyclic Redundancy Check (CRC) Computation Circuit Architecture Using FPGA
Bennet et al. Computation Of Field Programmable Cyclic Redundancy Checks Circuit Architecture
Ganesh et al. Design and Synthesis of a Field Programmable CRC Circuit Architecture
Shanthi et al. CHIPSCOPE Implementation of CRC circuit architecture

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20090617