CN101458673A - Internal memory module of sequence transmission interface for quick access by address, sequence transmission controller and control method - Google Patents
Internal memory module of sequence transmission interface for quick access by address, sequence transmission controller and control method Download PDFInfo
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- CN101458673A CN101458673A CNA2007101968382A CN200710196838A CN101458673A CN 101458673 A CN101458673 A CN 101458673A CN A2007101968382 A CNA2007101968382 A CN A2007101968382A CN 200710196838 A CN200710196838 A CN 200710196838A CN 101458673 A CN101458673 A CN 101458673A
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Abstract
A memory module for using an address to rapidly access a sequence transmission interface, a sequence transmission controller and control method are provided, the memory comprises a flash memory array; a sequence paralleling converter for receiving a signal transmitted by the sequence mode and generating a control command, an address and access data; an address buffer; an address accumulator for back storing the accumulated address stored at temporary by the address buffer; and a flash memory controller for controlling the data access of the flash memory array. The control method comprises that, when the control command received by the sequence paralleling converter is a common command, the sequence paralleling converter can receive the address subsequently transmitted from the system chip, and can store the address to the address buffer. Then the flash memory controller can access the data of the flash memory array by the address stored at temporary in the address buffer; when the control command received by the sequence paralleling converter is a special command, so that the flash memory controller can directly access the data of the flash memory array by the address stored at temporary in the buffer and need not wait for updating the address.
Description
Technical field
The invention relates to memory modules, sequence transmission controller and the control method of sequence transmission interface, particularly about using memory modules, sequence transmission controller and the control method of the sequence transmission interface that the address gets soon.
Background technology
(Serial Peripheral Interface SPI) is to use fixing field length to transmit different control command (8bits) and 24 bit address to present widely used sequence transmission interface.Could transmit required data bit afterwards, as shown in Figure 1.When chip select signal (CS) is enabled and its address is a consecutive hours continuously, still must repeat to transmit 24 bit address, cause the loss of transmitting usefulness, and can't meet the frequency range demand of present High Speed System.
The system of getting (cache) is generally arranged soon, and the be enabled data volume of access of chip select signal is the length of its fast line taking (cache line) each time, and major part is 16 bytes (bytes)～64 bytes.And chip select signal is when being enabled continuously, the probability nearly 80%～90% that its address is continuous.Therefore, transmit 24 bit address, then can promote data access speed if can reduce.
Summary of the invention
Because the problems referred to above, the purpose of this invention is to provide a kind of memory modules, sequence transmission controller and control method of using the sequence transmission interface that the address gets soon.
For reaching above-mentioned purpose, the present invention uses the memory modules of the sequence transmission interface that the address gets soon to comprise: a flash array; One sequence parallel converters is used for receiving the signal that transmits in the sequence mode and produces control command, address and access data; One Address Register; One address accumulator is to return after being added up in the address that Address Register is kept in to deposit to Address Register; And a flash controller, be used for controlling the data access of flash array.
Its control method is, when the control command that receives when the sequence parallel converters is general orders, the sequence parallel converters can receive from the follow-up address of transmitting of System on Chip/SoC, and be stored into Address Register, the flash controller address of being kept in data of coming the access flash array afterwards with Address Register; And the control command that receives when the sequence parallel converters is when being special command, this moment the address access flash array that flash controller directly keep in Address Register data and do not need to wait for the address renewal.
In addition, the present invention uses the sequence transmission controller of the sequence transmission interface that the address gets soon, comprises: an Address Register stores the access address; One data buffer is in order to store temporal data; One address accumulator is to return after being added up in the address that Address Register is kept in to deposit to Address Register; One address comparator; One instruction control unit receives comparison signal, output control command signal; One sequence parallel converters is used for exporting the signal that transmits in the sequence mode;
Description of drawings
Figure 1 shows that present widely used sequence transmission interface uses fixing field length to transmit the synoptic diagram of different control commands, address bit and data bit.
Fig. 2 uses the Organization Chart of the memory modules of the sequence transmission interface that the address gets soon for the present invention.
Fig. 3 uses the step of System on Chip/SoC in the control method of the sequence transmission interface that the address gets soon for the present invention.
Fig. 4 uses the step of the memory modules of sequence transmission interface in the control method of the sequence transmission interface that the address gets soon for the present invention.
Fig. 5 A shows the sequential chart when the present invention does not have continuity in the address of adjacent enable signal CS, and is single position transmission data.
Fig. 5 B shows the sequential chart when the present invention has continuity in the address of adjacent enable signal CS, and is single position transmission data.
Fig. 6 A shows the sequential chart when the present invention does not have continuity in the address of adjacent enable signal CS, and is dibit transmission data, that is the data of each two position of frequency period transmission.
Fig. 6 B shows the sequential chart when the present invention has continuity in the address of adjacent enable signal CS, and is dibit transmission data, that is the data of each two position of frequency period transmission.
Embodiment
Below with reference to graphic and describe memory modules, sequence transmission controller and the control method that the present invention uses the sequence transmission interface that the address gets soon in detail.
Fig. 2 uses the Organization Chart of the memory modules of the sequence transmission interface that the address gets soon for the present invention.As shown in the drawing, the memory system of the sequence transmission interface that get soon the use address comprises a System on Chip/SoC 100 and a flash memory module 200.When System on Chip/SoC 100 receives the access command of internal storage data, can carry out data access to flash memory module 200.System on Chip/SoC 100 is connected with flash memory module 200 via a plurality of I/O ports.I/O port has comprised system reference frequency SCK, chip enable signal CE_B and plurality of data signal DI, DO etc., and wherein this plurality of data signal is with sequence mode transmission signals.
System on Chip/SoC 100 has comprised micro controller unit (MCU) 110 and sequence transmission controller 120.This sequence transmission controller 120 has sequence parallel converters 126, data buffer 124, instruction control unit 123, Address Register 122, address accumulator 125 and address comparator 121.
The sequence mode that sequence parallel converters 126 (function that comprises serial line interface coder and sequence transmission unit) is the order being responsible for transmitting, address, change into 1,2 or 4 with data transmits and receives.That is sequence parallel converters 126 is to walk abreast/the data kenel conversion of serial, serial no longer repeat specification.Certainly, this sequence parallel converters 126 can be the transmission of single bit sequence, also can be multiple bit sequence transmission, and for example data-signal DI and DO all are used for transmission of data signals.
When micro controller unit (MCU) 110 accesses finish the data of this access command, present access address can be seen through address accumulator 125 and add up, and be stored in Address Register 122.Micro controller unit 110 OPADD signals are to address comparator 121, and the data of being correlated with in the access data buffer 124.When micro controller unit 110 sent new access command, the first OPADD signal of meeting was to address comparator 121.At this moment, sequence transmission controller 120 can see through address comparator 121 earlier, and whether more present access address is identical with the next access address in being temporary in Address Register 122.If the address is identical, represent that corresponding data have continuity, address comparator 121 can be set at first standard with a comparison signal, otherwise is set at second standard.Instruction control unit 123 can be given sequence transmission controller 120 by output one control command signal.When instruction control unit 123 detects after comparison signal is first standard, control command is set at special command, allow sequence transmission controller 120 adopt the communications protocol of special sequence transmission interface.And detect after comparison signal is second standard when instruction control unit 123, control command is set at general orders, allow sequence transmission controller 120 adopt the communications protocol of general sequence transmission interface.That is sequence transmission controller 120 sees through instruction control unit 123 and sends specific order to sequence parallel converters 126.Sequence parallel converters 126 utilizes special command, and for example 0x4bH goes to notify flash memory module 200 to adopt the next address of the address of before last access to come access data.Then, see through sequence parallel converters 126 and begin to receive or transmit data.When if the address does not have continuity, then adopt the communications protocol of the sequence transmission interface of standard to transmit standard reading order, address and data.
Fig. 5 A shows the sequential chart (that is control command is a general orders) when the present invention does not have continuity in the address of adjacent enable signal CS, and Fig. 5 B shows the sequential chart (that is control command is a special command) when the present invention has continuity in the address of adjacent enable signal CS, and is single position transmission data.Can recognize that from Fig. 5 B when the address of adjacent enable signal CS had continuity, signal wire DO promptly began to transmit data in the 8th frequency of frequency signal CLK.Therefore, during the enabling of this enable signal CS, can save the time of transmission 24 bit address.
Fig. 6 A shows the sequential chart (that is control command is a general orders) when the present invention does not have continuity in the address of adjacent enable signal CS, and Fig. 6 B shows the sequential chart (that is control command is a special command) when the present invention has continuity in the address of adjacent enable signal CS, and be dibit transmission data, that is each frequency period transmit two data.Can recognize that from Fig. 6 B when the address of adjacent enable signal CS had continuity, signal wire DO promptly began to transmit data in the 8th frequency of frequency signal CLK.Therefore, during the enabling of this enable signal CS, can save the time of transmission 24 bit address.
The communications protocol of the sequence transmission interface of standard is after sending 8 order of the bit and 24 bit address earlier, again access data.And the communications protocol of special sequence transmission interface is after sending 8 special commands, need not wait for any address signal, gets final product direct accessing data.Therefore, if the address has continuity, then the present invention uses the memory modules of the sequence transmission interface that the address gets soon can save the time of transfer address signal.
In addition, as shown in Figure 2, flash memory module 200 comprises a sequence parallel converters 201, address accumulator 203, Address Register 204, flash controller 210 and flash array 205.Flash controller 210 is connected to each other with address and data bus with flash array 205, can be standard JEDEC industry interface or other different flash memory control interface, the no longer repeat specification of its connected mode.
Flash controller 210 comprises command buffer 213, Address Register 212 and data buffer 211.The Address Register 212 of flash controller 210 can read the address of the stored address of Address Register 204 as flash array 205.And the control life life that command buffer 213 meeting receiving sequence parallel converters 201 are exported.And the data buffer 211 of flash controller 210 can be kept in the data from flash array 205 or sequence parallel converters 201, and sends sequence parallel converters 201 or flash array 205 to.
After the data of intact this access command of flash memory module 200 accesses, the address of present institute access can be seen through address accumulator 203 and add up and be stored in Address Register 204.When sequence parallel converters 201 receives general orders, then 24 bit address signals of follow-up reception can be stored into Address Register 204.And after sequence parallel converters 201 receives special command (for example 0x4bH), can stop to receive new address signal, that is data that can scheduler buffer 204.At this moment, flash controller 210 can directly use the address that has stored in the Address Register 204 to come access data, and sees through sequence parallel converters 201 with data back System on Chip/SoC 100.So, after control command that sequence parallel converters 201 receives is special command, can export an access control signal, notice flash memory module 200 need not waited for sequence parallel converters 201 receiver address signals, and directly use the address that has stored in the Address Register 204 to come access data, so, can save the time of sequence parallel converters 201 receiver address signals.
Fig. 3 and Fig. 4 use the control method of the sequence transmission interface that the address gets soon for the present invention, and wherein Fig. 3 is the step of the control method of System on Chip/SoC, and Fig. 4 is the step of control method of the memory modules of sequence transmission interface.It is to comprise the following step that the present invention uses the control method of the sequence transmission interface that the address gets soon:
Step S302: send new access command.
Whether step S304: detecting the address has continuity.Be to detect present access command by a System on Chip/SoC to want the address of memory modules of the sequence transmission interface of the address of memory modules of sequence transmission interface of access and last access command whether continuity is arranged.When continuity, then skip to step 306; When no continuity, then skip to step 308.
Step S306: when there is continuity the address, after System on Chip/SoC is sent control command via a plurality of signal wires, the data of the aforementioned memory modules of direct access, and this control command is a special command.
Step S308: when the address did not have continuity, after System on Chip/SoC was sent control command and M bit address signal in regular turn via a plurality of signal wires, the data of the aforementioned memory modules of access, and this control command again were general orders.
Step S310: after the data of intact this control command of System on Chip/SoC access, the address of last access data is stored to one second Address Register, whether have in successional step, read the address of memory modules of the sequence transmission interface of last institute access from this second Address Register if using detecting the address.
Step S320: receive control command.It is the control command of being sent by the memory modules receiving system chip of sequence transmission interface.
Step S322: judge whether control command is special command.When received control command is a special command, then skip to step S326; When received control command is a general orders, then skip to step S324.
Step S324: scheduler buffer.The address signal that the memory modules receiving system chip of this sequence transmission interface is transmitted, and write one first Address Register.
Step S326: access data.The address that the memory modules of this sequence transmission interface is kept in according to first Address Register, and then the data of access flash array.
Step S328: after the data of intact this control command of the memory modules access of this sequence transmission interface, the back of adding up, the address of aforementioned first Address Register is returned and deposited to aforementioned first Address Register.
Because the present invention uses the address to get soon and the sequence transmission interface of multidata position output when having continuity with method in the address, System on Chip/SoC can not need the transport address signal to memory modules, and then the raising System on Chip/SoC is for the data access speed of memory modules.Though the above illustrates the present invention with embodiment the present invention, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, the sector person can carry out various distortion or change.
Claims (6)
1. memory modules that uses the sequence transmission interface that the address gets soon is characterized in that this memory modules comprises:
One sequence parallel converters, be to receive a reference frequency signal, a chip enable signal of a System on Chip/SoC and control command signal, address signal and the data-signal that is transmitted in the sequence mode via a plurality of signal wires, and then export a control command, an address bus signal and a data bus signal;
One flash array is to be used for storing the aforementioned data bus signals;
One Address Register is in order to as the access address according to the aforementioned addresses bus signals;
One address accumulator after the intact data of the memory modules access of this sequence transmission interface, after adding up in this address accumulator this access address that the aforementioned addresses buffer is stored, and then is returned and is deposited to the aforementioned addresses buffer; And
One flash controller, be to receive aforementioned control command and receive the stored access address of aforementioned addresses buffer, in order to the data access in the aforementioned flash array is controlled, this flash controller give this sequence parallel converters with the data transmission that is read in the aforementioned flash array or the data storing that received from this sequence parallel converters to aforementioned flash array;
Wherein, after this control command signal that aforementioned sequence parallel converters receives is general orders, aforementioned sequence parallel converters can this control command signal is follow-up part position signal be stored in the aforementioned addresses buffer as the access address, aforementioned afterwards flash controller begins to carry out the access of data; After this control command signal that aforementioned sequence parallel converters receives was special command, aforementioned flash controller began access data.
2. the memory modules of the sequence transmission interface that get soon the use address of being put down in writing according to claim 1 is characterized in that aforementioned sequence parallel converters can utilize single position to carry out data transmission.
3. the memory modules of the sequence transmission interface that get soon the use address of being put down in writing according to claim 1 is characterized in that aforementioned sequence parallel converters can utilize multiple position to carry out data transmission.
4. control method of using the sequence transmission interface that the address gets soon, this sequence transmission interface is to utilize a plurality of signal wires to transmit control command, M bit address and plural byte data in the sequence mode by a System on Chip/SoC to give a memory modules, this System on Chip/SoC begins memory modules is carried out access action after receiving an access command, it is characterized in that this control method is to comprise the following step:
Detect the access address whether continuity is arranged, be to want before the access address of the aforementioned memory modules of access and the access command once by this access command of aforementioned system chip detection whether the access address of the aforementioned memory modules of institute's access has continuity, wherein, when this access address does not have continuity, after the aforementioned system chip is sent this control command and this M bit address in regular turn via aforementioned a plurality of signal wires, data in the aforementioned memory modules of access again, and this control command is a general orders, when there is continuity this access address, after the aforementioned system chip is sent this control command via aforementioned a plurality of signal wires, and then the data of the aforementioned memory modules of direct access, and this control command is a special command;
Aforementioned memory modules receives the aforementioned control command that the aforementioned system chip is sent, it is characterized in that,
When the received aforementioned control command of aforementioned memory modules is aforementioned general orders, this memory modules is stored in one first Address Register with this M bit address of follow-up reception, and then upgrade aforementioned access address, go to receive or transmit data and give the aforementioned system chip according to this stored access address of this first Address Register again;
When the received aforementioned control command of aforementioned memory modules was aforementioned special command, then this memory modules directly went to receive or transmits data and give the aforementioned system chip according to this stored access address of aforementioned first Address Register; And
After the data of intact this access command of the memory modules access of this sequence transmission interface, the back of adding up, this access address of last institute access is returned and deposited to aforementioned first Address Register.
5. the control method of the sequence transmission interface of getting soon as the use address of being put down in writing as described in the claim 4, after it is characterized in that the data of intact this access command of aforementioned system chip access, this access address of last institute access is stored to one second Address Register, use when whether having continuity, write down the address of internal memory of the sequence transmission interface of last access with this second Address Register in this access address of aforementioned detection.
6. sequence transmission controller that uses the sequence transmission interface that the address gets soon, be to export control command signal, M bit address signal and the number of it is believed that of complex digital joint number with a plurality of signal wires in the sequence mode to give a memory modules, this sequence transmission controller is to be disposed in the System on Chip/SoC, and this System on Chip/SoC begins memory modules is carried out access action after receiving an access command, it is characterized in that this sequence transmission controller comprises:
One Address Register is to store the access address;
One data buffer is in order to store temporal data;
One address accumulator after the data of the intact access that this access command is desired of this sequence transmission controller access, after adding up in this address accumulator access address that the aforementioned addresses buffer is stored, is deposited and is back to the aforementioned addresses buffer;
One address comparator, be whether access address stored in the comparison of aforementioned Address Register is identical with the access address of the access command access of wanting at present of this sequence transmission controller, and then produce a comparison signal and an address signal, wherein, when this access address is identical, this comparison signal is first standard, otherwise this comparison signal is second standard;
One instruction control unit is to receive aforementioned comparison signal, and then exports a control command signal, wherein when this comparison signal be first punctual, this control command signal is a special command, and when this comparison signal be second punctual, this control command signal is a general orders; And
One sequence parallel converters, be to export a reference frequency and a chip enable signal according to aforementioned control command signal, and export after converting this address signal that aforementioned control command signal and aforementioned addresses comparer are exported to sequence signal, and data-switching temporary in the aforementioned data buffer become sequence signal output, or be stored in the aforementioned data buffer after receiving the sequence signal of aforementioned memory modules;
Wherein, when aforementioned comparison signal be first punctual, aforementioned sequence parallel converters can promptly begin to receive or transmit this data-signal behind the aforementioned control command signal of output; And aforementioned sequence parallel converters can then be exported aforementioned M bit address signal behind the aforementioned control command signal of output on time when aforementioned comparison signal is second, just begins to receive or transmit this data-signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2007101968382A CN101458673A (en) | 2007-12-11 | 2007-12-11 | Internal memory module of sequence transmission interface for quick access by address, sequence transmission controller and control method |
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| CNA2007101968382A CN101458673A (en) | 2007-12-11 | 2007-12-11 | Internal memory module of sequence transmission interface for quick access by address, sequence transmission controller and control method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102087633A (en) * | 2009-07-17 | 2011-06-08 | 旺宏电子股份有限公司 | Serial flash memory and address transmission method thereof |
| CN103838689A (en) * | 2012-11-23 | 2014-06-04 | 普诚科技股份有限公司 | Interface transmission method and data structure production |
| CN107402714A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method and serial flash for the write operation of serial flash |
-
2007
- 2007-12-11 CN CNA2007101968382A patent/CN101458673A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102087633A (en) * | 2009-07-17 | 2011-06-08 | 旺宏电子股份有限公司 | Serial flash memory and address transmission method thereof |
| CN102087633B (en) * | 2009-07-17 | 2012-09-26 | 旺宏电子股份有限公司 | Serial flash memory and address transmission method thereof |
| CN103838689A (en) * | 2012-11-23 | 2014-06-04 | 普诚科技股份有限公司 | Interface transmission method and data structure production |
| CN103838689B (en) * | 2012-11-23 | 2016-11-23 | 普诚科技股份有限公司 | Interface transmission method and data transmission system |
| CN107402714A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method and serial flash for the write operation of serial flash |
| CN107402714B (en) * | 2016-05-20 | 2020-06-02 | 中芯国际集成电路制造(上海)有限公司 | Method for writing operation of serial flash memory and serial flash memory |
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Open date: 20090617 |