CN101453219B - Money search circuit and money search method using the circuit - Google Patents
Money search circuit and money search method using the circuit Download PDFInfo
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- CN101453219B CN101453219B CN2007101715660A CN200710171566A CN101453219B CN 101453219 B CN101453219 B CN 101453219B CN 2007101715660 A CN2007101715660 A CN 2007101715660A CN 200710171566 A CN200710171566 A CN 200710171566A CN 101453219 B CN101453219 B CN 101453219B
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Abstract
The invention provides a money search circuit which comprises a master control state machine, an error positioning circuit and a shift unit array, wherein the shift unit array is used for carrying out shift operation on a Delta operator to generate every bit of a new Delta operator, and sending the generated Delta operator to the error positioning circuit; the shift unit array carries out the parallel processing on the Delta operator during each clock cycle; the error positioning circuit is used for detecting whether the newly generated Delta operator sent from the shift unit array has an error; and if the error is detected, the error positioning circuit indicates the specific position of the error. The money search circuit adopts a circuit structure combining the parallel processing and pipelining technology, thereby ensuring speed increase without greatly increasing circuit cost.
Description
Technical field
The invention belongs to the data communication field, relate to a kind of Method and circuits that is used for the error correction decode process, relate in particular to a kind of money search method of realizing the money search circuit of money searching algorithm and utilizing this money search circuit.
Background technology
Error-correcting code technique is widely used at aspects such as data communication, storage.Common error correcting code has now: RS (Reed-Solomon) sign indicating number, BCH code, Hamming code.Wherein Hamming code can only be corrected a bit-errors because code distance is less.And the RS sign indicating number, BCH can carry out many bit error correction, thereby uses very extensively.The money searching algorithm is a kind of algoritic module commonly used in BCH, the RS decoding.
The money search procedure comes down to a process of testing root.Need search check by turn with traditional algorithm; Adopt the mode of serial process; Also promptly clock cycle can only be handled the data of a bit, and regular software decode system etc. adopt this method to the not high application system of rate request, but this is for to the demanding data communication system of data transmission rate; And memory device all can cause bottleneck, seriously restricted data transmission bauds/storage speed.
In order to improve the problem of money searching algorithm speed; Generally can adopt the mode of parallel processing, and realize, for a N parallel-by-bit treatment circuit with hardware circuit; It can reach the processing speed of N bit/clockcyle in theory, and slow-footed problem is to have solved.But owing to adopt simple parallel processing circuit structure; Make its circuit scale also amplify N basically doubly; Increased the cost of realizing widely, and increased the system power dissipation expense, this obviously also is not too to be fit to for the application scenario to cost and sensitive power consumption.
Summary of the invention
The purpose of this invention is to provide a kind of money search circuit that can reduce money search cycle number and take into account the realization cost.
Another object of the present invention provides a kind of money search method that utilizes above-mentioned money search circuit.
To achieve these goals, the present invention provides a kind of money search circuit, is connected with Delta operator circuit, and Delta operator circuit output Delta operator is to this money search circuit; This money search circuit comprises major state machine, location of mistake circuit, reaches the shift unit array; Said location of mistake circuit, shift unit array are connected with said major state machine; Each shift unit is connected with said location of mistake circuit in the said shift unit array; Said major state machine is in order to control each shift unit and said location of mistake circuit in the said shift unit array; Said shift unit array in order to said Delta operator is carried out shifting function, generates the every of new Delta operator; And the Delta operator of above-mentioned generation delivered to said location of mistake circuit; Said each clock cycle of shift unit array is carried out parallel processing to said Delta operator; Said location of mistake circuit, whether wrong through detecting the newly-generated Delta operator that sends from said shift unit array if detecting communication data; If detect mistake, the particular location that points out faults.
As a kind of preferred version of the present invention, the result of calculation of said shift unit this clock cycle of array is used to calculate the numerical value of next clock cycle.
As a kind of preferred version of the present invention, the line number of said shift unit array is corresponding with the error correction figure place; The columns and the pipeline series of said shift unit array are corresponding; The line number of shift unit array and columns are more than or equal to 2.
As a kind of preferred version of the present invention, said error correction figure place is 4, and said pipeline series is 8, and said shift unit array is the array of 4 row, 8 row.
The present invention also provides a kind of money search method that utilizes above-mentioned money search circuit; The process that is used for error correction decode; This method comprises: parallel shifting function step; The shift unit array carries out shifting function to the Delta operator, generates new Delta operator everybody, and the Delta operator of above-mentioned generation is delivered to said location of mistake circuit; Said each clock cycle of shift unit array is carried out parallel processing to several Delta operators; Searching and detecting error bit step, whether the newly-generated Delta operator that said location of mistake circuit sends from said shift unit array through detection detects communication data wrong; If detect mistake, the particular location that points out faults.
As a kind of preferred version of the present invention, the result of calculation of said shift unit this clock cycle of array is used to calculate the numerical value of next clock cycle.
As a kind of preferred version of the present invention, the line number of said shift unit array is corresponding with the error correction figure place; The columns and the pipeline series of said shift unit array are corresponding; The line number of shift unit array and columns are more than or equal to 2.
As a kind of preferred version of the present invention, said error correction figure place is 4, and said pipeline series is 8, and said shift unit array is the array of 4 row, 8 row.
As a kind of preferred version of the present invention, said money search method also comprises the system mode control procedure, specifically comprises: the idle condition controlled step, and system is in idle condition after the system reset, and each module of money search circuit all is in off position; Get into the ready state step, the major state machine is received enable signal, if effectively, gets into ready state; Zero padding State Control step, major state machine are waited for the Delta input signal of Delta operator circuit, and be effective if the major state machine examination measures said Delta input signal, shows that said Delta input signal is ready, and system gets into the zero padding state; The search condition controlled step, when search check beginning, major state machine system mode is set to search condition; Search completion status controlled step, after search finished, system got into the search done state, and output search end signal, and the search completion status is only kept a clock cycle, and idle condition will be got back to by system.
As a kind of preferred version of the present invention, the line number of said shift unit array is that I, columns are J, and system is provided with the BIT of last byte search condition, last byte
J-2Search done state, BIT
J-3The search done state ..., BIT
1Search done state, BIT
0The search done state.
Compared with prior art, beneficial effect of the present invention is following: the circuit structure that the present invention adopts a kind of parallel processing and pipelining to combine, and make it when guaranteeing raising speed, the cost of circuit can not improve a lot.
Description of drawings
Fig. 1 is the workflow diagram of BCH error correction circuit.
Fig. 2 is the composition sketch map of money search circuit of the present invention.
Fig. 3 is a major state machine state transitions sketch map.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done concrete introduction.
Embodiment one
See also Fig. 1, the BCH error correction circuit comprises S operator circuit, Delta operator circuit, the money search circuit that is used for the money searching algorithm, the errors present output circuit that connects successively.Wherein S operator circuit is used for accepting the input data and producing syndrome S operator; Delta operator circuit input S operator also produces the delta operator, and Delta operator circuit is invert circuit and field element mlultiplying circuit of IncFlds element also; The money search circuit is as important module in the BCH decode system.The money search circuit receives the Delta operator signal that Delta operator circuit produces, through the displacement and the logical operation of a series of complicacies, but final misjudgment position and produce the positional information of error bit; The errors present output circuit is used for record and output error position.
For convenience of description, present embodiment is decoded as example with 512Byte, 4bit error correction BCH code, adopts 8 stage pipeline structure.Its code length n=2
m-1=8191; Wherein, primitive polynomial number of times m=13.
Actual coding length 4148, data bit length 4096bit wherein, check digit length 52bit.Because actual coding length does not reach the length that the bch sign indicating number needs, be employed in the way polishing length of head benefit 0 on the algorithm.Be think on the algorithm coding after data: 0-51bit is a check digit, and 52-4147bit is a data bit, and 4148-8190bit is 0.Having obtained after the delta coefficient, in fact is exactly to have obtained the bit-error locations equation, but directly finds the solution this equation and be not easy, so with the substitution one by one of possible position, if equation is set up after certain position substitution, then this position is exactly an errors present.
For judging whether highest order is wrong, a
N-1A substitution equation reciprocal:
delta(a)＝delta
1(a)+delta
2(a)
2+....+delta
v(a)
v
If delta (a)=1 explanation highest order is wrong.
Whether wrong for judging a time high position, a
N-2A reciprocal
2The substitution equation:
delta(a
2)＝delta
1(a
2)+delta
2(a
2)
2+....+delta
v(a
2)
v
From top process, can see if testing the root process begins from highest order, thereby then the back can utilize previous result to reduce operand at every turn.4096 of the present invention's one total data bit are so if search needs 4096 cycles at least by turn.In order to reduce the periodicity that the money search needs, adopted the way of 8 parallel-by-bits search, simultaneously in order to reduce area, adopted 8 grades of flowing structures from algorithm.Each is calculated the corresponding delta operator of bit7 clock cycle, and bit6 then utilizes the result of bit7 to calculate in the next clock cycle, and bit5 then postpones two clock cycle and utilizes the result of bit6 to calculate, and the like.
See also Fig. 2, the present invention has introduced a kind of money search circuit of realizing the money searching algorithm, is connected with Delta operator circuit, and Delta operator circuit output Delta operator is to this money search circuit; This money search circuit comprises major state machine, location of mistake circuit, reaches the shift unit array; Said location of mistake circuit, shift unit array are connected with said major state machine; Each shift unit is connected with said location of mistake circuit in the said shift unit array.
Said major state machine is in order to control each shift unit and said location of mistake circuit in the said shift unit array.Said shift unit array generates the every of new Delta operator in order to said Delta operator is carried out shifting function; And the Delta operator of above-mentioned generation delivered to said location of mistake circuit; Said each clock cycle of shift unit array is carried out parallel processing to said Delta operator.Whether the newly-generated Delta operator that said location of mistake circuit sends from said shift unit array through detection detects communication data wrong; If detect mistake, the particular location that points out faults.The result of calculation of said shift unit this clock cycle of array is used to calculate the numerical value of next clock cycle.
Wherein the shift unit array is a main arithmetic element, for 512Byte, 4bit error correction BCH decode system, 4 Delta operators (1～4) is arranged, and adopts 8 stage pipeline structure; Need to use 4 * 8=32 shift unit altogether, the shift unit array will carry out a series of specific shifting functions to the Delta operator of input, generate the bit7 of Delta operator; Bit6 ... bit1, bit0 (bit7; Bit6 ... bit1, bit0 refer to the 7th to the 0th of Delta operator respectively); The bit7 of the Delta operator that the shift unit array produces, bit6 ..., intermediate data such as bit1, bit0 will deliver to a location of mistake circuit; Through handling the particular location that can obtain error bit (if wrong generation): Error_byte (error byte position) and Error_bit (error bit position), error flag signal Error_find is found in output simultaneously.
The present invention has also introduced the money search method that utilizes above-mentioned money search circuit; Because the major state machine is in order to controlling each shift unit and said location of mistake circuit in the said shift unit array, so the process of controlling other module status through the major state machine is introduced the flow process of money search method of the present invention.
The process of system mode control sees also Fig. 3, specifically comprises:
(1) idle condition controlled step, system is in IDLE (free time) state after the system reset; At the IDLE state, each position of system's (being whole money search circuit) all is in off position.
(2) get into the ready state step, the major state machine is waited for the enable signal Chien_en of applications end (Delta operator circuit), in case that system detects Chien_en is effective, system can leave the IDLE state and get into " DELTA_READY " (ready) state.
(3) zero padding State Control step; At " DELTA_READY " state; The Delta signal useful signal Delta_ready of system wait applications end (Delta operator circuit); In case it is effective that system detects Delta_ready, show that the Delta input signal is ready, system can leave " DELTA_READY " state and get into " SKIP_ZERO " (zero padding) state.
The shifting function that walks abreast under this state, because the input data do not reach the code length that bch requires, can the data head of algorithm be filled out in advance is 0, one to have 4043 zero-bits in the present embodiment.So before reality gets into the money search, need carry out the feedback shift computing, delta1 displacement 4043 times, delta2 displacement 4043*2 time, delta3 displacement 4043*3 time, delta4 displacement 4043*4 time to the delta operator.
(4) search condition controlled step, under this state, shifting function and searching and detecting error bit operation walks abreast.Parallel shifting function step: the shift unit array carries out shifting function to the Delta operator, generates new Delta operator everybody, and the Delta operator of above-mentioned generation is delivered to said location of mistake circuit; Said each clock cycle of shift unit array is carried out parallel processing to several Delta operators.Searching and detecting error bit step: whether said location of mistake electric circuit inspection is wrong from the newly-generated Delta operator that said shift unit array sends; If detect mistake, the particular location that points out faults.Idiographic flow is following.
0 all move after (end of " SKIP_ZERO " state) get into search procedure, corresponding to " DELTA_SHIFT " state of host state machine.For the bit7 of delta1, delta2, delta3, delta4, need previous operation result be shifted 8 times 16 times respectively at every turn; 24 times and 32 times, correspond respectively to " Shift Unit1 " among Fig. 2, " Shift Unit2 "; " Shift Unit3 ", " ShiftUnit4 ".And other bit (bit0～bit6) only need be with the result's of previous bit 1 time (the Delta shift1 in the corresponding diagram 2) of delta1 displacement; Delta2 2 times (the Delta shift2 in the corresponding diagram 2) that be shifted; Delta3 3 times (the Delta shift3 in the corresponding diagram 2) that be shifted, delta4 4 times (the Delta shift4 in the corresponding diagram 2) that be shifted.If do not adopt water operation, then corresponding delta1, delta2, delta3, the delta4 of each other bit of bat also will be shifted 8 times, 16 times, 24 times, 32 times, and needed combinational logic can increase greatly.
Owing to adopted the circuit structure of streamline; So can cause the data processing of last several beats different with the appearance of front; Last 8 clock cycle of algorithm steps (512-519) that the face that specifically sees before is described; For can being discerned in this, hardware distinguishes; And making correct processing, system is provided with " LAST_SEARCH " (last byte search condition), " BIT6_END " (BIT6 search done state of last byte), " BIT5_END " (BIT5 search done state of last byte), " BIT4_END " (BIT4 search done state of last byte), " BIT3_END " (BIT3 search done state of last byte), " BIT2_END " (BIT2 search done state of last byte), " BIT1_END " (BIT1 search done state of last byte), eight states of " BIT0_END " (BIT0 search done state of last byte) specially.These 8 states correspond respectively to last 8 clock cycle of algorithm steps.These 8 states are carried out successively, need 8 clock cycle altogether.
(5) search completing steps.After last " BIT0_END " finished, system got into " SEARCH_END " (search finishes) state, and output Chien_Search_End signal, shows that the money search procedure finishes." SEARCH_END " state is only kept a clock cycle, and the IDLE state will be got back to by system.
When adopting BCH error correction circuit of the present invention to handle money searching algorithm (512byte 4bit error correction BCH decoding); Owing to used parallel processing technique; The money searching disposal of accomplishing 4096bit (512byte) data only needs 519 clock cycle; And if use conventional serial algorithm then needs 4096 clock cycle, processing speed improves 7.89 times.Simultaneously owing to used pipeline organization; Make and realize that the combinational logic that circuit needs greatly reduces; Reduced the scale of circuit, thereby reduced the cost that system realizes, than traditional simple parallel processing structure; This technology can reduce the system scale/chip area more than 2 times, and processing speed difference is little with it.Because this patented technology has been taken into account processing speed simultaneously and has been realized cost; Be that a kind of algorithm realization very reasonable, that optimize is technological; Be applicable to the BCH, RS decoding circuit and the device that use the money searching algorithm, this technology is specially adapted to speed and all responsive application of cost.
Embodiment two
The difference of present embodiment and embodiment one is that the error correction figure place is 8, and pipeline series is 8; Be that the shift unit array is the array of 8 row, 8 row.Certainly, the line number of shift unit array and columns can be for more than or equal to other values of 2.
Above embodiment is the unrestricted technical scheme of the present invention in order to explanation only.Do not break away from any modification or the local replacement of spirit and scope of the invention, all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1. search circuit is connected with Delta operator circuit, and Delta operator circuit output Delta operator is to this money search circuit; It is characterized in that:
This money search circuit comprises major state machine, location of mistake circuit, reaches the shift unit array;
Said location of mistake circuit, shift unit array are connected with said major state machine; Each shift unit is connected with said location of mistake circuit in the said shift unit array;
Said major state machine is in order to control each shift unit and said location of mistake circuit in the said shift unit array;
Said shift unit array in order to said Delta operator is carried out shifting function, generates the every of new Delta operator; And the Delta operator of above-mentioned generation delivered to said location of mistake circuit; Said each clock cycle of shift unit array is carried out parallel processing to said Delta operator;
Said location of mistake circuit, whether wrong through detecting the newly-generated Delta operator that sends from said shift unit array if detecting communication data; If detect mistake, the particular location that points out faults.
2. money search circuit as claimed in claim 1 is characterized in that the result of calculation of said shift unit this clock cycle of array is used to calculate the numerical value of next clock cycle.
3. money search circuit as claimed in claim 1 is characterized in that, the line number of said shift unit array is corresponding with the error correction figure place; The columns and the pipeline series of said shift unit array are corresponding; The line number of shift unit array and columns are more than or equal to 2.
4. money search method as claimed in claim 3 is characterized in that, said error correction figure place is 4, and said pipeline series is 8, and said shift unit array is the array of 4 row, 8 row.
5. utilize the money search method of the said money search circuit of claim 1, be used for the process of error correction decode, it is characterized in that, this method comprises:
Parallel shifting function step, the shift unit array carries out shifting function to the Delta operator, generates new Delta operator everybody, and the Delta operator of above-mentioned generation is delivered to said location of mistake circuit; Said each clock cycle of shift unit array is carried out parallel processing to several Delta operators;
Searching and detecting error bit step, whether wrong through detecting the newly-generated Delta operator that sends from said shift unit array if detecting communication data; If detect mistake, the particular location that points out faults.
6. money search method as claimed in claim 5 is characterized in that the result of calculation of said shift unit this clock cycle of array is used to calculate the numerical value of next clock cycle.
7. money search method as claimed in claim 5 is characterized in that, the line number of said shift unit array is corresponding with the error correction figure place; The columns and the pipeline series of said shift unit array are corresponding; The line number of shift unit array and columns are more than or equal to 2.
8. money search method as claimed in claim 7 is characterized in that, said error correction figure place is 4, and said pipeline series is 8, and said shift unit array is the array of 4 row, 8 row.
9. money search method as claimed in claim 5 is characterized in that, said money search method also comprises the system mode control procedure, specifically comprises:
The idle condition controlled step, system is in idle condition after the system reset, and each module of money search circuit all is in off position;
Get into the ready state step, the major state machine is received enable signal, if effectively, gets into ready state;
Zero padding State Control step, major state machine are waited for the Delta input signal of Delta operator circuit, and be effective if the major state machine examination measures said Delta input signal, shows that said Delta input signal is ready, and system gets into the zero padding state;
The search condition controlled step, when search check beginning, major state machine system mode is set to search condition;
Search completion status controlled step, after search finished, system got into the search done state, and output search end signal, and the search completion status is only kept a clock cycle, and idle condition will be got back to by system.
10. money search method as claimed in claim 9 is characterized in that, the line number of said shift unit array is that I, columns are J, and system is provided with the BIT of last byte search condition, last byte
J-2Search done state, BIT
J-3The search done state ..., BIT
1Search done state, BIT
0The search done state.
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| CN2007101715660A CN101453219B (en) | 2007-11-30 | 2007-11-30 | Money search circuit and money search method using the circuit |
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| CN102957437B (en) * | 2012-10-29 | 2016-03-30 | 记忆科技(深圳)有限公司 | A kind of money search method and device |
| CN103916138B (en) * | 2012-12-28 | 2018-03-16 | 深圳开阳电子股份有限公司 | A kind of money search circuit and ECC decoding apparatus and method based on the money search circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1658515A (en) * | 2005-03-21 | 2005-08-24 | 中国人民解放军空军工程大学 | Key equation solving circuit of read-solomon decoder |
| CN1252937C (en) * | 2000-03-27 | 2006-04-19 | 松下电器产业株式会社 | Decoder and decoding method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1252937C (en) * | 2000-03-27 | 2006-04-19 | 松下电器产业株式会社 | Decoder and decoding method |
| CN1658515A (en) * | 2005-03-21 | 2005-08-24 | 中国人民解放军空军工程大学 | Key equation solving circuit of read-solomon decoder |
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