CN201898502U

CN201898502U - BCH coding/decoding circuit

Info

Publication number: CN201898502U
Application number: CN2010206001024U
Authority: CN
Inventors: 曹晓冬; 吕前进; 张鹏泉; 李续; 范玉进; 赵维兵; 张波; 李柬; 刘欣; 宋光伟; 王文亮
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2010-11-10
Filing date: 2010-11-10
Publication date: 2011-07-13
Anticipated expiration: 2020-11-10

Abstract

The utility model relates to a BCH (Broadcast Channel) coding/decoding circuit, which comprises an FPGA (Field Programmable Gata Array) device. The internal circuit connection of the FPGA device is that: a controller is connected with a coding input storer, a BCH encoder, a coding output storer, a decoding input storer, a BCH decoder and a decoding output storer via a control wire; the coding input storer and the coding output storer are respectively connected with the BCH decoder via data cables; and the decoder input storer and the decoding output storer are respectively connected with the BCH decoder via data cables. The BCH coding/decoding circuit has the advantages that firstly, standby code modes are abundant and can be configured into an arbitrary BCH code with an n less than 1024, the control method is simple, and the operation is flexible and convenient; secondly, a specially designed coding/decoding algorithm is adopted, so that the operation is rapid and convenient; and thirdly, a programmable logic device is adopted, so that the structure is simple and the reliability is high.

Description

The Bose-Chaudhuri-Hocquenghem Code decoding circuit

Technical field

The utility model relates to the channel encoding/decoding apparatus in the communications field, particularly a kind ofly is used for the Bose-Chaudhuri-Hocquenghem Code decoding circuit that wireless communication system has error correcting capability.

Background technology

The BCH codec is a kind of forward error correction codec, obtains the forward error correction ability by the mode that increases redundant digit.Present BCH codec all is special-purpose codec, and promptly at the codec of a certain Demand Design, algorithm is single can only to carry out water operation; Can't dispose and state of a control, can only be used for specific situation and do not possess versatility and flexibility.

Summary of the invention

In view of the deficiency that prior art exists, the utility model provides a kind of that be configured and control, computing BCH coding and decoding device rapidly.

The utility model for achieving the above object, the technical scheme of being taked is: a kind of Bose-Chaudhuri-Hocquenghem Code decoding circuit, it is characterized in that: comprise the FPGA device, the internal circuit of described FPGA device is connected to: controller by control line respectively with the coding input store, the Bose-Chaudhuri-Hocquenghem Code device, the coding output storage, the decoding input store, the BCH decoder, the decoding output storage connects, described coding input store, the coding output storage is connected described decoder input store respectively with the BCH decoder by data wire, the decoding output storage is connected with the BCH decoder by data wire respectively.

Characteristics of the present utility model are: 1, alternative sign indicating number type is abundant, can be configured to the BCH code of any n＜1024, and control mode is simple, flexible and convenient operation; 2, adopt custom-designed code decode algorithm, computing is quick; 3, adopt programmable logic device to realize, simple in structure, the reliability height.

Description of drawings

Fig. 1 connects block diagram for the utility model circuit.

Fig. 2 is the control port schematic diagram.

Fig. 3 connects block diagram for controller circuitry.

Fig. 4 connects block diagram for encoder circuit.

Fig. 5 connects block diagram for decoder circuit.

Embodiment

As shown in Figure 1, a kind of Bose-Chaudhuri-Hocquenghem Code decoding circuit, comprise the FPGA(Field Programmable Gate Array) device, the internal circuit of FPGA device is connected to: controller is connected with coding input store, Bose-Chaudhuri-Hocquenghem Code device, coding output storage, decoding input store, BCH decoder, decoding output storage respectively by control line, coding input store, coding output storage are connected with the BCH decoder by data wire respectively, and decoder input store, decoding output storage are connected with the BCH decoder by data wire respectively.The control mouth is connected with controller by control bus, data-in port is connected with coding input store, decoding input store respectively by data/address bus, and data-out port is connected with coding output storage, decoding output storage respectively by data/address bus.Coder/decoder can be finished the BCH coding/decoding of 8 kinds of sign indicating number types.Controller can and be controlled the parameter and the state of 1～8 kind of sign indicating number type according to different demand settings.

As shown in Figure 2, index signal line, the busy not busy index signal line of F are finished in A address wire, B starting impulse control line, C encoding and decoding control line, D output pulse control line, E computing among the figure, coding/decoding control mode shown in the control port is: control bus finishes the index signal line by address wire, starting impulse control line, encoding and decoding control line, output pulse control line, computing and the not busy index signal line that hurries is formed, and the signal on the address wire is responsible for selecting the BCH code type; Signal controlling coding or decoding function on the encoding and decoding control line; The beginning of starting impulse control line control encoding and decoding.Starting impulse during work on the starting impulse control line resets the FPGA internal signal, data after the pulse on the data wire will serial be input to the coding/decoding memory, when FPGA detect the input finish after, start the BCH coder/decoder, finish coding/decoding, store data serial into the coding/decoding output storage.After coding/decoding is finished, the index signal line is finished in computing be changed to high level.When needing data output, input/output pulse signal on output pulse control line, then the data in the coding/decoding output storage will serial order output in the output port data line.Busy not busy index signal line is used for the busy-idle condition of tag system.

As shown in Figure 3, controller is made up of configuration circuit, sequential control circuit, memory read/write drive circuit and coding/decoding drive circuit.

Shown in Fig. 4,5, BCH encoding and decoding implementation is: the BCH code type is preestablished by configuration file, and controller can be changed between 1～8 kind of default BCH code type encoding and decoding type by control bus.The Bose-Chaudhuri-Hocquenghem Code device is made up of, generator polynomial, backward shift bit register and gate circuit; The BCH decoder is made up of syndrome arithmetic unit, key equation arithmetic unit, search circuit, delayer, adder and gate circuit.

Claims

1. Bose-Chaudhuri-Hocquenghem Code decoding circuit, it is characterized in that: comprise the FPGA device, the internal circuit of described FPGA device is connected to: controller is connected with coding input store, Bose-Chaudhuri-Hocquenghem Code device, coding output storage, decoding input store, BCH decoder, decoding output storage respectively by control line, described coding input store, coding output storage are connected with the BCH decoder by data wire respectively, and described decoder input store, decoding output storage are connected with the BCH decoder by data wire respectively.