CN101447514B - Metal oxide semiconductor field effect transistor - Google Patents
Metal oxide semiconductor field effect transistor Download PDFInfo
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- CN101447514B CN101447514B CN2008102049695A CN200810204969A CN101447514B CN 101447514 B CN101447514 B CN 101447514B CN 2008102049695 A CN2008102049695 A CN 2008102049695A CN 200810204969 A CN200810204969 A CN 200810204969A CN 101447514 B CN101447514 B CN 101447514B
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Abstract
The invention discloses a metal oxide semiconductor field effect transistor which comprises a semiconductor substrate, a grid insulation dielectric layer which is arranged on the surface of the semiconductor substrate, a grid which is piled on the grid insulation dielectric layer and a source electrode area and a drain electrode area which are arranged in the surface area of the semiconductor substrate at two sides of the grid and are separated by a channel region. A first part of the grid insulation dielectric layer is close to the drain electrode area, a second part thereof is close to the source electrode area, and the thickness of the first part is thicker than the thickness of the second part. The thickness of the second part near the source electrode area of the metal oxide semiconductor field effect transistor is thinner, thereby improving the control capacity of the grid on the channel, increasing saturation current, improving the drive capacity of the apparatus and also reducing the area of the apparatus. The thickness of the first part near the drain electrode area is thicker, thereby controlling leakage current caused by GIDL effect.
Description
Technical field
The present invention relates to a kind of semiconductor device, specifically, relate to a kind of mos field effect transistor.
Background technology
The applied environment of mos field effect transistor (MOSFET) is complicated day by day; Need under different voltage conditions, carry out work; Such as in memory peripheral circuit; Usually need a MOSFET under " shutoff " state, to drain and bear a higher voltage (like 12V), and grid all only bears normal operating voltage (like 3.3V) with drain electrode when " unlatching " state.When applying a high voltage in drain electrode, because gate-induced drain leaks (gate-induced-drain leakage GIDL) effect, drain electrode can produce very big leakage current, causes device power consumption to rise, and influences the working life of device.
The size of the leakage current that the GIDL effect causes has direct relation with near the thickness of the gate insulator dielectric layer of drain electrode, and the thickness of gate insulator dielectric layer is big more near the drain electrode, and the leakage current that the GIDL effect causes is more little.Therefore, in order to solve leakage problem, existing method is all used thicker gate insulator dielectric layer to whole M OSFET.But this method has shortcoming clearly, and after promptly the gate insulator medium thickness of MOSFET became greatly, grid was to the control ability variation of raceway groove, and threshold voltage raises, and causes the saturation current of device to reduce.In order to reach the driving force that needs, device needs very big area.
Summary of the invention
The technical problem that the present invention will solve is: a kind of mos field effect transistor is provided, under different voltage conditions, improves grid to the raceway groove control ability, overcome the leakage problem that exists in the mos field effect transistor simultaneously.
For solving the problems of the technologies described above, the present invention provides a kind of mos field effect transistor, comprising:
Semiconductor substrate;
The gate insulator dielectric layer is positioned on the said semiconductor substrate surface;
Grid is superimposed upon said gate insulator dielectric layer upper surface;
Source region and drain region are arranged in the semiconductor substrate surface zone of said grid both sides, and said source region and drain region are separated by channel region;
The first of said gate insulator dielectric layer is near said drain region, and second portion is near said source region, and the thickness of first is greater than the thickness of second portion.
Further, said mos field effect transistor also comprises grid curb wall, and said grid curb wall is positioned at said grid both sides.
Further, between said source region and the said channel region, be provided with lightly mixed drain area (LDD) between said drain region and the said channel region.
Further, the lightly mixed drain area that forms between the lightly mixed drain area that forms between said source region and the said channel region and said drain region and the said channel region has different doping conditions.
Further, the thickness range of the first of said gate insulator dielectric layer is 3～200 nanometers.
Further, the thickness range of the second portion of said gate insulator dielectric layer is 1～50 nanometer.
Further, said grid is N type or the P type polysilicon bar utmost point or metal gates.
Further, said gate insulator dielectric layer is the oxide of silicon, the nitrogen oxide of silicon, the dielectric layer of HfO2 or other high-ks.
Compare with traditional mos field effect transistor; The thickness of its gate insulator dielectric layer first of mos field effect transistor that the present invention proposes is greater than the thickness of second portion; The benefit of this structure is: one: near the second portion thinner thickness of source region, improved the control ability of grid to raceway groove, increased saturation current; Improve the driving force of device, also reduce device area.Two: the first's thickness near the drain region is thicker, suppresses the leakage current that the GIDL effect causes.
Description of drawings
Fig. 1 is the structural representation of mos field effect transistor in the embodiment of the invention;
Fig. 2 is the sketch map that mos field effect transistor is opened in the embodiment of the invention;
Fig. 3 is the sketch map that mos field effect transistor turn-offs in the embodiment of the invention.
Embodiment
For clearer understanding technology contents of the present invention, the special specific embodiment of lifting also cooperates appended graphic explanation following.
See also Fig. 1; Fig. 1 is the MOSFET structure sketch map in the embodiment of the invention, and this mos field effect transistor comprises Semiconductor substrate 1, and said Semiconductor substrate 1 surface is provided with gate insulator dielectric layer 2; Said gate insulator dielectric layer 2 is the oxide of silicon, the nitrogen oxide of silicon; The dielectric layer of HfO2 or other high-ks, in the present embodiment, said gate insulator dielectric layer 2 is the oxide silicon dioxide of silicon.
Said gate insulator dielectric layer 2 is made up of two parts, and first 20 is near said drain region 6, and second portion 21 is near said source region 5, and the thickness of first 20 is greater than the thickness of second portion 21.First 20 and the said gate insulator dielectric layer 2 of second portion 21 one-body molded common formations; Wherein, First's 20 selectable thickness ranges are 1～50 nanometer, and second portion 21 selectable thickness ranges are 3～200 nanometers, and length range is 0.02～1 micron.
Because said first 20 is different with the thickness of second portion 21; Near the thinner thickness of the second portion 20 of source region 5, improve the control ability of 3 pairs of channel regions of said grid, threshold voltage reduces; Increase the saturation current of device, improved driving force device.Under the condition of the identical driving force of maintenance, the required chip area of device also is able to reduce.
Referring to shown in Figure 2, Fig. 2 is the sketch map that mos field effect transistor is opened in the embodiment of the invention.Mos field effect transistor in the present embodiment is applied in connects word line in the flush memory device; When memory cell being carried out " reading " operation; In the source region 5, to apply voltage respectively be 0V, 3.3V, 3.3V for drain region 6, grid 3; Can between raceway groove, form electric current, accomplish " reading " operation.Simultaneously,, improved the driving force of device, also improved device operation speed, improved the performance of device greatly owing to the thickness attenuation.
Because the leakage current that causes of the GIDL effect only thickness with near the gate insulator dielectric layer 2 in drain region is relevant; Thickness that promptly should the zone is big more; The leakage current that the GIDL effect causes is just more little, therefore, and in the present embodiment; First 20 near said drain region 6 is thicker, has well overcome the leakage current that the GIDL effect causes.
Referring to shown in Figure 3, Fig. 3 is the sketch map that mos field effect transistor turn-offs in the embodiment of the invention.When memory cell being carried out " wiping " operation, the drain electrode of the mos field effect transistor in the present embodiment need connect word line.The grid of the mos field effect transistor in the present embodiment and voltage that source electrode applies are 0V in this case, and transistor is " shutoff " state.But because " wiping " action need high voltage, drain electrode need be born the high pressure of 12V.Because near the thickness of the gate insulator dielectric layer 21 the drain electrode is thicker, can suppress the leakage current that the GIDL effect causes, thereby reduce the power consumption of circuit, and it is breakdown to prevent to drain.
The thickness various structure of this gate insulator dielectric layer first 20 and second portion 21 has been improved the performance of device greatly, can under the different voltages with different condition, work, and has also avoided increasing extra circuit or device, has simplified the design of circuit.
Between said source region 5 and the said channel region, be provided with lightly mixed drain area 7 (LDD) between said drain region 6 and the said raceway groove, the lightly mixed drain area 8 that forms between the lightly mixed drain area 7 that forms between said source region 5 and the said channel region and said drain region 6 and the said channel region has different doping conditions.In actual production process, can impose according to the use needs of device different doping contents, different ionic type, implant energy or arbitrarily wherein various combination form different lightly mixed drain areas.In the present embodiment, lightly mixed drain area 7 uses heavier doping content to reduce source region 5 and the series resistance that lightly mixed drain area 7 forms, and improves transistorized saturation current; Lightly mixed drain area 8 uses lighter doping content to improve the puncture voltage of drain region 6.
This LDD structure can reduce the drain terminal maximum field of device effectively, has effectively suppressed hot carrier's effect, thereby can slow down the degeneration of device, prolongs the useful life of device.
More than show and described basic principle of the present invention, principal character and advantage of the present invention.The technical staff of the industry should understand; The present invention is not restricted to the described embodiments; That describes in the foregoing description and the specification just explains principle of the present invention; The present invention also has various changes and modifications under the prerequisite that does not break away from spirit and scope of the invention, and these variations and improvement all fall in the scope of the invention that requires protection.The present invention requires protection range to be defined by appending claims and equivalent thereof.
Claims (8)
1. mos field effect transistor comprises:
Semiconductor substrate;
The gate insulator dielectric layer is positioned on the said semiconductor substrate surface;
Grid is superimposed upon said gate insulator dielectric layer upper surface;
Source region and drain region are arranged in the semiconductor substrate surface zone of said grid both sides, and said source region and drain region are separated by channel region;
It is characterized in that: the first of said gate insulator dielectric layer is near said drain region, and second portion is near said source region, and the thickness of first is greater than the thickness of second portion.
2. mos field effect transistor as claimed in claim 1 is characterized in that: said mos field effect transistor also comprises grid curb wall, and said grid curb wall is positioned at said grid both sides.
3. according to claim 1 or claim 2 mos field effect transistor is characterized in that: between said source region and the said channel region, be provided with lightly mixed drain area between said drain region and the said channel region.
4. mos field effect transistor as claimed in claim 3 is characterized in that: the lightly mixed drain area that forms between the lightly mixed drain area that forms between said source region and the said channel region and said drain region and the said channel region has different doping conditions.
5. mos field effect transistor as claimed in claim 1 is characterized in that: the thickness range of the first of said gate insulator dielectric layer is 3～200 nanometers.
6. mos field effect transistor as claimed in claim 1 is characterized in that: the thickness range of the second portion of said gate insulator dielectric layer is 1～50 nanometer.
7. mos field effect transistor as claimed in claim 1 is characterized in that: said grid is N type or the P type polysilicon bar utmost point or metal gates.
8. mos field effect transistor as claimed in claim 1 is characterized in that: said gate insulator dielectric layer is the oxide of silicon, the nitrogen oxide of silicon, the dielectric layer of HfO2 or other high-ks.
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| CN2008102049695A CN101447514B (en) | 2008-12-30 | 2008-12-30 | Metal oxide semiconductor field effect transistor |
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| CN2008102049695A CN101447514B (en) | 2008-12-30 | 2008-12-30 | Metal oxide semiconductor field effect transistor |
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| CN101447514B true CN101447514B (en) | 2012-06-20 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102610525A (en) * | 2012-03-22 | 2012-07-25 | 上海华力微电子有限公司 | Method for reducing leakage of gate-induced drain electrode of semiconductor device |
| CN111627992B (en) * | 2020-06-05 | 2023-04-04 | 福建省晋华集成电路有限公司 | Grid structure and manufacturing method thereof |
| CN111627993B (en) * | 2020-06-05 | 2023-01-06 | 福建省晋华集成电路有限公司 | Grid structure and manufacturing method thereof |
| CN116153972B (en) * | 2023-04-18 | 2023-07-11 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002164537A (en) * | 2000-11-29 | 2002-06-07 | Seiko Epson Corp | Semiconductor device and its manufacturing method |
| US6506642B1 (en) * | 2001-12-19 | 2003-01-14 | Advanced Micro Devices, Inc. | Removable spacer technique |
| CN1645593A (en) * | 2004-01-22 | 2005-07-27 | 国际商业机器公司 | Selective nitridation of gate oxides |
| US7011980B1 (en) * | 2005-05-09 | 2006-03-14 | International Business Machines Corporation | Method and structures for measuring gate tunneling leakage parameters of field effect transistors |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002164537A (en) * | 2000-11-29 | 2002-06-07 | Seiko Epson Corp | Semiconductor device and its manufacturing method |
| US6506642B1 (en) * | 2001-12-19 | 2003-01-14 | Advanced Micro Devices, Inc. | Removable spacer technique |
| CN1645593A (en) * | 2004-01-22 | 2005-07-27 | 国际商业机器公司 | Selective nitridation of gate oxides |
| US7011980B1 (en) * | 2005-05-09 | 2006-03-14 | International Business Machines Corporation | Method and structures for measuring gate tunneling leakage parameters of field effect transistors |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |