CN116153972B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN116153972B
CN116153972B CN202310409290.4A CN202310409290A CN116153972B CN 116153972 B CN116153972 B CN 116153972B CN 202310409290 A CN202310409290 A CN 202310409290A CN 116153972 B CN116153972 B CN 116153972B
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drain
doped region
region
doping region
semiconductor substrate
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CN116153972A (en
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大田裕之
中嶋伸惠
石田浩
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
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    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor device includes: a semiconductor substrate; the source light doping region and the drain light doping region are arranged in the semiconductor substrate, and the drain light doping region and the source light doping region are arranged at intervals; the gate oxide layer is arranged on the semiconductor substrate and comprises a first subsection and a second subsection, the thickness of the second subsection is larger than that of the first subsection, the first subsection is arranged above the source light doping region and part of the drain light doping region, and the second subsection is arranged above the part of the drain light doping region and close to the source light doping region; the drain electrode heavy doping region is arranged in the drain electrode light doping region at one side of the second partition part far away from the source electrode light doping region, and the interface depth of the drain electrode heavy doping region is smaller than that of the drain electrode light doping region. The semiconductor device and the manufacturing method thereof can improve the performance of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and a manufacturing method thereof.
Background
Metal-Oxide-semiconductor field effect transistor (MOSFET), abbreviated as Metal-Oxide-Semiconductor Field-Effect Transistor. In a Lateral Double-diffused MOSFET, LDMOSFET field effect transistor (LDMOSFET), the thickness of the oxide layer near the drain is increased without affecting the performance of the field oxide layer isolated from the semiconductor device and improving the on-resistance or breakdown voltage of the LDMOSFET.
In an LDMOSFET, a lightly doped region (Lightly Doped Drain, LDD) on the Source side is not provided, wherein the Source-Drain (SD) impurity profile, LDD, channel (Channel), etc. are different from Medium Voltage metal oxide semiconductor field effect transistors (Medium Voltage MOSFET, MVMOSFET). Therefore, if the LDMOSFET structure is applied to the MVMOSFET, the source resistance of the MVMOSFET increases, resulting in a decrease in on-current (Ion). In addition, in the MVMOSFET, when the substrate bias is zero, the Gate-Induced-Drain-Leakage current (GIDL) is independent of the amount of overlap of the polysilicon and LDD of the Gate.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can improve the performance of the semiconductor device without increasing the manufacturing cost.
To achieve the above and other related objects, the present invention provides a semiconductor device comprising:
a semiconductor substrate;
the source light doping area is arranged in the semiconductor substrate;
the drain light doping region is arranged in the semiconductor substrate, and the drain light doping region and the source light doping region are arranged at intervals;
the gate oxide layer is arranged on the semiconductor substrate and comprises a first subsection and a second subsection, the thickness of the second subsection is larger than that of the first subsection, the first subsection is arranged above the source light doping region and part of the drain light doping region, the second subsection is arranged above part of the drain light doping region, and the second subsection is arranged close to the source light doping region; and
the drain electrode heavy doping region is arranged in the drain electrode light doping region at one side of the second partition part far away from the source electrode light doping region, and the interface depth of the drain electrode heavy doping region is smaller than that of the drain electrode light doping region.
In an embodiment of the present invention, the semiconductor device further includes a gate electrode, the gate electrode is disposed on the gate oxide layer, and a portion of the gate electrode is disposed on the second portion.
In an embodiment of the present invention, an offset portion is disposed between the gate electrode and the second portion near the end of the drain heavily doped region.
In an embodiment of the present invention, an end of the gate adjacent to the drain heavily doped region is aligned with an end of the second partition adjacent to the drain heavily doped region.
In an embodiment of the present invention, the semiconductor device further includes a gate, the gate is disposed on the gate oxide layer, and a portion of the gate is disposed on the second portion and extends to a transition region between the second portion and the first portion near the side of the drain heavily doped region.
In an embodiment of the present invention, the impurity implantation types of the source lightly doped region and the drain lightly doped region are the same, and the impurity implantation doses are equal.
The invention also provides a method for manufacturing the semiconductor device, which comprises the following steps:
providing a semiconductor substrate;
forming a source light doping region in the semiconductor substrate;
forming a drain light doping region in the semiconductor substrate, wherein the drain light doping region and the source light doping region are arranged at intervals;
forming a gate oxide layer on the semiconductor substrate, wherein the gate oxide layer comprises a first subsection and a second subsection, the thickness of the second subsection is larger than that of the first subsection, the first subsection is arranged above the source light doping region and part of the drain light doping region, the second subsection is arranged above part of the drain light doping region, and the second subsection is arranged close to the source light doping region; and
and forming a drain heavy doping region in the drain light doping region, wherein the drain heavy doping region is arranged in the drain light doping region at one side of the second partition part far away from the source light doping region, and the implantation energy of the drain heavy doping region is smaller than that of the drain light doping region.
In one embodiment of the present invention, the impurities in the source lightly doped region and the drain lightly doped region are implantedThe dosage is 1×10 13 atoms/cm 2 。
In an embodiment of the present invention, the step of forming the source lightly doped region and the drain lightly doped region is performed before the step of forming the gate oxide layer.
In an embodiment of the present invention, the step of forming the gate oxide layer includes:
forming a hard mask layer on the semiconductor substrate with the drain lightly doped region;
forming a photoresist layer on the hard mask layer, wherein the photoresist layer exposes part of the hard mask layer on the drain light doped region;
etching the hard mask layer to the semiconductor substrate by taking the photoresist layer as a mask to form an opening;
removing the photoresist layer;
forming the second sub-portion on the semiconductor substrate within the opening;
removing the hard mask layer; and
the first branch is formed on the semiconductor substrate except the second branch.
In summary, the present invention provides a semiconductor device and a method for manufacturing the same, which can improve the breakdown voltage of the semiconductor device, reduce the gate-induced drain leakage current of the semiconductor device, and improve the reliability of the semiconductor device. And simultaneously, the resistance of the source region is reduced, so that the reduction of the on current can be restrained. The potential barrier of the semiconductor device can be enlarged, and the number of electrons passing through the potential barrier can be reduced, thereby further suppressing the gate induced drain leakage current. The volume of the semiconductor device can be reduced without degrading the performance of the semiconductor device. Meanwhile, in the manufacturing process of the semiconductor device, a new manufacturing process or mask is not required to be added, the difficulty of the production process and the production cost are reduced, and the performance of the semiconductor device can be improved without increasing the manufacturing cost.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a P-well in a semiconductor substrate in accordance with one embodiment of the present invention.
FIG. 3 is a schematic diagram illustrating formation of lightly doped regions according to an embodiment of the invention.
FIG. 4 is a schematic diagram illustrating an opening formed in a hard mask layer according to an embodiment of the present invention.
FIG. 5 is a schematic diagram of a second sub-portion of the gate oxide layer formed according to an embodiment of the invention.
FIG. 6 is a schematic diagram illustrating a first sub-portion of forming a gate oxide layer according to an embodiment of the invention.
Fig. 7 is a schematic diagram illustrating a process of forming a gate according to an embodiment of the invention.
FIG. 8 is a schematic diagram of a gate formed in an embodiment of the invention.
Fig. 9 is a schematic diagram of forming a sidewall structure according to an embodiment of the invention.
FIG. 10 is a schematic diagram illustrating the formation of metal silicide in accordance with one embodiment of the present invention.
FIG. 11 is a schematic view of forming a contact portion according to an embodiment of the invention.
Fig. 12 is a graph showing a comparison of potential barriers of a semiconductor device according to various embodiments of the present invention.
Fig. 13 is a graph showing comparison of output characteristics of semiconductor devices according to various embodiments of the present invention.
Fig. 14 is a graph showing a comparison of potential barriers of a semiconductor device according to various embodiments of the present invention.
Fig. 15 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.
Fig. 16 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.
Description of the reference numerals:
1. a semiconductor device; 2. a semiconductor substrate; 3. a source lightly doped region; 4. a drain lightly doped region; 5. a source heavily doped region; 6. a drain heavily doped region; 7. a gate oxide layer; 8. a first subsection; 9. a second subsection.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
Referring to fig. 1, in an embodiment of the present invention, a semiconductor device such as a Medium Voltage metal oxide semiconductor field effect transistor (Medium Voltage MOSFET, MVMOSFET) is provided. In the present embodiment, as shown in fig. 1, the direction of the thickness of the semiconductor substrate 2 is defined as a thickness direction X, and the direction orthogonal to the thickness direction X is defined as a width direction Y. The semiconductor device shown in fig. 1 is continuously formed in a predetermined range in a depth direction orthogonal to the thickness direction X and the width direction Y, respectively, and the description of other devices is omitted here. In the following description, specific examples are given as to the thickness and width, but the present invention is not limited to the specific examples, and for example, errors in the implantation amount in the manufacturing process, errors in the thickness or width of the completed product, and the like are within allowable ranges.
Referring to fig. 1, in an embodiment of the invention, a semiconductor device 1 is, for example, a MVMOSFET. The semiconductor device 1 includes a semiconductor substrate 2, a P-well, a shallow trench isolation STI (not shown), a source lightly doped region 3, a drain lightly doped region 4, a source heavily doped region 5, a drain heavily doped region 6, a gate oxide layer 7, and a gate G. In the semiconductor substrate 2, a P-well (Pwell) is formed by implanting P-type impurities, the ion doping types of the source light doped region 3 and the drain light doped region 4 are, for example, N-type light doped regions (Negative Lightly Doped Drain, NLDD) are formed, the ion doping types of the source heavy doped region 5 and the drain heavy doped region 6 are, for example, N-type, and the N-type heavy doped regions are formed as the source and the drain of the semiconductor device, which is denoted as Negative Source Drain (NSD). The gate oxide layer 7 includes a first portion 8 and a second portion 9, and the thickness of the first portion 8 is smaller than the thickness of the second portion 9.
Referring to fig. 1, in an embodiment of the present invention, a semiconductor device 1 is, for example, a MVMOSFET, and the MVMOSFET is illustrated as an MVNMOS. In other embodiments, other configurations of MOS structures may be selected. In this embodiment, the MVNMOS is, for example, a MOSFET having an operating voltage of 2.5v to 8 v.
Referring to fig. 1, in an embodiment of the present invention, a semiconductor substrate 2 is, for example, a silicon substrate, and P-wells and shallow trench isolation STI (not shown) are formed in the semiconductor substrate 2. The P-well is a region having P-type polarity formed by implanting P-type impurities such as boron (B) into the semiconductor substrate 2, and the shallow trench isolation STI is used to block the structure between the regions in the semiconductor substrate 2. Shallow trench isolation STI is formed by forming a trench at a predetermined position and filling silicon oxide into the trench. The shallow trench isolation STI is formed by using an insulating material, and thus electrically isolates regions formed on the surface of the semiconductor substrate 2.
Referring to fig. 1, in an embodiment of the present invention, a source lightly doped region 3 is formed in a low concentration region of a semiconductor substrate 2 by implanting an N-type impurity such As arsenic (As) or phosphorus (P) into the semiconductor substrate 2. Since a low concentration region is formed in the semiconductor substrate 2, a depletion layer in the P-well expands, thereby reducing the surface electric field strength. The source lightly doped region 3 is located below the first portion 8 in the thickness direction X, that is, below the first portion 8 of the source region, and the source lightly doped region 3 is disposed closely to the lower surface of the first portion 8.
Referring to fig. 1, in an embodiment of the present invention, a drain lightly doped region 4 is formed in a low concentration region of a semiconductor substrate 2 by implanting an N-type impurity such as arsenic or phosphorus into the semiconductor substrate 2. Since a low concentration region is formed in the semiconductor substrate 2, a depletion layer in the P-well under the gate G expands, thereby reducing the surface electric field strength. In addition, the drain lightly doped region 4 is located below the second portion 9 and the first portion 8 away from the source lightly doped region 3 in the thickness direction X, and the drain lightly doped region 4 is disposed in close contact with the lower surfaces of the second portion 9 and the first portion 8.
Referring to fig. 1, in an embodiment of the present invention, a source heavily doped region 5 is formed by implanting impurities into a region where a source of a transistor is disposed. The source heavily doped region 5 is, for example, polysilicon, and is used to form a source region of the transistor. In addition, the interface depth of the source heavily doped region 5 is smaller than that of the source lightly doped region 3.
Referring to fig. 1, in one embodiment of the present invention, the drain heavily doped region 6 is formed by implanting impurities into the region where the transistor drain is located. The drain heavily doped region 6 is, for example, polysilicon, and is used to form a region of the drain of the transistor. In addition, the interface depth of the drain heavily doped region 6 is smaller than the interface depth of the drain lightly doped region 4. In this embodiment, the source heavily doped region 5 and the drain heavily doped region 6 are formed by implanting ions such as N-type impurities of arsenic or phosphorus.
Referring to fig. 1, in an embodiment of the present invention, a gate oxide layer 7 is disposed on a surface of a semiconductor substrate 2, and the gate oxide layer 7 includes a first portion 8 and a second portion 9. The first subsection 8 is located on the semiconductor substrate 2 of the source region and a part of the drain region, and the thickness of the first subsection 8 is 14nm, for example. The second sub-portion 9 is located on the semiconductor substrate 2 near the drain, and the thickness of the second sub-portion 9 is 120nm, for example, and the width of the second sub-portion 9 is 200nm to 300nm, for example. By increasing the thickness of the gate oxide layer 7 on the region near the drain, the breakdown voltage of the semiconductor device 1 can be increased, the gate-induced drain leakage current of the semiconductor device can be reduced, and the reliability of the semiconductor device can be improved.
Referring to fig. 1, in an embodiment of the present invention, the source lightly doped region 3 and the drain lightly doped region 4 are selectively implanted with N-type impurities having the same impurity type and implantation dose, so as to effectively increase the breakdown voltage of the semiconductor device 1 and reduce the gate-induced drain leakage current of the semiconductor device.
Referring to fig. 1, in an embodiment of the present invention, the gate G is made of polysilicon (Poly), and is formed on the gate oxide layer 7, and the thickness of the gate G is 200nm, for example. In other embodiments, the gate G is, for example, a high dielectric constant insulating film/Metal Gate (MGHK) structure. The gate G and the source lightly doped region 3 and the gate G and the drain lightly doped region 4 have an Overlap region over lap in the width direction Y, and the dimensions of the Overlap region over lap are equal in length in the width direction Y, and the length of the Overlap region over lap is 200nm, for example.
Referring to fig. 2 to 11, in an embodiment of the present invention, a manufacturing process of a semiconductor device is further provided, and an example of manufacturing an MVMOSFET is specifically described.
Referring to fig. 2, in step S10, shallow trench isolation STI is formed in the semiconductor substrate 2, and the shallow trench isolation STI is used to isolate each region. Specifically, a trench is formed at a predetermined position on the semiconductor substrate 2, and an insulating material such as silicon oxide is deposited in the trench for electrically isolating each region of the semiconductor substrate 2. Then, P-type impurities such as boron are implanted into the semiconductor substrate 2, and a P-well is formed in the semiconductor substrate 2. After the shallow trench isolation STI is formed, a sacrificial oxide layer is present on the surface of the semiconductor substrate 2, which can prevent damage to the semiconductor substrate 2 when the P-well and the lightly doped region are implanted.
Referring to fig. 3, in step S12, a source lightly doped region 3 and a drain lightly doped region 4 are formed in the P-well. Specifically, a first photoresist layer PR1 is formed on the semiconductor substrate 2, and the first photoresist layer PR1 exposes regions where the source light doped region 3 and the drain light doped region 4 are formed, and in various embodiments, the regions of the source light doped region 3 and the drain light doped region 4 are selected according to the design of the semiconductor device. And using the first photoresist layer PR1 as a mask, and injecting impurities into the P well to form a source light doped region 3 and a drain light doped region 4. Wherein the impurity is N-type impurity such as phosphorus, and the implantation dosage of the impurity is 1×10 13 atoms/cm 2 . By implanting ions of the same type and in the same amount in the source lightly doped region 3 and the drain lightly doped region 4, the number of masks is not increased in the manufacturing process, the difficulty and cost of the manufacturing process are reduced, and the resistance of the source region is reduced, so that the decrease in on-current (Ion) can be suppressed.
Referring to fig. 1, 3 and 4, in step S14, after forming the source lightly doped region 3 and the drain lightly doped region 4, the first photoresist layer PR1 and the sacrificial oxide layer on the semiconductor substrate 2 are removed. A hard mask layer SiN is formed on the semiconductor substrate 2, and is formed by a method such as chemical vapor deposition (Chemical Vapor Deposition, CVD) and the like, and has a thickness of 70nm to 200nm, for example. After the formation of the hard mask layer SiN, a second photoresist layer PR2 is formed on the hard mask layer SiN, and the second photoresist layer PR2 covers the region other than the region where the second portion 9 is formed. The hard mask layer SiN is etched to the semiconductor substrate 2 with the second photoresist layer PR2 as a mask to form an opening for forming the second division 9. The method of etching the hard mask layer SiN is, for example, dry etching, and the dry etching is, for example, etching by using high Radio Frequency (RF) discharge.
Referring to fig. 4 to 5, in step S16, after forming the opening, the second photoresist layer PR2 is removed, for example, by chemical cleaning. The second portion 9 is formed in the opening, wherein the second portion 9 is formed by, for example, a thermal oxidation method, for example, any one of a dry oxidation method, a wet oxidation method, and a vapor oxidation method among the thermal oxidation methods. In this embodiment, the thickness of the second part 9 is, for example, 120nm.
Referring to fig. 5 to 6, in step S18, after forming the second sub-portion 9, the hard mask layer SiN on the semiconductor substrate 2 is removed. Wherein the SiN of the hard mask layer is removed by wet etching, and the wet etching liquid is phosphoric acid (H) 3 PO 4 ) Is a solution. After removal of the hard mask layer SiN, a first portion 8 is formed on the semiconductor substrate 2 outside the second portion 9 by a thermal oxidation method, wherein the thickness of the first portion 8 is, for example, 14nm. Gate oxide layers of different thicknesses are formed on the semiconductor substrate 2 by a two-time thermal oxidation process, wherein a thicker second division 9 is formed on a partial region near the drain and a thinner first division 8 is formed on a source-side region and on the remaining region. In the present invention, an LDD region has been formed in a substrate at the time of forming a gate oxide layer, that is, a step of forming an LDD region is a step preceding a step of forming a gate oxide layer. Therefore, the penetration phenomenon caused by the ion implantation of polysilicon can be avoided when forming the gate electrode, and the LDD region can be formed to be deep, that is, the gate induced drain leakage current of the semiconductor device can be suppressed by the improvement of the manufacturing process.
Referring to fig. 7 to 8, in step S20, after forming the first portion 8, a polysilicon layer (Poly) is formed on the semiconductor substrate 2, and the polysilicon layer is formed by chemical vapor deposition, for example, and the thickness of the polysilicon layer is 200nm, for example. A patterned photoresist layer is formed on the polysilicon layer, the patterned photoresist layer covering the polysilicon layer for forming the gate electrode G. The remaining regions of the polysilicon layer are then removed by etching, in this embodiment, by removing the polysilicon layer, for example, by dry etching techniques, to form the gate electrode G, and then removing the patterned photoresist layer. Wherein the gate G on the drain region covers part of the second subsection 9 and covers the channel of the semiconductor device.
Referring to fig. 9, in step S24, after forming the gate electrode G, a dielectric film (not shown) is formed on the semiconductor substrate 2 and the gate electrode G. After removing the dielectric film layer on the semiconductor substrate 2 and the gate electrode G by etching, for example, by reactive ion etching (Reaction Ion Etching, RIE), the dielectric film layers remaining on both sides of the gate electrode G form the sidewall structure SW. Wherein the sidewall structure SW of the source side region is formed on the first subsection 8 and the sidewall structure SW of the source side region is formed on the second subsection 9.
Referring to fig. 9, in step S24, N-type impurities such as phosphorus are implanted into the source lightly doped region 3 and the drain lightly doped region 4 to form an N-type source heavily doped region 5 and a drain heavily doped region 6. Wherein, in the drain region, the gate G is disposed on a part of the second subsection 9 of the gate oxide layer, and a predetermined distance is provided from the gate G to the edge of the second subsection 9, so that a predetermined distance exists between the drain heavily doped region 6 and the gate G, and the predetermined distance is defined as an Offset OS (Offset). In forming the source and drain heavily doped regions 5 and 6, the impurity implantation energy is smaller than that in forming the source and drain lightly doped regions 3 and 4, and thus the depth of the source and drain heavily doped regions 5 and 6 in the semiconductor substrate 2 is smaller than that of the source and drain lightly doped regions 3 and 4, i.e., the interface depth of the heavily doped regions is smaller than that of the lightly doped regions. And because the thickness of the second sub-portion 9 is large, N-type impurities are not implanted into the drain lightly doped region 4 under the second sub-portion 9 when the drain heavily doped region 6 is formed. That is, by providing the offset portion OS, diffusion of impurities from the drain heavily doped region 6 to the drain lightly doped region 4 to the region below the gate G can be suppressed, and thus, occurrence of an excessively high impurity concentration in the drain lightly doped region 4 below the gate G can be prevented, and GIDL of the semiconductor device can be suppressed.
Referring to fig. 9, in an embodiment of the present invention, when forming a heavily doped region, the depth of the heavily doped region is smaller than that of the lightly doped region, which can be controlled according to the implantation energy. In one embodiment of the present invention, when the semiconductor device is a P-type device, the LDD region is formed by implanting P-type impurities, such as 20KeV, and ions, such as boron, and the heavily doped region is formed by implanting P-type impurities, such as boron, with an implantation energy, such as 6 KeV. In one embodiment of the present invention, when the semiconductor device is an N-type device, the LDD region is formed by implanting N-type impurities, such as phosphorus, at an implantation energy of, for example, 70KeV, and the heavily doped region is formed by implanting N-type impurities, such as phosphorus, at an implantation energy of, for example, 30 KeV. That is, in the present invention, the GIDL can be more effectively suppressed by selecting different implantation energies for the lightly doped region and the heavily doped region depending on the type of semiconductor device to be formed.
Referring to fig. 10, in step S26, after forming the source heavily doped region 5 and the drain heavily doped region 6, a metal layer (not shown), such as a metal nickel layer, is formed on the semiconductor substrate 2, and the metal layer is formed by sputtering or physical vapor deposition (Physical Vapor Deposition, PVD) or the like. After the formation of the metal layer, the semiconductor substrate 2 is annealed, and the metallic nickel reacts with silicon in the semiconductor substrate 2 or the gate electrode G to produce nickel silicide (NiSi). After the reaction is completed, the unreacted metal layer on the oxide layer is removed, for example, by a chemical cleaning method. In other embodiments, nickel silicide may be replaced by other metal silicide, or may be prepared by selecting a silicide manufacturing process.
Referring to fig. 10 to 11, in step S28, after forming nickel silicide, an interlayer insulating layer is formed on the conductive layer, the electrode or the wiring of the semiconductor device 1 in an embodiment of the present invention. The interlayer insulating layer is etched by etching, for example, dry etching, to form contact holes for connecting the electrodes of the source electrode S, the drain electrode D, and the gate electrode G. The contact hole is filled with a metal such as tungsten (W), a contact portion is formed, and metal wiring or the like is laid on the surface of the contact portion to connect the electrodes of the source electrode S, the drain electrode D, and the gate electrode G.
Referring to fig. 1 and 12, in one example of the present invention, a comparison graph of the potential barrier of MVMOSFETs made in various embodiments is provided. Wherein the horizontal axis represents the electric field strength (G-D) between the gate G and the drain D in the thickness direction X, and the vertical axis represents the electric field strength (S-D) between the source S and the drain D in the width direction Y. In the MOSFET device having a shallow LDD region, the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band are represented by embodiment a, the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band are represented by embodiment b, and the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band are represented by the MOSFET device having a deep LDD region and a thick second portion 9 in the gate oxide layer 7. In fig. 12, a solid line, a dash-dot line, and a broken line near the horizontal axis X in the vertical axis Y direction indicate the electric field intensity Ev of the valence band in the different embodiments, and a solid line, a dash-dot line, and a broken line far from the horizontal axis X in the vertical axis Y direction indicate the electric field intensity Ec of the conduction band, respectively.
Referring to fig. 12, in an embodiment of the present invention, a region sandwiched between the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band represents a potential barrier. According to the lines in the figures, the MVMOSFET barriers provided in the different embodiments are compared. As can be seen from fig. 12, the potential barrier of the semiconductor device is gradually enlarged from embodiment a to embodiment c. That is, since the LDD region in the MVMOSFET is formed deeper than the gate oxide layer, the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band are reduced in the X-axis direction in the vicinity of the gate oxide layer, and the potential barrier is enlarged. In addition, since the LDD region in the MVMOSFET is formed deep with respect to the gate oxide layer, an electric field may be generated at a position deep with respect to the gate oxide layer, that is, on the right side in the X-axis direction in fig. 12, to form a potential barrier. In this way, since the potential barrier is enlarged, the number of electrons passing through the potential barrier is reduced, and the gate-induced drain leakage current can be further suppressed.
Referring to fig. 12, in an example of the present invention, the potential barrier of embodiment c is further enlarged by comparing embodiment b with embodiment c. In the embodiments b and c, the LDD region in the MVMOSFET is formed deeper than the gate oxide layer, but in the embodiment c, the gate oxide layer has a thicker second portion, so that the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band are further reduced in the vicinity of the gate oxide layer, and the potential barrier is enlarged. In this way, since the potential barrier is enlarged, the number of electrons passing through the potential barrier is reduced, and the gate-induced drain leakage current can be further suppressed.
Referring to fig. 13, in an example of the present invention, a graph comparing the output characteristics of MVMOSFETs prepared in different embodiments is provided. The horizontal axis in fig. 13 represents the gate voltage Vg, and the vertical axis represents the drain current Id. In fig. 13, the dash-dot line represents GIDL of embodiment b, and the solid line represents GIDL of embodiment c. Wherein the minimum value of the indicated drain current Id in the different lines is the evaluation value of GIDL of the MOSFET.
Referring to fig. 13, in an example of the present invention, in embodiment c, the LDD region is formed deeper with respect to the gate oxide layer and has a thicker second subsection of the MOSFET at the gate oxide layer, compared to the GIDL of the MOSFET in embodiment b, which is formed deeper with respect to the gate oxide layer, which is lower by an amount of, for example, 2.5 orders of magnitude than the GIDL of embodiment b. That is, by forming a thicker second division in the gate oxide film, GIDL of the obtained MOSFET is improved. That is, the present invention can expand the potential barrier of the semiconductor device by changing the structure of the MOSFET, and can suppress GIDL.
Referring to fig. 14, in one example of the present invention, a comparison graph of the potential barriers of MVMOSFETs made in various embodiments is provided. Wherein the horizontal axis represents the electric field strength (G-D) between the gate G and the drain D in the thickness direction X, and the vertical axis represents the electric field strength (S-D) between the source S and the drain D in the width direction Y. Wherein the solid line indicates the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band of the MVMOSFET in the embodiment c, and the embodiment c is a second division in which the LDD region is formed deeper with respect to the gate oxide layer and the gate oxide layer is thicker. The broken line indicates the electric field intensity Ec of the conduction band and Ev of the valence band of the MVMOSFET in the embodiment d, and the embodiment d is the MVMOSFET in which the LDD region is formed deeper with respect to the gate oxide layer and the gate oxide layer has a thicker second division, and the offset portion OS is provided between the end of the drain heavily doped region and the end of the gate electrode G near the drain.
Referring to fig. 14, in an embodiment d of the present invention, the end of the heavily doped region of the drain is offset from the LDD region near the drain, so that the amount of impurities diffusing from the heavily doped region of the drain to the lightly doped region of the drain below the gate is reduced. Thus, the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band are further reduced in the X-axis direction near the gate oxide layer, and the potential barrier is enlarged. That is, by providing the offset portion OS between the end of the drain heavily doped region and the end of the gate electrode close to the drain, GIDL of the MOSFET can be suppressed.
Referring to fig. 1 and 15, in another embodiment of the present invention, the present invention also provides a cross-sectional view of another MVMOSFET11 structure. In the MVMOSFET11, compared with the semiconductor device 1, the end portion of the drain heavily doped region 6 is aligned with the sidewall structure, and no offset portion is provided in the MVMOSFET 11. The end of the gate G is located on the "Bird's beak" of the thicker second section 9, i.e. the two-dot chain line circled in the figure, i.e. the transition region of the second section 9 and the first section 8. In the process of manufacturing the MVMOSFET11, the process of manufacturing the MVMOSFET11 in this embodiment is the same as the process of manufacturing the semiconductor device 1 except that the positions of the photoresist layer and the second division portion 9 formed in the steps S14 and S16 described above are different.
Referring to fig. 1 and 15, in an embodiment of the present invention, in the MVMOSFET11, no offset portion is provided between the end of the drain heavily doped region 6 and the end of the gate G near the drain side, so that the size of the MVMOSFET11 in the width direction Y is shortened, enabling the size of the semiconductor device to be reduced. The MVMOSFET11 in this embodiment is manufactured in the same manner as the semiconductor device 1, except that the position of the polysilicon formed in step S20 is different. By providing the gate G on the gate oxide layer with the end portion of the gate G near the drain side being located on the beak of the second division portion 9, the GIDL of the semiconductor device can be suppressed while the size of the semiconductor device is reduced by providing no offset portion between the gate G and the drain heavily doped region 6.
Referring to fig. 1 and 16, in another embodiment of the present invention, the present invention also provides a cross-sectional view of another MVMOSFET21 structure. In this embodiment, the thicker second sub-portion 9 is formed by chemical vapor deposition, and the gate electrode G is aligned with the end of the second sub-portion 9 near the drain electrode at the end near the drain electrode. In the process of manufacturing the MVMOSFET21, the process of manufacturing the MVMOSFET21 in this embodiment is the same as the process of manufacturing the semiconductor device 1 except that the method of forming the second subsection 9 in step S16 described above is a chemical vapor deposition method. In the thermal oxidation method, a gate oxide layer is formed by thermally treating a semiconductor substrate using a high temperature process, and thus "bird's beak" is formed at both ends of the second segment. Unlike thermal oxidation, the chemical vapor deposition method does not form bird's beak at two ends of the second division, and can precisely control the shapes of the first division and the second division when the gate oxide layer is formed.
Referring to fig. 16, in an embodiment of the present invention, when forming the second sub-portion 9 by the chemical vapor deposition method, it is not necessary to add a new mask, the manufacturing cost is not increased, and the MOSFET with improved GIDL performance can be obtained. In the manufacturing process, before the grid oxide layer is formed by utilizing a chemical vapor deposition method, sacrificial oxidation is firstly carried out on the semiconductor substrate, the damage layer on the surface of the semiconductor substrate or pollution is removed, and then the grid oxide layer is formed, so that the grid oxide layer with higher uniformity can be obtained.
Referring to fig. 1, 12 and 16, in the semiconductor device according to the embodiment of the invention, the thickness of the gate oxide layer 7 is greater near the drain side than near the source side, i.e., a thicker second portion 9 is formed near the drain side. Wherein the drain lightly doped region 4 is arranged in contact with the lower surface of the second sub-portion 9. The source lightly doped region 3 is located on the lower surface of the first subsection 8, and the source lightly doped region 3 and the drain lightly doped region 4 are arranged at intervals in the width direction Y. The drain heavily doped region 6 is formed in the drain lightly doped region remote from the second partition 9, and the depth of the drain heavily doped region 6 is smaller than that of the drain lightly doped region 4. Therefore, in the vicinity of the gate oxide layer, the potential barrier is enlarged, and the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band are reduced in each direction, so that the obtained MVMOSFET can suppress GIDL. The manufacturing process is the same as that of the MOSFET, and a new manufacturing process or mask is not required to be added. The performance of the semiconductor device can be improved without increasing the manufacturing cost.
In summary, the semiconductor device has a MOSFET structure, and the method for manufacturing the semiconductor device includes: and a gate oxide layer forming step for forming a second portion of the gate oxide layer thicker in the drain region than in the source region. And a lightly doped region forming step, wherein the source lightly doped region and the drain lightly doped region are arranged at intervals, the drain lightly doped region is formed below the second division, and the source lightly doped region is formed below the gate oxide layer. And forming a heavily doped region, wherein the drain heavily doped region is formed on the drain lightly doped region of the second subsection, which is close to the outer side of the drain side, and the implantation energy of the drain heavily doped region is smaller than that of the drain lightly doped region. The semiconductor device formed includes: the thickness of the second part of the grid oxide layer on the drain side is larger than that of the first part on the source side. The drain electrode lightly doped region is positioned on the lower surface of the second sub-part, and the source electrode lightly doped region is positioned on the lower surface of the second sub-part and is arranged at intervals with the drain electrode lightly doped region in the width direction. The drain heavily doped region is formed at the end far away from the second subsection, and the impurity injection energy of the drain heavily doped region is smaller than that of the drain lightly doped region, so that the interface depth of the drain heavily doped region is smaller than that of the drain lightly doped region. In addition, in the semiconductor device, the potential barrier is enlarged in the vicinity of the gate oxide layer, and the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band are small in each direction, so GIDL of the semiconductor device can be suppressed. Meanwhile, in the manufacturing process of the semiconductor device, a new manufacturing process or mask is not required to be added. Therefore, the performance of the semiconductor device can be improved without increasing the manufacturing cost.
Reference throughout this specification to "one embodiment," "an embodiment," or "a particular embodiment (a specific embodiment)" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily in all embodiments, of the invention. Thus, the appearances of the phrases "in one embodiment (in one embodiment)", "in an embodiment (in an embodiment)", or "in a specific embodiment (in a specific embodiment)" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It will be appreciated that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the invention.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (8)

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming a source light doping region in the semiconductor substrate;
forming a drain light doping region in the semiconductor substrate, wherein the drain light doping region and the source light doping region are arranged at intervals;
forming a gate oxide layer on the semiconductor substrate, wherein the gate oxide layer comprises a first subsection and a second subsection, the thickness of the second subsection is larger than that of the first subsection, the first subsection is arranged above the source light doping region and part of the drain light doping region, the second subsection is arranged above part of the drain light doping region, and the second subsection is arranged close to the source light doping region; and
forming a drain heavy doping region in the drain light doping region, wherein the drain heavy doping region is arranged in the drain light doping region at one side of the second partition part far away from the source light doping region, and the implantation energy of the drain heavy doping region is smaller than that of the drain light doping region;
the forming step of the gate oxide layer comprises the following steps:
forming a hard mask layer on the semiconductor substrate with the drain lightly doped region;
forming a photoresist layer on the hard mask layer, wherein the photoresist layer exposes part of the hard mask layer on the drain light doped region;
etching the hard mask layer to the semiconductor substrate by taking the photoresist layer as a mask to form an opening;
removing the photoresist layer;
forming a second part on the semiconductor substrate in the opening, wherein the thickness of the second part is 120nm, and the width of the second part is 200-300 nm;
removing the hard mask layer; and
the first branch is formed on the semiconductor substrate except the second branch.
2. The method according to claim 1, wherein the semiconductor device further comprises a gate electrode, wherein the gate electrode is provided over the gate oxide layer, and wherein a portion of the gate electrode is provided over the second portion.
3. The method according to claim 2, wherein an offset portion is provided between the gate electrode and the second portion at an end of the gate electrode adjacent to the drain heavily doped region.
4. The method of manufacturing a semiconductor device according to claim 2, wherein an end of the gate adjacent to the drain heavily doped region is aligned with an end of the second partition adjacent to the drain heavily doped region.
5. The method of manufacturing a semiconductor device according to claim 1, further comprising a gate electrode provided on the gate oxide layer, wherein a portion of the gate electrode is provided on the second portion and extends to a transition region between the second portion and the first portion near the side of the drain heavily doped region.
6. The method according to claim 1, wherein the source lightly doped region and the drain lightly doped region are the same in the kind of impurity implanted therein, and wherein the impurity implantation doses are the same.
7. The method for manufacturing a semiconductor device according to claim 1, wherein an implantation dose of impurities in the source light-doped region and the drain light-doped region is 1×10 13 atoms/cm 2 。
8. The method according to claim 1, wherein the step of forming the source lightly doped region and the drain lightly doped region is before the step of forming the gate oxide layer.
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