CN102610525A - Method for reducing leakage of gate-induced drain electrode of semiconductor device - Google Patents
Method for reducing leakage of gate-induced drain electrode of semiconductor device Download PDFInfo
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- CN102610525A CN102610525A CN2012100777177A CN201210077717A CN102610525A CN 102610525 A CN102610525 A CN 102610525A CN 2012100777177 A CN2012100777177 A CN 2012100777177A CN 201210077717 A CN201210077717 A CN 201210077717A CN 102610525 A CN102610525 A CN 102610525A
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Abstract
The invention provides a method for reducing the leakage of a gate-induced drain electrode of a semiconductor device. The method comprises the following steps that: a semiconductor substrate is provided, a gate electrode dielectric layer and a gate electrode are sequentially formed on the semiconductor substrate, the gate electrode is provided with a first side and a second side, the semiconductor substrate at the first side of the gate electrode is a source electrode region, and the semiconductor substrate at the second side of the gate electrode is a drain electrode region, the method also comprises the step of carrying out inclined angle light doping drain electrode injection on a drain electrode and a source electrode so that a drain electrode light doping region is formed in the drain electrode region, and a source electrode light doping region is formed in the source electrode region. The method for reducing the leakage of the gate-induced drain electrode of the semiconductor device is invented, and the inclined angle injection method is effectively adopted, so the overlapping region of the drain terminal and the gate electrode is reduced under the condition of maintaining the effective length of a channel unchanged, the effective longitudinal electric field of the drain terminal is weakened, the gate-induced drain electrode leakage current of the semiconductor device is reduced, and meanwhile, the effective longitudinal electrode field of the drain terminal is weakened under the condition of maintaining the effective length of the channel unchanged.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field, relate in particular to a kind of method that semiconductor device gate is induced drain leakage current that reduces.
Background technology
Gate-induced drain leaks (Gate Induced Drain Leakage; Be called for short GIDL) be meant, under the situation that device is turn-offing, (being positive voltage on the grid=0); If drain electrode links to each other with forward voltage drop; (be that forward voltage drop=Vdd), because the overlapping between grid and the drain electrode, can there be highfield in the overlapping region between grid and drain electrode; Tunneling effect (band to band tunneling) can is with-be with to charge carrier under the highfield effect, thereby cause the leakage current between the drain-to-gate.
The gate-induced drain leakage current has become the one of the main reasons of aspects such as influencing small size MOS device reliability, power consumption; It also has material impact to the erasable operation of EEPROM memory devices such as (Electrically Erasable Programmable Read-Only Memory are called for short EEPROM) simultaneously.When technology gets into sub-micro after the epoch, owing to device size dwindles day by day, numerous integrity problems of GIDL electric current initiation become serious further.
Usually in technology; Carrying out lightly doped drain injection (Lightly Doped Drain, i.e. LDD) direction is perpendicular to silicon chip surface, leaks light doping section through injecting with annealing process formation source afterwards; The cross section of device is as shown in Figure 1; 5 one-tenth symmetrical structures of drain electrode lightly doped region in the source electrode lightly doped region 3 in source class district 2 and the drain region 4 in the drawings, because overlapping between the drain electrode lightly doped region 3 in gate electrode 6 and the drain region 2, can there be highfield in the overlapping region between gate electrode 6 and drain region 2; Tunneling effect can is with-be with to charge carrier under the highfield effect, thereby cause the leakage current between the drain-to-gate.
Summary of the invention
Disclosure of the Invention a kind ofly reduce the method that semiconductor device gate is induced drain leakage current.In order to solve in the prior art in the lightly doped drain injection technology, tunneling effect is with-is with to charge carrier can under the effect of the existing highfield of crossover region between grid and the drain electrode, thereby reduce to cause the problem of leakage current between the drain-to-gate.
For realizing above-mentioned purpose, the technical scheme that invention is adopted is:
A kind ofly reduce the method that semiconductor device gate is induced drain leakage current; Comprise: Semiconductor substrate is provided, is formed with gate dielectric layer and gate electrode on the said Semiconductor substrate successively, said gate electrode has first side and second side; The Semiconductor substrate of said gate electrode first side is a source area; The Semiconductor substrate of second side is the drain region, wherein, also comprises: the injection of oblique angle lightly doped drain is carried out in drain electrode and source electrode; Make to form the drain electrode lightly doped region in the drain region, form the source electrode lightly doped region in the source area.
Above-mentioned method, wherein, the direction that lightly doped drain injects is that benchmark carries out the lightly doped drain injection to source area drift angle 10 degree to said source area and said drain region for from top to bottom with the vertical source polar region.
Above-mentioned method, wherein, the length that the said source electrode light doping section length of field in the said source area is longer than the said drain electrode lightly doped region in the said drain region.
Above-mentioned method, wherein, the said gate electrode of said source electrode lightly doped region and top has the overlapping part.
Above-mentioned method, wherein, the said gate electrode of said drain electrode lightly doped region and top has the overlapping part.
Above-mentioned method, wherein, the overlapping partial-length of said source electrode lightly doped region and the said gate electrode in top is longer than the overlapping part of said drain electrode lightly doped region and the said gate electrode in top.
A kind ofly among the present invention reduce the method that semiconductor device gate is induced drain leakage current, having adopted as above, scheme has following effect:
1, the method that adopts the oblique angle to inject is effectively remained valid under the constant situation of length raceway groove, has reduced drain terminal and grid overlapping region, has reduced effective longitudinal electric field of drain terminal, causes drain leakage current thereby reduced semiconductor device gate;
2, keep simultaneously having reduced the effective longitudinal electric field of drain terminal under the constant situation of raceway groove effective length.
Description of drawings
Through the detailed description that reading is done non-limiting example with reference to following accompanying drawing, the further feature of invention, it is more obvious that purpose and advantage will become.
Fig. 1 is the sketch map in device cross section after the common lightly doped drain injection technology;
Fig. 2 is a kind of upper shield sketch map that semiconductor device gate is induced the method for drain leakage current that reduces;
Reference diagram preface: substrate 1, drain region 2, drain electrode lightly doped region 3, source area 4, source electrode lightly doped region 5, gate electrode 6, gate dielectric layer 7.
Embodiment
For technological means that invention is realized, create characteristic, reach purpose and effect and be easy to understand and understand that following combinations specifically illustrates, and further sets forth the present invention.
As shown in Figure 2, a kind ofly reduce the method that semiconductor device gate is induced drain leakage current, comprising: Semiconductor substrate 1 is provided; Be formed with gate dielectric layer 7 and gate electrode 6 on the Semiconductor substrate 1 successively; Further gate electrode 6 is positioned among the dielectric layer 7, and gate electrode 6 has first side and second side, and the Semiconductor substrate 1 of gate electrode 6 first sides is a source area 4; The Semiconductor substrate 1 of second side is drain region 2, more than is existing MOS
The processing step of device; Wherein, Also comprise: the injection of oblique angle lightly doped drain is carried out in drain region 2 and source area 4; Make to form drain electrode lightly doped region 3 in the drain region 2, form source electrode lightly doped region 5 in the source area 4, to accomplish of the formation of drain electrode lightly doped region 3 with source electrode lightly doped region 5.
In specific embodiment of the present invention; The direction that lightly doped drain injects is for from top to bottom being covered in the upper surface of MOS device; And inject so that to be benchmark carry out lightly doped drain to the direction of source area 4 drift angles 10 degree to source area 4 and drain region 2 in vertical source polar region 4; Further, in the drain region 2, because ion that lightly doped drain injects and the distance between the semiconductor device raceway groove are zoomed out; Thereby the length of formed drain electrode lightly doped region 3 is shorter with respect to the length of original drain electrode lightly doped region 3; The overlapping region of lightly doped region 3 and top gate electrode 6 of draining this moment also reduces, and when gate electrode 6 turn-offs, and drain region 2 reduces in the sphere of action of gate electrode 6 with the longitudinal electric field of drain electrode lightly doped region 3 overlapping regions when connecing positive voltage; Thereby reduced the band-band tunneling effect of charge carrier, reduced semiconductor device gate electrode 6 and caused the electric current that drain region 2 is leaked.
In specific embodiment of the present invention; After drain region 4 being carried out the lightly doped drain injection; Source electrode lightly doped region 5 length in the source area are longer than the length of the drain electrode lightly doped region 3 in the drain region 2; Further, zoomed out at the ion of lightly doped drain injection and the distance between the semiconductor device raceway groove.Simultaneously; Ion that lightly doped drain injected in the source area 4 and the distance between the semiconductor device raceway groove are drawn in; Further, remain unchanged basically at the total length of the quite original drain electrode lightly doped region 3 of the drain electrode lightly doped region 3 and the total length of source electrode lightly doped region 5 with source electrode lightly doped region 5.
In specific embodiment of the present invention, in 45nm cmos device technology, at first be prepared as example with nmos device.The ion that lightly doped drain injects adopts arsenic to inject, and injection direction carries out the injection of lightly doped drain for being the direction of benchmark to source area 4 drift angles 10 degree with the vertical source polar region from top to bottom to source area 4 and drain region 2.Thereby the length of formed drain electrode lightly doped region 3 is shorter with respect to the length of original drain electrode lightly doped region 3; The overlapping region of lightly doped region 3 and top gate electrode 6 of draining simultaneously also reduces; When gate electrode 6 turn-offs, and drain region 2 reduces in the sphere of action of gate electrode 6 with the longitudinal electric field of drain electrode lightly doped region 3 overlapping regions when connecting positive voltages; Thereby reduced the band-band tunneling effect of charge carrier, reduced semiconductor device gate electrode 6 and caused the electric current that drain region 2 is leaked.
In sum, invent a kind of method that semiconductor device gate is induced drain leakage current that reduces, the method that adopts the oblique angle to inject effectively; Raceway groove is remained valid under the constant situation of length; Reduced drain terminal and grid overlapping region, reduced effective longitudinal electric field of drain terminal, caused drain leakage current thereby reduced semiconductor device gate; Keep simultaneously having reduced the effective longitudinal electric field of drain terminal under the constant situation of raceway groove effective length.
More than to the invention specific embodiment be described.It will be appreciated that invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Those skilled in the art can make various distortion or modification within the scope of the claims, and this does not influence the essence of an invention content.
Claims (6)
1. one kind reduces the method that semiconductor device gate is induced drain leakage current; Comprise: Semiconductor substrate is provided, is formed with gate dielectric layer and gate electrode on the said Semiconductor substrate successively, said gate electrode has first side and second side; The Semiconductor substrate of said gate electrode first side is a source area; The Semiconductor substrate of second side is the drain region, it is characterized in that, also comprises: the injection of oblique angle lightly doped drain is carried out in drain region and source area; Make to form the drain electrode lightly doped region in the drain region, form the source electrode lightly doped region in the source area.
2. method according to claim 1 is characterized in that, the direction that lightly doped drain injects is that benchmark carries out the lightly doped drain injection to source area drift angle 10 degree to said source area and said drain region for from top to bottom with the vertical source polar region.
3. method according to claim 1 is characterized in that, the length that the said source electrode light doping section length of field in the said source area is longer than the said drain electrode lightly doped region in the said drain region.
4. method according to claim 1 is characterized in that, the said gate electrode of said source electrode lightly doped region and top has the overlapping part.
5. method according to claim 1, wherein, the said gate electrode of said drain electrode lightly doped region and top has the overlapping part.
6. according to claim 4 or 5 described methods, it is characterized in that the overlapping partial-length of said source electrode lightly doped region and the said gate electrode in top is longer than the overlapping part of said drain electrode lightly doped region and the said gate electrode in top.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100777177A CN102610525A (en) | 2012-03-22 | 2012-03-22 | Method for reducing leakage of gate-induced drain electrode of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100777177A CN102610525A (en) | 2012-03-22 | 2012-03-22 | Method for reducing leakage of gate-induced drain electrode of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112599436A (en) * | 2020-12-10 | 2021-04-02 | 泉芯集成电路制造(济南)有限公司 | Transistor and STI abnormal hole detection method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101447514A (en) * | 2008-12-30 | 2009-06-03 | 上海宏力半导体制造有限公司 | Metal oxide semiconductor field effect transistor |
| CN102386234A (en) * | 2010-09-03 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Strained asymmetric source/drain |
| CN102446717A (en) * | 2011-09-08 | 2012-05-09 | 上海华力微电子有限公司 | Method for reducing damage of semiconductor device caused during hot carrier injection |
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2012
- 2012-03-22 CN CN2012100777177A patent/CN102610525A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101447514A (en) * | 2008-12-30 | 2009-06-03 | 上海宏力半导体制造有限公司 | Metal oxide semiconductor field effect transistor |
| CN102386234A (en) * | 2010-09-03 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Strained asymmetric source/drain |
| CN102446717A (en) * | 2011-09-08 | 2012-05-09 | 上海华力微电子有限公司 | Method for reducing damage of semiconductor device caused during hot carrier injection |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112599436A (en) * | 2020-12-10 | 2021-04-02 | 泉芯集成电路制造(济南)有限公司 | Transistor and STI abnormal hole detection method |
| CN112599436B (en) * | 2020-12-10 | 2022-07-05 | 泉芯集成电路制造(济南)有限公司 | Detection structure and STI abnormal hole detection method |
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Application publication date: 20120725 |