CN101447410A - 半导体器件的制造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 82
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 69
- 239000000463 material Substances 0.000 claims abstract description 61
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000005516 engineering process Methods 0.000 claims description 46
- 230000003647 oxidation Effects 0.000 claims description 26
- 238000007254 oxidation reaction Methods 0.000 claims description 26
- 238000004140 cleaning Methods 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 8
- 239000002253 acid Substances 0.000 claims description 8
- 239000007864 aqueous solution Substances 0.000 claims description 8
- 239000011324 bead Substances 0.000 claims description 8
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 4
- 239000002904 solvent Substances 0.000 claims description 4
- 239000000243 solution Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 4
- 238000012958 reprocessing Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000013100 final test Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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Abstract
一种用于半导体器件的制造方法简化了用于形成高压器件的氧化膜的工艺,从而降低了高压器件的制造成本和制造时间。该制造方法包括在半导体晶片上方涂覆栅极氧化物材料,在栅极氧化物材料上方涂覆光刻胶材料,在光刻胶材料上实施曝光工艺和第一显影工艺以形成光刻胶图样,实施使用了光刻胶图样的刻蚀工艺以形成栅极氧化膜,以及实施第二显影工艺以去除光刻胶图样。
Description
本申请基于35 U.S.C 119要求第10-2007-0122591号(于2007年11月29日递交)韩国专利申请的优先权,其全部内容结合于此作为参考。
技术领域
本发明涉及一种半导体器件的制造方法,更具体地,涉及一种半导体器件的制造方法,该制造方法能够简化用于形成高压器件的氧化膜的工艺,从而降低高压器件的制造成本和制造时间。
背景技术
通常,用于制造半导体器件的工艺可以划分为预处理和后处理。可以以下述顺序来实施预处理:氧化、应用光刻胶、曝光、显影、刻蚀、离子注入、化学气相沉积、金属化以及引线键合(wirebonding)。在预处理之后实施后处理,该后处理包括组装(assembly)和检测(inspection)。具体地,可以以下述顺序来实施后处理:晶片EDS测试、晶片切割(wafer sawing)、芯片固定(chip dieattachment)、引线键合、成型以及最终测试。通过上述工艺可以在晶片上形成高压器件或低压器件。然而,当在单个晶片上形成高压器件和低压器件时,制造工艺变得非常复杂。
图1A到图1C是示出了形成高压器件的栅极氧化膜的相关方法的过程截面图。首先,如图1A中所示,在半导体晶片2上方顺序形成栅极氧化物材料层4a和例如光刻胶层6a的感光膜。这里,栅极氧化物材料层4a可以用作高压器件的栅极绝缘层。通过旋涂装置(spin coating apparatus)的离心力来在半导体晶片2的顶部上方均匀地形成栅极氧化物材料层4a和光刻胶层6a。随后,将溶剂喷射到半导体晶片2的边缘以从半导体晶片2的边缘处去除光刻胶层6a(边缘球状物去除(edge bead removal):EBR)。这样,完成预曝光工艺。
随后,如图1B中所示,布置掩膜,并且实施曝光工艺以形成图样。使用显影剂来使曝光的半导体晶片2显影,以便除了选定的部分光刻胶层6a之外,光刻胶层6a的剩余部分形成光刻胶图样6。随后,将去离子水(DI水)喷射到已经喷射了显影剂的半导体晶片2,以清洗半导体晶片2,以及然后将清洗过的半导体晶片2烘干。从经过显影的光刻胶图样6处去除残留的溶液,以及同时实施硬烘培工艺(坚膜工艺,hard baking process)以增强光刻胶图样6的结合力(bonding strength)和改善光刻胶图样6的形态(morphology)。
随后,如图1C中所示,在24℃到25℃的温度下实施使用了缓冲氟化氢(buffered hydrogen fluoride)(BHF)的湿法刻蚀工艺以在半导体晶片2上方形成栅极氧化膜4。随后,实施使用了显影剂的显影工艺以去除光刻胶图样6,以及然后实施清洗(washing)和烘干(drying)工艺,以便在半导体晶片2上方仅留下栅极氧化膜4。
然而,形成高压器件的栅极氧化膜的该相关方法存在问题。在形成光刻胶图样6之后,必须实施诸如清洗工艺、烘干工艺和硬烘培工艺的各种工艺以形成栅极氧化膜4。这增加了高压器件的制造时间和制造成本。
发明内容
本发明实施例涉及一种半导体器件的制造方法,更具体地,涉及一种半导体器件的制造方法,该制造方法能够简化用于形成高压器件的氧化膜的工艺,从而降低高压器件的制造成本和制造时间。
本发明实施例涉及一种半导体器件的制造方法,该制造方法能够简化用于形成高压器件的氧化膜的工艺,从而降低高压器件的制造成本和制造时间。
本发明实施例涉及一种半导体器件的制造方法,该方法包括在半导体晶片上方涂覆(applying)栅极氧化物材料,在栅极氧化物材料上方涂覆光刻胶材料,在光刻胶材料上实施曝光工艺和第一显影工艺(初次显影工艺,primary development process)以形成光刻胶图样,实施使用了光刻胶图样的刻蚀工艺以形成栅极氧化膜,以及实施第二显影工艺(二次显影工艺,secondary developmentprocess)以去除光刻胶图样。根据本发明实施例,形成栅极氧化膜可以包括在24℃到25℃的温度下实施使用了缓冲氟化氢(BHF)的湿法刻蚀工艺。可以使用选自由硫磺酸(sulfuric acid)、臭氧和超度含水溶液(hyperhydric solution)组成的组中的至少一种来实施上述的第二显影工艺。根据本发明实施例,在形成栅极氧化膜之后,去除光刻胶图样可以包括使用选自由硫磺酸、臭氧和超度含水溶液组成的组中的至少一种来实施第二显影工艺,而不需要另外的清洗工艺、烘干工艺和硬烘培工艺。
本发明实施例涉及一种方法,该方法可以包括下列中的至少一个:在半导体晶片上方涂覆栅极氧化物材料;在栅极氧化物材料上方涂覆光刻胶材料;在光刻胶材料上实施曝光工艺和第一显影工艺以形成光刻胶图样;实施使用了光刻胶图样的刻蚀工艺以形成栅极氧化膜;以及然后实施第二显影工艺以去除光刻胶图样。
本发明实施例涉及一种方法,该方法可以包括下列中的至少一个:在半导体晶片上方形成氧化物材料;在氧化物材料上方形成光刻胶材料;通过在光刻胶材料上实施曝光工艺和第一显影工艺来形成光刻胶图样;通过使用光刻胶图样作为掩膜在氧化物材料上实施刻蚀工艺来形成栅极氧化膜;以及然后在形成栅极氧化膜之后,通过实施第二显影工艺来去除光刻胶图样。
附图说明
图1A到图1C是示出了形成高压器件的栅极氧化膜的相关方法的过程截面图。
实例图2示出了一种根据本发明实施例的用于制造高压器件的装置。
实例图3A到图3C示出了一种根据本发明实施例的形成高压器件的栅极氧化膜的方法。
实例图4示出了一种根据本发明实施例的高压器件的制造方法。
具体实施方式
实例图2是示出了用于制造根据本发明实施例的高压器件的装置的结构图。实例图2中所示的制造装置包括其上安装有半导体晶片2的旋转卡盘(rotary chuck)24,使旋转卡盘24旋转的转轴(rotaryshaft)22,化学材料(沉积和刻蚀材料)喷嘴26,以及超高纯溶液喷嘴(ultra pure solution spray nozzle)28。该制造装置可以进一步包括LIC-3喷嘴和N2气喷嘴。该制造装置通过安装在基座(susceptor)处的LIC-3喷嘴、化学材料(沉积和刻蚀材料)喷嘴26、N2气喷嘴以及超高纯溶液喷嘴28来喷射化学材料、超高纯溶液和N2气。同样,该制造装置可以进一步包括动力法兰(powerflange)、SUS室、钟罩加热器(bell jar heater)、槽阈(slot valve)以及真空泵(vacuum pump),其中,动力法兰连接至安装在普通单一型装置处的基座以向上或向下移动基座,SUS室包括围绕基座和动力法兰的石英圆顶(quartz dome),钟罩加热器用来调节SUS室中的处理温度,槽阈根据半导体晶片2的进入(introduction)和回退(withdrawal)来设定为打开或关闭,而真空泵用来在SUS室中产生真空。
实例图3A到图3C是示出了根据本发明实施例的形成高压器件的栅极氧化膜的方法的过程截面图,而实例图4是示出了根据本发明实施例的高压器件的制造方法的流程图。首先,如实例图3A中所示,可以将半导体晶片32放置在旋转卡盘24上,其中栅极氧化物材料34a和光刻胶材料36a将被涂覆至该半导体晶片32。可以在半导体晶片32上实施六甲基二硅胺烷(hexamethyl-disilazane)(HMDS)工艺以便可以将栅极氧化物材料或用于半导体晶片光刻的光刻胶材料有效地粘合至半导体晶片32的表面。可以将半导体晶片32冷却到预定的温度。旋转卡盘24旋转以向半导体晶片32提供离心力。随后,可以将栅极氧化物材料34a涂覆至半导体晶片32。通过离心力,可以在半导体晶片32的整个表面上方均匀地涂覆栅极氧化物材料34a。在栅极氧化物材料34a固化之后,可以将光刻胶材料36a涂覆至固化的栅极氧化物材料34a。通过离心力可以在栅极氧化物材料34a的整个表面上方均匀地涂覆光刻胶材料36a。随后,可以将溶剂喷射到半导体晶片32的边缘以从半导体晶片32的边缘处去除光刻胶层36a(边缘球状物去除,edge beadremoval)。这样,完成预曝光工艺(S1)。
随后,如实例图3B中所示,可以布置掩膜,并且实施曝光工艺以形成图样。使用显影剂来使曝光的半导体晶片32显影,并且除了选定的部分光刻胶层36a以外剩余的部分光刻胶层36a,即光刻胶层36a的图样部分形成了光刻胶图样36(S2)。在曝光工艺期间或之后,可以通过附加的晶圆边缘曝光球状物去除(optical edgebead removal)(OEBR)装置来实施OEBR工艺以更安全地从半导体晶片32的边缘处去除光刻胶层36a。
随后,如实例图3C中所示,可以在24℃到25℃的温度下实施使用了缓冲氟化氢(BHF)的湿法刻蚀工艺以在半导体晶片32上方形成栅极氧化膜34。也就是,可以去除除了与光刻胶图样36相对应的部分栅极氧化物材料34a以外剩余的部分栅极氧化物材料34a以形成栅极氧化膜34(S3)。可以使用选自由硫磺酸、臭氧和超度含水溶液组成的组中至少一种来实施显影工艺以去除光刻胶图样36(S4)。可以实施清洗工艺和烘干工艺。在半导体晶片32上仅留下栅极氧化膜34(S5)。
在根据如上所述的本发明实施例的半导体器件的制造方法中,在实施用于形成光刻胶图样36(S2)的工艺之后,可以去除除了与光刻胶图样36相对应的部分栅极氧化物材料34a以外剩余的部分栅极氧化物材料34a,以形成栅极氧化膜34(S3),而不需要另外的清洗、烘干和硬烘培工艺。随后,可以使用选自由硫磺酸、臭氧和超度含水溶液组成的组中的至少一种来实施显影工艺(S4)以在半导体晶片32上仅留下栅极氧化膜34。
根据本发明实施例,如上所述,简化了用于形成高压器件的栅极氧化膜34的工艺。因此,降低了用于高压器件的制造成本和制造时间。根据本发明实施例的半导体器件的制造方法具有简化用于形成高压器件的氧化膜的工艺,从而降低制造成本和制造时间的效果。
尽管本文中描述了多个实施例,但是应该理解,本领域技术人员可以想到多种其他修改和实施例,它们都将落入本公开的原则的精神和范围内。更特别地,在本公开、附图、以及所附权利要求的范围内,可以在主题结合排列的排列方式和/或组成部分方面进行各种修改和改变。除了组成部分和/或排列方面的修改和改变以外,可选的使用对本领域技术人员来说也是显而易见的。
Claims (20)
1.一种方法,包括:
在半导体晶片上方涂覆栅极氧化物材料;
在所述栅极氧化物材料上方涂覆光刻胶材料;
在所述光刻胶材料上实施曝光工艺和第一显影工艺以形成光刻胶图样;
实施使用了所述光刻胶图样的刻蚀工艺以形成栅极氧化膜;以及然后
实施第二显影工艺以去除所述光刻胶图样。
2.根据权利要求1所述的方法,其中,形成所述栅极氧化膜包括实施使用了缓冲氟化氢的湿法刻蚀工艺。
3.根据权利要求2所述的方法,其中,在大约24℃到25℃之间的范围内的温度下进行实施使用了缓冲氟化氢的所述湿法刻蚀工艺。
4.根据权利要求1所述的方法,其中,使用选自由硫磺酸、臭氧和超度含水溶液组成的组中的至少一种来实施所述第二显影工艺。
5.根据权利要求1所述的方法,其中,在形成所述光刻胶图样之后,实施所述第二显影工艺包括使用选自由硫磺酸、臭氧和超度含水溶液组成的组中的至少一种,而不需要另外的清洗工艺、烘干工艺和硬烘培工艺。
6.根据权利要求1所述的方法,进一步包括:
在向所述半导体晶片上方涂覆所述栅极氧化物材料之前,将所述半导体晶片放置在旋转卡盘上。
7.根据权利要求1所述的方法,进一步包括:
在向所述半导体晶片上方涂覆所述栅极氧化物材料之前,在所述半导体晶片上实施六甲基二硅胺烷工艺。
8.根据权利要求1所述的方法,进一步包括:
在所述栅极氧化物材料上方涂覆所述光刻胶材料之后,在所述半导体晶片的边缘处实施用于喷射溶剂的边缘球状物去除工艺以从所述半导体晶片的所述边缘处去除所述光刻胶材料。
9.根据权利要求1所述的方法,进一步包括:
在所述光刻胶材料上实施所述曝光工艺和所述第一显影工艺以形成所述光刻胶图样之后,实施晶圆边缘曝光球状物去除工艺以从所述半导体晶片的边缘处去除所述光刻胶材料。
10.根据权利要求1所述的方法,进一步包括:
仅在实施所述第二显影工艺以去除所述光刻胶图样之后实施清洗工艺和烘干工艺。
11.一种方法,包括:
在半导体晶片上方形成氧化物材料;
在所述氧化物材料上方形成光刻胶材料;
通过在所述光刻胶材料上实施曝光工艺和第一显影工艺来形成光刻胶图样;
通过使用所述光刻胶图样作为掩膜在所述氧化物材料上实施刻蚀工艺来形成栅极氧化膜;以及然后
在形成所述栅极氧化膜之后,通过实施第二显影工艺去除所述光刻胶图样。
12.根据权利要求11所述的方法,其中,所述刻蚀工艺包括湿法刻蚀工艺,所述湿法刻蚀工艺包括缓冲氟化氢。
13.根据权利要求12所述的方法,其中,所述刻蚀工艺包括在大约24℃到25℃之间的范围内的温度下实施使用了缓冲氟化氢的湿法刻蚀工艺。
14.根据权利要求11所述的方法,其中,使用选自由硫磺酸、臭氧和超度含水溶液组成的组中的至少一种来实施所述第二显影工艺。
15.根据权利要求11所述的方法,其中,在形成所述栅极氧化膜之后,使用选自由硫磺酸、臭氧和超度含水溶液组成的组中的至少一种来实施所述第二显影工艺,而不需要另外的清洗、烘干和硬烘培工艺。
16.根据权利要求11所述的方法,进一步包括,在形成所述氧化物材料之前,将所述半导体晶片固定在旋转卡盘上。
17.根据权利要求11所述的方法,进一步包括,在形成所述氧化物材料之前,先在所述半导体晶片上实施六甲基二硅胺烷工艺。
18.根据权利要求11所述的方法,进一步包括,在形成所述光刻胶材料之后,在所述半导体晶片的边缘处实施用于喷射溶剂的边缘球状物去除工艺以从所述半导体晶片的所述边缘处去除所述光刻胶材料。
19.根据权利要求11所述的方法,进一步包括,在形成光刻胶图样之后,实施晶圆边缘曝光球状物去除工艺以从所述半导体晶片的所述边缘处去除所述光刻胶材料。
20.根据权利要求11所述的方法,进一步包括,在去除所述光刻胶图样之后,实施清洗工艺和烘干工艺。
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CN102709175A (zh) * | 2012-05-23 | 2012-10-03 | 上海宏力半导体制造有限公司 | 深沟槽工艺中光刻胶层的形成方法 |
CN110928142A (zh) * | 2019-11-28 | 2020-03-27 | 北京遥测技术研究所 | 一种光刻厚胶与金属基底结合力的改善方法 |
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US6867148B2 (en) * | 2001-05-16 | 2005-03-15 | Micron Technology, Inc. | Removal of organic material in integrated circuit fabrication using ozonated organic acid solutions |
US20050124160A1 (en) * | 2003-12-05 | 2005-06-09 | Taiwan Semiconductor Manufacturing Co. | Novel multi-gate formation procedure for gate oxide quality improvement |
DE102004029012B4 (de) * | 2004-06-16 | 2006-11-09 | Leica Microsystems Semiconductor Gmbh | Verfahren zur Inspektion eines Wafers |
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CN102709175A (zh) * | 2012-05-23 | 2012-10-03 | 上海宏力半导体制造有限公司 | 深沟槽工艺中光刻胶层的形成方法 |
CN102709175B (zh) * | 2012-05-23 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | 深沟槽工艺中光刻胶层的形成方法 |
CN110928142A (zh) * | 2019-11-28 | 2020-03-27 | 北京遥测技术研究所 | 一种光刻厚胶与金属基底结合力的改善方法 |
CN110928142B (zh) * | 2019-11-28 | 2023-08-29 | 北京遥测技术研究所 | 一种光刻厚胶与金属基底结合力的改善方法 |
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