CN101438236A - 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统 - Google Patents

用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统 Download PDF

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Publication number
CN101438236A
CN101438236A CNA2007800165248A CN200780016524A CN101438236A CN 101438236 A CN101438236 A CN 101438236A CN A2007800165248 A CNA2007800165248 A CN A2007800165248A CN 200780016524 A CN200780016524 A CN 200780016524A CN 101438236 A CN101438236 A CN 101438236A
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China
Prior art keywords
unit
register
units
word
instruction
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Pending
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CNA2007800165248A
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English (en)
Chinese (zh)
Inventor
曾贸
卢奇安·科德雷斯库
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Qualcomm Inc
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Qualcomm Inc
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Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to CN201410348018.0A priority Critical patent/CN104133748B/zh
Publication of CN101438236A publication Critical patent/CN101438236A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
CNA2007800165248A 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统 Pending CN101438236A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410348018.0A CN104133748B (zh) 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/431,300 2006-05-10
US11/431,300 US8127117B2 (en) 2006-05-10 2006-05-10 Method and system to combine corresponding half word units from multiple register units within a microprocessor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201410348018.0A Division CN104133748B (zh) 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统

Publications (1)

Publication Number Publication Date
CN101438236A true CN101438236A (zh) 2009-05-20

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CNA2007800165248A Pending CN101438236A (zh) 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统
CN201410348018.0A Active CN104133748B (zh) 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统

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Country Status (6)

Country Link
US (1) US8127117B2 (enExample)
EP (1) EP2027533A2 (enExample)
JP (4) JP2009536774A (enExample)
KR (1) KR100988964B1 (enExample)
CN (2) CN101438236A (enExample)
WO (1) WO2007134013A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107273095A (zh) * 2011-04-01 2017-10-20 英特尔公司 用于对齐寄存器的系统、装置和方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8127117B2 (en) * 2006-05-10 2012-02-28 Qualcomm Incorporated Method and system to combine corresponding half word units from multiple register units within a microprocessor
US8417922B2 (en) * 2006-08-02 2013-04-09 Qualcomm Incorporated Method and system to combine multiple register units within a microprocessor
JP2011242995A (ja) * 2010-05-18 2011-12-01 Toshiba Corp 半導体装置
KR101783312B1 (ko) 2011-11-15 2017-10-10 삼성전자주식회사 클러스터 간의 통신으로 인한 오버헤드를 최소화하는 장치 및 방법
JP5701930B2 (ja) * 2013-04-22 2015-04-15 株式会社東芝 半導体装置
US11593117B2 (en) 2018-06-29 2023-02-28 Qualcomm Incorporated Combining load or store instructions
KR102685097B1 (ko) 2018-12-07 2024-07-16 한화오션 주식회사 파이프 시편 절단용 지그기구
KR102663496B1 (ko) * 2022-08-02 2024-05-08 이화여자대학교 산학협력단 프로세서의 레지스터 캐시 인덱스 결정 방법 및 이를 수행하는 전자 장치

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JPH0415832A (ja) * 1990-05-09 1992-01-21 Nec Corp 障害処理方式
US5564056A (en) * 1994-03-01 1996-10-08 Intel Corporation Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
EP0743591B1 (en) 1995-05-16 2002-01-02 Océ-Technologies B.V. Printing system comprising a communication control apparatus
GB9509988D0 (en) * 1995-05-17 1995-07-12 Sgs Thomson Microelectronics Matrix transposition
GB9509987D0 (en) 1995-05-17 1995-07-12 Sgs Thomson Microelectronics Manipulation of data
CN1264085C (zh) * 1995-08-31 2006-07-12 英特尔公司 一种用于执行多媒体应用的操作的装置、系统和方法
WO1997009679A1 (en) * 1995-09-01 1997-03-13 Philips Electronics North America Corporation Method and apparatus for custom processor operations
US5933650A (en) * 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6052522A (en) 1997-10-30 2000-04-18 Infineon Technologies North America Corporation Method and apparatus for extracting data stored in concatenated registers
EP1194835A2 (en) * 1999-05-13 2002-04-10 ARC International U.S. Holdings Inc. Method and apparatus for loose register encoding within a pipelined processor
US6463525B1 (en) * 1999-08-16 2002-10-08 Sun Microsystems, Inc. Merging single precision floating point operands
US6631460B1 (en) * 2000-04-27 2003-10-07 Institute For The Development Of Emerging Architectures, L.L.C. Advanced load address table entry invalidation based on register address wraparound
WO2001086431A1 (en) * 2000-05-05 2001-11-15 Lee Ruby B A method and system for performing subword permutation instructions for use in two-dimensional multimedia processing
US7228403B2 (en) 2000-12-23 2007-06-05 International Business Machines Corporation Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture
JP3776732B2 (ja) 2001-02-02 2006-05-17 株式会社東芝 プロセッサ装置
US7103756B2 (en) * 2002-09-30 2006-09-05 Hewlett-Packard Development Company, L.P. Data processor with individually writable register subword locations
US7689641B2 (en) * 2003-06-30 2010-03-30 Intel Corporation SIMD integer multiply high with round and shift
GB2409064B (en) * 2003-12-09 2006-09-13 Advanced Risc Mach Ltd A data processing apparatus and method for performing in parallel a data processing operation on data elements
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US8127117B2 (en) * 2006-05-10 2012-02-28 Qualcomm Incorporated Method and system to combine corresponding half word units from multiple register units within a microprocessor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107273095A (zh) * 2011-04-01 2017-10-20 英特尔公司 用于对齐寄存器的系统、装置和方法
CN107273095B (zh) * 2011-04-01 2020-12-29 英特尔公司 用于对齐寄存器的系统、装置和方法

Also Published As

Publication number Publication date
US8127117B2 (en) 2012-02-28
JP2016194929A (ja) 2016-11-17
JP2009536774A (ja) 2009-10-15
WO2007134013B1 (en) 2008-02-14
EP2027533A2 (en) 2009-02-25
WO2007134013A3 (en) 2008-01-10
KR20090009959A (ko) 2009-01-23
JP2013242892A (ja) 2013-12-05
US20070266226A1 (en) 2007-11-15
CN104133748A (zh) 2014-11-05
WO2007134013A2 (en) 2007-11-22
CN104133748B (zh) 2018-10-19
JP2018156672A (ja) 2018-10-04
JP6242615B2 (ja) 2017-12-06
KR100988964B1 (ko) 2010-10-20

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Application publication date: 20090520