CN101425541B

CN101425541B - Semiconductor element and device using the same

Info

Publication number: CN101425541B
Application number: CN2008101842571A
Authority: CN
Inventors: 片冈耕太郎; 岩田浩; 太田佳似; 木本贤治; 小宫健治; 足立浩一郎; 柴田晃秀; 原田真臣
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2007-09-18
Filing date: 2008-09-18
Publication date: 2011-03-02
Anticipated expiration: 2028-09-18
Also published as: CN101425541A; JP4521433B2; JP2009076485A

Abstract

A memory element having a large memory window and a high reliability is provided at low cost by performing high speed write and erase operations at a relatively low voltage and suppressing rewrite degradation. A memory element includes a semiconductor layer arranged on an insulating substrate, a first diffusion layer region and a second diffusion layer region having a conductivity type of P-type, a charge accumulating film for covering a channel region between the first diffusion layer region and the second diffusion layer region and being injected with charges from the channel region, and a gate electrode positioned on a side opposite to the channel region with the charge accumulating film in between.

Description

Semiconductor element and adopt the device of this semiconductor element

Technical field

The present invention relates to semiconductor element and driving method and possess the semiconductor device of the drive circuit of this semiconductor element.In more detail, relate to semiconductor element and driving method and the device that possesses the drive circuit of this semiconductor element, for example display unit, liquid crystal indicator and the receiver of in the insulator of level, accumulating electric charge with trap-charge.

Background technology

Semiconductor memery device uses Semiconductor substrate to form usually.On the other hand, as liquid crystal indicator, use in the device of insulating properties substrate such as glass, on the insulating properties substrate, form semiconductor layer, and use this semiconductor layer to form thin-film transistor (TFT).Constitute signal processing circuit, device drive circuit by this TFT.It is desirable to also memory component is formed on this insulating properties substrate simultaneously with the TFT that constitutes these circuit.

For example, works such as Hung-Tse Chen " SID 05 Digest ", p1152-1155 discloses a kind of non-volatile memory device that has adopted the silicon nitride film that forms on dielectric substrate such as glass substrate in 2005 (non-patent literatures 1).

Figure 28 is the schematic diagram of disclosed semiconductor storage in the expression non-patent literature 1.Among the figure, the 901st, the insulating properties substrate that constitutes by glass, the 902nd, underlayer insulating film, the 911st, silicon semiconductor layer, the 921st, bottom insulating film, the 922nd, electric charge capture dielectric film (silicon nitride film), the 923rd, top dielectric film, the 931st, control gate.The diffusion layer region 912,913 of N type impurity has mixed in the semiconductor layer 911 of the both sides of control gate 931 with being formed with high concentration.In this structure, the gate insulating film that works as memory stores portion has ONO (Oxide-Nitride-Oxide: structure oxide-nitride thing-oxide).The erasable following of stored information carries out, and, applies high electric field between gate electrode 931 and diffusion layer region 912,913 that is, and by Fowler-Nordheim type (FN) tunnel current from silicon semiconductor layer 911 to electric charge capture dielectric film 922 iunjected charges.By the number of the quantity of electric charge accumulated in the electric charge capture dielectric film 922, field effect transistor is that the threshold value of memory component changes.By detecting this changes of threshold, carry out reading of stored information.

Such as in the non-patent literature 1 record, on the insulating properties substrate that constitutes by glass, form in the technology of nonvolatile memory, when writing and wipe, use the FN channel current to carry out electronics with respect to the injection of electric charge capture dielectric film 922 or deviate from.Therefore, existence writes and/or wipe (write, wipe) action needs high-tension problem.In above-mentioned non-patent literature 1, for writing the high voltage that has applied 20V, for clashing the high voltage that applies 40V.Therefore, need be used to be provided for writing, wiping high-tension power supply and even booster circuit, thereby manufacturing cost is raise.

On the other hand, if reduce write, erasing voltage, then FN raceway groove efficient sharply reduces, and write, erasing speed significantly reduces, and therefore, can not obtain enough memory windows.

Such write for compensating, the reduction of erasing speed, the memory component (works such as Szu-I Hsieh " IEEE ELECTRON DEVICE LETTERS ", p272-274, VOL.27, No.4, APRIL 2006 (non-patent literature 2)) of structure shown in Figure 29 is proposed.In this memory component, the assigned position in silicon semiconductor layer 911 is formed with crystal boundary portion 941, and at this position, is formed with projection 942 on the surface of silicon semiconductor layer 911.In this memory component, write, wipe also following carrying out, that is, and by between gate electrode 931 and n type diffused layer zone 912,913, applying high electric field, by FN type channel current electric charge is captured in the dielectric film 922 from silicon semiconductor layer 911 iunjected charges, write thus, erasing move.

Particularly in this memory component, form projection 942 by the surface in silicon semiconductor layer 911, electric field concentrates on the part of this projection 942 thus, promotes the tunnel effect (ト Application ネリ Application グ) of electric charge to the electric charge capture dielectric film 922 at this position.Therefore, compare, can write, wipe by lower voltage with the semiconductor storage of the above-mentioned non-patent literature 1 that does not have projection 942.In addition, in the memory component of Figure 29,, also can write, wipe with low-voltage more by adopting writing, wiping of hot carrier.

In addition, works such as Hung-Tse Chen " IEEE ELECTRON DEVICE LETTERS ", p499-501, VOL.28, No.6, JUNE 2007 (non-patent literature 3)) in, as above-mentioned non-patent literature 2, the assigned position in semiconductor layer 911 forms crystal boundary, and in surface formation projection, and, this memory component is configured to the NAND type, and writes and wipe and use the FN raceway groove to carry out.By diffusion layer region being formed the P type, and make the hot carrier formation efficiency P type device lower usually, suppress readout error and write, be the so-called upset (リ one De デイスタ one Block) of reading than N type device.

But, the projection 942 that the memory component utilization of this Figure 29 produces on the Si semiconductor surface of crystal boundary portion 941.The shape of projection 942 and size are easy to generate deviation because of creating conditions.The memory component of non-patent literature 2 and non-patent literature 3 is owing to the electric field that utilizes in the segment set of projection 942, so device property depends on shape, the size of projection 942 very much.Consequently the characteristic deviation between memory component is big.The very big problem that this becomes the reliability reduction that makes memory is unsuitable for volume production.

Summary of the invention

The present invention constitutes for solving above-mentioned problem, and its purpose is, provides semiconductor element with low cost, high speed writes this semiconductor element and erasing move by carrying out with low voltage, and suppress erasable deterioration, have the storage characteristics that memory window is big and reliability is high thus, and be suitable for volume production.In addition, its purpose also is, semiconductor device, for example display unit, liquid crystal indicator and the receiver of the drive circuit that possesses such semiconductor element is provided.

For solving above-mentioned problem, first aspect present invention provides a kind of semiconductor element, it is characterized in that, possesses: semiconductor layer, and it is located on the dielectric substrate; First diffusion layer region and second diffusion layer region, it is located in the described semiconductor layer, is the P-type conduction type; The electric charge accumulation film, it covers the channel region between first diffusion layer region and second diffusion layer region at least, can be from this channel region iunjected charge; Gate electrode, it is positioned at a side opposite with described channel region across described electric charge accumulation film.

Have in the P type semiconductor element of the present invention of this structure, according to making the result of the test that we carried out when the present invention, can obtain enough memory characteristics, be write diagnostics, erasing characteristic, big window.This also will be with Fig. 4, Figure 22 explanation in the back.On the other hand, know as can be known, be formed at N type semiconductor element on the dielectric substrate and can not obtain gratifying write diagnostics, erasing characteristic, big memory characteristics such as window.This also will be with Fig. 3, Figure 20, Figure 21 explanation in the back.The present invention is based on above-mentioned opinion and makes.

As the nonvolatile memory that is formed on the single crystal semiconductor substrate, to compare with P type device, N type device can carry out high speed motion, and carries out the low-voltage action, therefore, for forming nonvolatile memory, it has been generally acknowledged that to it is desirable to N type device.Under the situation of the nonvolatile memory on the single crystal semiconductor substrate, write by being injected into that electric charge capture dielectric film 922 carries out because of the flow hot carrier electric charge generate of channel current.In this method, compare, can carry out electric charge at a high speed with low-voltage and inject, and also not need the such semi-conductive projection of memory component among Figure 29 with the electric charge injection of having adopted FN type channel current.At this, use N type device usually.In N type device, the electric charge capture dielectric film is carried out electronics inject, relative with it, in P type device, the electric charge capture dielectric film is carried out the hole inject.But when particularly using silicon oxide film as bottom insulating film, to the barrier potential height of the barrier potential in hole comparison electronics, therefore, the electric charge injection efficiency of P type device is low.In addition, in P type device, though form channel current by the hole, the rate of ionization of hole in raceway groove is little, and the formation efficiency of hot carrier is low.In addition be that light element is a boron owing to form the impurity of drain electrode, so the joint steepness of drain electrode end in P type device, slow down, and also low at the hot carrier formation efficiency of drain electrode end.Put from these, the hot carrier injection efficiency of P type device is poor, uses N type device can carry out writing at a high speed under low-voltage, therefore, preferably it.

Think that also N type device is desirable when equally, on dielectric substrate, forming memory component.For example also thinking like this in the non-patent literature 2.

But, result of the test according to us is learnt, when forming memory component on dielectric substrate, the N type memory component that forms on the such dielectric substrate of glass or resin can not obtain gratifying write diagnostics, erasing characteristic, big memory characteristics such as window.On the other hand, when forming on dielectric substrate when thinking originally that memory performance was not so good as the high P type memory component of N type memory component, unexpected the discovery can access enough write diagnostics, erasing characteristic, big memory characteristics such as window.

When forming memory component on single crystal semiconductor substrate, the semi-conductive crystallinity that forms channel region is high, and, form in the operation at devices such as forming film, can use high-temperature technology.For example form the thermal oxidation method that bottom insulating film can use semiconductor substrate surface, and can use highdensity film.Therefore, it is stronger to be formed at the damage that the memory on the monocrystalline substrate brings because of hot carrier, thereby erasable this hot carrier of using of memory is injected.

On the other hand, when forming memory component on the such dielectric substrate of glass or resin, the thermal endurance of substrate is lower than monocrystalline silicon Semiconductor substrate, forms in the operation at device, can not use high-temperature technology.Therefore, the crystallinity of the semiconductor layer of formation channel region is lower, in addition, and the membranous density film that can not use as when forming semiconductor element on the single crystal semiconductor substrate of bottom insulating film.Because these influences, when carrying out the hot carrier same when injecting with being formed at memory on the single crystal semiconductor substrate to being formed at N type memory component on the dielectric substrate, on semiconductor element, produce big damage, thereby can not obtain stable memory characteristics.

In fact, in described non-patent literature 1, also represented, if use the wiring method adopted hot carrier, then only carry out five erasable characteristics significantly deterioration (with reference to non-patent literature 1, Fig. 3. (c)).

Result of the test according to us is learnt, be formed at the unique mechanism of P type memory element performance on the dielectric substrate, thus, can obtain N type memory component can not obtain enough memory characteristics, be write diagnostics, erasing characteristic, big window, and it is few to give the damage of semiconductor element.The present invention is based on such opinion and invents.

Semiconductor element of the present invention can be used as writing of data or wipes so-called like this semiconductor memery device and use.In addition, semiconductor element of the present invention can be used as by the adjusting amount of writing and keeps the semiconductor element use that its write state is regulated threshold value.Therefore,, carry out the electric charge injection to the electric charge accumulation film, can carry out writing or erasing move of high speed to the P type semiconductor element with low voltage, and can suppress erasable deterioration for carrying out the information record according to said structure.Its result can realize the semiconductor element that memory window is big and reliability is high.

Description of drawings

Figure 1A is the summary section of the memory component of expression first embodiment of the invention, and Figure 1B is a plane graph;

Fig. 2 is the figure of wiring method of the memory component of explanation first embodiment of the invention;

Fig. 3 represents that as a reference element is to the figure of the write diagnostics of the memory component of first embodiment of the invention;

Fig. 4 is the figure of write diagnostics of the memory component of expression first embodiment of the invention;

Fig. 5 be the expression first embodiment of the invention memory component write fashionable threshold value displacement and the dependent figure of substrate heating temperature thereof;

Fig. 6 is the dependent figure of the channel width of writing fashionable threshold value displacement of the memory component of expression first embodiment of the invention;

Id-Vg characteristic when Fig. 7 A is the reading of memory component of expression first embodiment of the invention, and with the figure of the Id-Vg characteristic of source electrode-when drain electrode switching is read, be that grid voltage is-situation of 12V;

Id-Vg characteristic when Fig. 7 B is the reading of memory component of expression first embodiment of the invention, and with the figure of the Id-Vg characteristic of source electrode-when drain electrode switching is read, be that grid voltage is-situation of 15V;

Id-Vg characteristic when Fig. 7 C is the reading of memory component of expression first embodiment of the invention, and with the figure of the Id-Vg characteristic of source electrode-when drain electrode switching is read, use be the semiconductor element that has adopted the gate insulating film thicker than the thickness of Fig. 7 A, Fig. 7 B;

Id-Vg characteristic when Fig. 7 D is the reading of memory component of expression first embodiment of the invention, and with the figure of the Id-Vg characteristic of source electrode-when drain electrode switching is read, use be the semiconductor element that has adopted the gate insulating film thicker than the thickness of Fig. 7 C;

Fig. 8 A, 8B are the examples of the write diagnostics under the various channel lengths, channel width, drain voltage of the memory component of first embodiment of the invention;

Fig. 9 is that expression suitably distributes channel length and channel width and drain voltage and writes the fashionable figure that writes displacement respectively;

Figure 10 A be expression with Vgs=-12V ,-15V ,-writing speed of 18V carries out the figure of the branch timing of Fig. 9;

Figure 10 B be the expression with Vgs=-12V ,-15V ,-writing speed of 18V carries out the figure of the branch timing of Fig. 9, is the figure when writing 100 milliseconds;

Figure 10 C be the expression with Vgs=-12V ,-15V ,-writing speed of 18V carries out the figure of the branch timing of Fig. 9, is the figure when writing 1 second;

Figure 11 A is the summary section of the memory component of expression second embodiment of the invention, and Figure 11 B is a plane graph;

Figure 12 is the skeleton diagram of the memory component of expression second embodiment of the invention, is the plane graph when adopting the structure different with Figure 11 B;

Figure 13 is the plane graph of the structure that raises because of leakage current of the electric current of write state;

Figure 14 is the figure of wiring method of the memory component of explanation second embodiment of the invention;

Figure 15 is the figure of method for deleting of the memory component of explanation second embodiment of the invention;

Figure 16 is explanation is used to predict the test of injected electrons diffusion when wiping in the memory component of second embodiment of the invention figure;

Figure 17 A is the example of the Id-Vg curve that obtains of the test from Figure 16, is the situation of channel length 0.45 μ m, and Figure 17 B is the situation of channel length 1.2 μ m, and Figure 17 C is the situation of channel length 1.7 μ m;

Figure 18 is the figure of the result of the test of expression Figure 16;

To be expression carry out erasing time dependence, and the dependent figure of erasing time of threshold value displacement when using the FN electronics to inject to wipe of the threshold value displacement of erasing move to the memory component of second embodiment of the invention to Figure 19;

Figure 20 be the memory component element as a reference of the relative second embodiment of the invention of expression erasing characteristic (wipe preceding, 100 milliseconds wipe the back, wiped the back in 1 second, the Id-Vg characteristic after wiping in 10 seconds) figure;

Figure 21 be the memory component element as a reference of relative second embodiment of the invention erasing characteristic (wipe preceding, 100 milliseconds wipe the back, wiped the back in 1 second, the Id-Vg characteristic after wiping in 10 seconds), be the figure of the erasing characteristic of expression when wiping with the voltage higher than the voltage of Figure 20;

Figure 22 is the erasing characteristic (wipe preceding, 1 millisecond wipe back, 10 milliseconds and wipe back, 100 milliseconds of Id-Vg characteristics after wiping) of the memory component of expression second embodiment of the invention;

Figure 23 be relative second embodiment of the invention memory component element as a reference erasing characteristic and annealing after characteristic;

Figure 24 is the figure of the erasing characteristic after the writing of memory component of expression second embodiment of the invention;

Figure 25 A, 25B are the circuit block diagrams of the liquid crystal indicator of third embodiment of the invention;

Figure 26 is the circuit block diagram of the display unit of four embodiment of the invention;

Figure 27 is the structure chart of the receiver of fifth embodiment of the invention;

Figure 28 is the summary section of the nonvolatile memory of expression prior art;

Figure 29 is the summary section of the nonvolatile memory of expression prior art.

Description of symbols

1 memory component, 6 display unit, 7 receivers

101 dielectric substrate, 103 interlayer dielectrics, 111 tagmas

112 diffusion layer regions, 113 diffusion layer regions, 114 body contact areas

121 bottom insulating films, 122 electric charge accumulation dielectric films (silicon nitride film)

The terminal that 123 top dielectric films, 131 gate electrodes 151 are connected with gate electrode

152 terminals that are connected with diffusion layer region 112

153 terminals that are connected with diffusion layer region 113

154 terminals that are connected with the tagma

The gate insulating film that 161 semiconductor layers 162 have the electric charge accumulation function

171 injected holes 172 inject electronics 180 DC power supply

181 first circuit, 182 second circuits, 183 tertiary circuits

184 the 4th circuit, 190 DC power supply 191 the 5th circuit

192 the 6th circuit 193 the 7th circuit 194 the 8th circuit

511 pixel electrodes, 515 opposite electrodes, 522 voltage generating circuits

611 storage part 612DA converters, 614 output circuits

711 display unit (display panels), 712 tuners, 714 control parts

Embodiment

In the semiconductor element with first feature of the present invention, the pyroconductivity of above-mentioned dielectric substrate can be 0.1～9W/mK.More preferably above-mentioned dielectric substrate is that pyroconductivity is the glass substrate of 0.5～2W/mK.Perhaps above-mentioned dielectric substrate can be the resin substrates of 0.1～2W/mK for pyroconductivity.

In addition, the electric charge that is injected into described electric charge accumulation film from above-mentioned channel region is, when first diffusion zone flows to second diffusion zone by above-mentioned channel region, on whole of the auxiliary channel region of the heat that has been subjected to producing, produce charge carrier and the electric charge that obtains at electric current by above-mentioned electric current.

In addition, the electric charge that injects above-mentioned electric charge accumulation film from above-mentioned channel region is, at electric current when first diffusion layer region flows to second diffusion zone by above-mentioned channel region, it is auxiliary to be subjected to the heat that produced by above-mentioned electric current, the electric charge that is injected in the mode that roughly is symmetrically distributed in above-mentioned electric charge accumulation film.

In addition, the electric charge that injects above-mentioned electric charge accumulation film from above-mentioned channel region is, at electric current when first diffusion layer region flows to second diffusion zone by above-mentioned channel region, the heat that is subjected to above-mentioned electric current generation is auxiliary, at least by near the above-mentioned electric charge accumulation film trapped charges first diffusion layer region.

In addition, the electric charge that is injected into above-mentioned electric charge accumulation film from above-mentioned channel region is characterised in that, at electric current when first diffusion layer region flows to second diffusion zone by above-mentioned channel region, the heat that is subjected to being produced by above-mentioned electric current is assisted and is injected, and under the state that has injected above-mentioned electric charge, the difference of threshold value when first diffusion layer region has been applied reference potential and second diffusion layer region applied negative voltage and the threshold value when second diffusion layer region applied reference potential and first diffusion layer region applied negative potential is below 10%.

According to having above-mentioned each semiconductor element that constitutes, the electric charge accumulation film being carried out the hole when injecting, between diffusion layer region, flow through electric current for carrying out the information record, heat takes place thus, utilize this heat can realize efficiently the few hole of damage of elements is injected.Thus, the window edge of memory (ウイ Application De ウマ one ジ Application) is widened, and obtains the high semiconductor element of reliability, even and particularly repeat the erasable of memory, the deterioration that damage causes is also little, and guarantees wide window edge.This high performance semiconductor element can use dielectric substrate to obtain with the low cost manufacturing.

In the semiconductor element with first feature of the present invention, at above-mentioned channel region, the upper surface of above-mentioned semiconductor layer can be general planar.According to this semiconductor element, owing to need not make complicated step such as projection on the surface of semiconductor layer, so can suppress manufacturing cost, in addition, because raceway groove top be general planar and be mild shape, so interelement form variations is little, but the characteristic deviation between suppression element.Therefore, obtain being suitable for the semiconductor element of volume production.

In the semiconductor element with first feature of the present invention, above-mentioned semiconductor layer can be formed on the above-mentioned dielectric substrate by island.In addition, can form interlayer dielectric on the above-mentioned semiconductor layer and on the above-mentioned gate electrode.In addition, the local at least of above-mentioned interlayer dielectric is made of resin.In addition, the thickness of above-mentioned semiconductor layer can be 30nm～150nm.In addition, the channel width of above-mentioned channel region can be 0.5 μ m～100 μ m.In addition, the channel width of above-mentioned channel region can be 2 μ m～20 μ m.In addition, the channel length of above-mentioned channel region can be 0.1 μ m～3.4 μ m.In addition, the channel length of channel region can be 0.1 μ m～2.4 μ m.In addition, the channel length of above-mentioned channel region can be 0.1 μ m～0.9 μ m.In addition, above-mentioned electric charge accumulation film preferably has the stepped construction that is made of first dielectric film, the electric charge accumulation film with electric charge accumulation ability and second dielectric film at least.The electric charge accumulation film that particularly preferably has above-mentioned electric charge accumulation ability is nitride film or high dielectric film.

According to semiconductor element,, can obtain the semiconductor element of best action as semiconductor element of the present invention with such feature.

Semiconductor element with first feature of the present invention is characterised in that above-mentioned semiconductor layer also possesses the contact area for N type conduction type, and above-mentioned contact area and control terminal join.In addition, it is characterized in that, between above-mentioned contact area and first diffusion zone and second diffusion zone, be formed with the impurity concentration semiconductor layer zone lower than the impurity concentration of above-mentioned contact area.In addition, on the semiconductor layer zone of above-mentioned low concentration, has above-mentioned gate electrode.

According to this semiconductor element, by control terminal be the contacting of the body contact area of N type conduction type, contact resistance between the two can reduce, and can obtain ohm and connect, and therefore, can improve the controlled of bulk potential, suppresses the action deviation.

In addition, owing to have low concentration region between contact area and the diffusion layer region, particularly on this low concentration region, have gate electrode, thereby when having applied reverse voltage between contact area and diffusion layer region, what flow through between the two is suppressed in conjunction with leaking with doing one's utmost.

In addition, in the semiconductor element with second feature of the present invention, also possesses display unit on the above-mentioned dielectric substrate.

According to said structure, owing on the panel substrate of display unit, be formed with semiconductor element of the present invention, so can cut down the cost of outer tape member self, the installation cost of outer tape member.In addition, because the automation of regulating is easy, so can cut down the inspection cost.In addition, because the process number of the simple structure of its gate insulating film of semiconductor element of the present invention and necessity is few, so favourable to cost cutting.

In addition, semiconductor element with the 3rd feature of the present invention is a liquid crystal indicator, it possesses liquid crystal indicator and liquid crystal display drive circuit on the panel substrate, wherein, described liquid crystal indicator has: the scan line of rectangular configuration and holding wire, with the zone that is surrounded by described scan line and holding wire is a pixel and the drive circuit that optionally drives the pixel electrode corresponding with this pixel, is located at the liquid crystal between described pixel electrode and the opposed with it opposite electrode; Described liquid crystal display drive circuit has: input digit information and the voltage that will be determined by described digital information are to the voltage follower circuit of described opposite electrode output, with the DA converter of digital tone data conversion for the tonal signaling of simulation, the memory circuit that possesses semiconductor element, the correlation data of the voltage of described digital tone data of this semiconductor element store predetermined and simulation tonal signaling; Described semiconductor element is the semiconductor element of record in the claim 1.

According to liquid crystal indicator,, therefore, can cut down the cost of outer tape member self, the installation cost of outer tape member because the semiconductor element with first feature of the present invention is formed on the panel substrate of liquid crystal indicator with said structure.In addition, because the automation of regulating is easy, so can cut down the inspection cost.In addition, because the process number of the simple structure of its gate insulating film of semiconductor storage of the present invention and necessity is few, so favourable to cost cutting.

In addition, semiconductor element with the 4th feature of the present invention is a receiver, it possesses display unit and memory circuit, described memory circuit has: the receiving circuit that receives picture signal, to be supplied with the picture signal circuit of display unit by the picture signal that described receiving circuit receives, storage generates the semiconductor element of described picture signal desired data; Described semiconductor element is the semiconductor element of record in the claim 1.

According to receiver, be formed with the display unit with semiconductor storage of first feature of the present invention owing to possess, so can realize H.D receiver with low cost with said structure.

In addition, the semiconductor element with the 5th feature of the present invention also possesses the heater that above-mentioned dielectric substrate is heated.

According to semiconductor element, by the heating dielectric substrate, can promote the hole to inject, and can suppress the element deterioration that implant damage causes, and can carry out the hole at high speed and inject with said structure.

Semiconductor device with the 6th feature of the present invention, it possesses: semiconductor element; First voltage applying circuit that is connected with first diffusion layer region via first switch element; Second voltage applying circuit that is connected with second diffusion layer region via the second switch element; Apply circuit via the 3rd switch element with the tertiary voltage that above-mentioned gate electrode is connected; Wherein, above-mentioned semiconductor element possesses: semiconductor layer, and it is located on the dielectric substrate; First diffusion layer region and second diffusion layer region, it is located in the above-mentioned semiconductor layer, is the conduction type of P type; The electric charge accumulation film, it covers interior described first diffusion layer region of described semiconductor layer and the channel region between second diffusion layer region at least, can be from this channel region iunjected charge; Gate electrode, it is positioned at a side opposite with above-mentioned channel region across above-mentioned electric charge accumulation film.

Therefore, according to semiconductor device with said structure, can provide a kind of and carry out the electric charge injection and the P type semiconductor element is carried out the semiconductor device of writing of high speed or erasing move to the electric charge accumulation film, and can suppress erasable deterioration with low voltage for carrying out the information record.Consequently, can drive the semiconductor element that memory window is big and reliability is high.

In the semiconductor device with the 6th feature of the present invention, second voltage applying circuit and tertiary voltage apply circuit can export the low voltage of voltage than the output of first voltage applying circuit.

According to semiconductor device, can realize producing heat and having utilized and the high efficiency of heat to have been injected by the few hole of damage of elements by between diffusion layer region, flowing through electric current with said structure.By this operation, can carry out the hole to the electric charge accumulation film and inject and the information of carrying out record.Thus, obtain the semiconductor element that window edge is wide and reliability is high of memory, even particularly repeat the erasable of memory, the deterioration that damage causes is also little, can guarantee wide window edge.This high performance semiconductor device can use dielectric substrate to obtain with the low cost manufacturing.

In addition, in the semiconductor device with the 6th feature of the present invention, tertiary voltage applies circuit can export the low voltage of voltage than the output of second voltage applying circuit.

According to semiconductor device with said structure, owing to relax the transverse direction electric field of diffusion layer region end by the electric field of gate electrode, so the hot carrier formation efficiency that the impact ionization in the diffusion layer region end causes reduces, the damage that gives the interface in gate insulating film, gate insulating film and tagma reduces.

In addition, the semiconductor device with the 7th feature of the present invention, it possesses: semiconductor element; First voltage applying circuit that is connected with first diffusion layer region via first switch element; Second voltage applying circuit that is connected with second diffusion layer region via the second switch element; Apply circuit via the 3rd switch element with the tertiary voltage that above-mentioned gate electrode is connected; The 4th voltage applying circuit that is connected with above-mentioned tagma via the 4th switch element; Wherein, above-mentioned semiconductor element possesses: semiconductor layer, and it is located on the dielectric substrate; First diffusion layer region and second diffusion layer region, it is located in the above-mentioned semiconductor layer, is the conduction type of P type; The tagma, it wraps first diffusion layer region stated in the semiconductor layer and the channel region between second diffusion layer region, electric charge accumulation film at least; It covers above-mentioned channel region, can be from this channel region iunjected charge; Gate electrode, it is positioned at a side opposite with above-mentioned channel region across above-mentioned electric charge accumulation film.

According to semiconductor device, carry out the electric charge injection for carrying out the information record to the electric charge accumulation film, and can carry out writing or erasing move of high speed to the P type semiconductor element, and can suppress erasable deterioration with low voltage with said structure.Consequently, can realize the semiconductor device that memory window is big and reliability is high.In addition, semiconductor device of the present invention is by the adjusting amount of writing and keep this write state, can realize having regulated the semiconductor device of threshold value.In addition, by the control volume current potential, can realize erasing move at a high speed with low voltage.In addition, wipe owing to inject by electronics, thus gate insulating film given and the interface equivalent damage is little, thus the deterioration of device performance is few.

In the semiconductor device with the 7th feature of the present invention, it is desirable to, above-mentioned tertiary voltage applies circuit and the output of the 4th voltage applying circuit high voltage of voltage than the output of first voltage applying circuit.

According to semiconductor device with this structure because the part of the charge carrier that produces when wiping also discharges from the body contact zone, so the controlled of bulk potential increase, thereby can reduce action deviation between device.

In addition, in the semiconductor device with the 7th feature of the present invention, it is desirable to the roughly the same voltage of voltage of the output of second voltage applying circuit and the output of first voltage applying circuit.

According to the semiconductor device with said structure, a part of electronics that generates in the charge carrier of high-octane charge carrier and this generation is attracted by the electromotive force of gate electrode, and is injected in the gate insulating film, wipes.

In addition, in the semiconductor element device with the 7th feature of the present invention, it is desirable to, above-mentioned tertiary voltage applies the voltage high voltage of circuit output than above-mentioned the 4th voltage applying circuit output.

According to semiconductor device, can carry out more wiping of high speed with this structure.

In addition, according to the semiconductor element device with the 7th feature of the present invention, has the decoding circuit of optionally controlling above-mentioned switch element.Thus, can suitably control timing, voltage application time, the voltage that voltage applies and apply order.

In addition, according to other viewpoint, the present invention is the driving method with semiconductor element of the 8th feature, uses semiconductor element, as the operation of storage for information about, second diffusion zone and above-mentioned gate electrode are applied with respect to the voltage of the reference voltage that puts on first diffusion layer region for bearing, make above-mentioned channel region produce electric current, and make its heating, thus the hole is injected above-mentioned electric charge accumulation film, wherein, above-mentioned semiconductor element has: semiconductor layer, and it is located on the dielectric substrate; First diffusion layer region and second diffusion layer region, it is located in the above-mentioned semiconductor layer, is the conduction type of P type; The tagma, it wraps first diffusion layer region stated in the semiconductor layer and the channel region between second diffusion layer region at least; The electric charge accumulation film, it covers above-mentioned channel region, can be from this channel region iunjected charge; Gate electrode, it is positioned at a side opposite with above-mentioned tagma across above-mentioned electric charge accumulation film.

By above-mentioned driving method, can write in hole injector grid dielectric film from whole of channel region.By writing like this, can obtain having enough write diagnostics, erasing characteristic and big memory window.

In addition, in the driving method of above-mentioned semiconductor element of the present invention, it is desirable to, as the operation of storage for information about, in execution mode, the absolute value of negative voltage that puts on above-mentioned gate electrode is bigger than the absolute value of the voltage of bearing that puts on second diffusion layer region.

Thus, can attract to generate electronics effectively, can will write high speed by the electric field of gate electrode.

In addition, in the driving method of above-mentioned semiconductor element of the present invention, it is desirable to, as operation about information stores, in execution mode, be positive voltage, electronics is injected above-mentioned electric charge accumulation film by applying with respect to the reference voltage that puts on first diffusion layer region above-mentioned gate electrode and above-mentioned tagma.

Thus, generate high-octane charge carrier, and its a part of charge carrier is drawn in gate insulating film and injection, wipe.

In addition, in the driving method of above-mentioned semiconductor element of the present invention, it is desirable to, as the operation of storage for information about, applying with respect to the current potential in the reference voltage that puts on the first p type diffused layer zone and the second p type diffused layer zone to above-mentioned gate electrode and above-mentioned tagma is the positive voltage of roughly the same current potential.Thus, generate high-octane charge carrier, and its a part of charge carrier is drawn in gate insulating film and injection, wipe.

In addition, in the driving method of above-mentioned semiconductor element of the present invention, it is desirable to, in the operation of electronics being injected above-mentioned electric charge accumulation film, the positive voltage height that the positive voltage ratio that applies to above-mentioned gate electrode applies to above-mentioned tagma.Thus, can carry out more wiping of high speed.

In addition, in the driving method of above-mentioned semiconductor element of the present invention, it is desirable to, the negative voltage that second diffusion layer region is applied for-6V～-14V, the negative voltage that above-mentioned gate electrode is applied is the big voltage of absolute value.Particularly the negative voltage that applies to gate electrode can for-6V～-18V.

Thus, generation has the hole of hole from the required sufficient energy of whole injector grid dielectric film of channel region, writes.

In addition, in the driving method of above-mentioned semiconductor element of the present invention, it is desirable to, the positive voltage that above-mentioned tagma is applied is 6～15V, and the positive voltage that above-mentioned gate electrode is applied is high voltage.Particularly the negative voltage that applies to gate electrode can be 6V～30V.

In the semiconductor device with the 9th feature of the present invention, it is characterized in that on above-mentioned dielectric substrate, also possessing display unit.

According to said structure, owing on the panel substrate of display unit, be formed with semiconductor element of the present invention, so can cut down the cost of outer tape member self, the installation cost of outer tape member.In addition, because the automation of regulating is easy, so can cut down the inspection cost.In addition, because the simple structure of the gate insulating film of semiconductor element of the present invention and required operation are few, so be favourable for cost cutting.

In addition, semiconductor device with the tenth feature of the present invention is a liquid crystal indicator, it is characterized in that, on the panel substrate, possesses liquid crystal indicator, this liquid crystal indicator is with scan line and the rectangular configuration of holding wire, and possessing with the zone that is surrounded by described scan line and holding wire is a pixel and the drive circuit that optionally drives the pixel electrode corresponding with this pixel, and be provided with liquid crystal between pixel electrodes and opposed with it opposite electrode, possess on the panel substrate of above-mentioned liquid crystal indicator: input digit information and the voltage that will be determined by above-mentioned digital information are to the voltage follower circuit of above-mentioned opposite electrode output, with the DA converter of digital tone data conversion for the simulation tonal signaling, store the above-mentioned semiconductor device of the above-mentioned digital tone data and the data of the correlation of the voltage of simulation tonal signaling.

According to said structure, owing to the semiconductor device with the 6th or the 7th feature of the present invention forms on the panel substrate of liquid crystal indicator, so can cut down the cost of outer tape member self, the installation cost of outer tape member.In addition, because the automation of regulating is easy, so can cut down the inspection cost.In addition, because the simple structure of the gate insulating film of the semiconductor storage of this aspect and required process number are few, so be favourable to cost cutting.

In addition, the semiconductor device with the 11 feature of this aspect is a receiver, it is characterized in that, comprise display unit, on the panel substrate of above-mentioned display unit, possess: receive picture signal receiving circuit, will supply with the picture signal circuit of display unit, the above-mentioned semiconductor device that storage generates the required data of above-mentioned picture signal by the picture signal that above-mentioned receiving circuit receives.

According to said structure, be formed with the display unit with semiconductor device of the 6th or the 7th feature of the present invention owing to possess, so can realize H.D receiver with low cost.

In addition, the semiconductor device with the 12 feature of the present invention is characterised in that also possess the heater of the above-mentioned dielectric substrate of heating.

According to said structure, by the heating dielectric substrate, can promote the element deterioration that the hole is injected and the inhibition implant damage causes, and can carry out the hole at high speed and inject.

As mentioned above, according to the semiconductor element with first feature of the present invention, two information stores states of this that read current is little, read current is big inject by hole injection, electronics respectively to be realized.The former hole inject use be, make element heating by flowing through electric current, utilize this heat to promote the effect that hole is injected, therefore, it is few to have the damage deterioration, even locally produce damage and also can make its recovery by the annealing effect that is caused by heat.In addition, though the electronics few by damage injects realization, owing to be the big information stores state of read current, is window edge so can increase the difference of two information stores states, particularly repeating also can to obtain the semiconductor memory component that deterioration is little and reliability is high when erasable.

In addition, according to the semiconductor element with second feature of the present invention, owing to semiconductor element of the present invention forms on the panel substrate of display unit, so can cut down the cost of outer tape member self, the installation cost of outer tape member.In addition, because the automation of regulating is easy, so can cut down the inspection cost.In addition, because the process number of the simple structure of its gate insulating film of semiconductor element of the present invention and necessity is few, so favourable to cost cutting.

In addition, according to the semiconductor element with the 3rd feature of the present invention, owing to semiconductor element of the present invention forms on the panel substrate of display unit, so can cut down the cost of outer tape member self, the installation cost of outer tape member.In addition, because the automation of regulating is easy, so can cut down the inspection cost.In addition, because the process number of the simple structure of its gate insulating film of semiconductor element of the present invention and necessity is few, so favourable to cost cutting.

In addition, according to the semiconductor element with the 4th feature of the present invention, owing to possess the display unit that is formed with semiconductor element of the present invention, so can realize H.D receiver with low cost.

In addition, according to the semiconductor element with the 5th feature of the present invention, realize more at a high speed or more the hole under the low-voltage inject.

(first execution mode)

In the following description, relevant with information stores two states, so-called write state and erase status are as giving a definition.

Will be in having the gate insulating film of accumulating the electric charge function, the situation of mainly accumulating most of charge carrier of the conduction type that first and second diffusion layer region is arranged is defined as write state.And, be defined as erase status with mainly accumulating to have with the situation of the charge carrier of this conductivity type opposite type or accumulate situation few on the electric charge actual effect.Comprise that hole and electronics are all accumulated and electromotive force is each other offset, accumulate the few situation of electric charge on the actual effect.

Semiconductor element of the present invention is that first and second diffusion layer region is the P channel-type semiconductor element of P type.Under this situation, will have the state of mainly accumulating the hole in the gate insulating film of the function of accumulating electric charge and be defined as write state, with the state of main accumulated electrons and accumulate state few on the electric charge actual effect and be defined as erase status.

Use Fig. 1 that first embodiment of the invention is described.Figure 1A is the A-B line generalized section of Figure 1B, and Figure 1B is a floor map.In the semiconductor element of first execution mode (below be also referred to as memory component) 1, on the dielectric substrate 101 that constitutes by glass substrate or resin substrates, form underlayer insulating film 102, on underlayer insulating film 102, further form semiconductor layer 161.On semiconductor layer 161,, form two

diffusion layer regions

112 and 113 of P-type conduction type according to mode across at least a portion in tagma 111.They work as source region and drain region.

Tagma 111 is N type conduction type or intrinsic (イ Application トリ Application シ Star Network).In the source region and drain region when working, form channel region 110 at the superficial layer of semiconductor layer 161.Form this channel region 110 semiconductor layer above become smooth.At this, smooth be meant when making semiconductor layer 161, do not form wittingly concavo-convex.Therefore, among the present invention, the top smooth flatness degree that can form that is meant of semiconductor layer by making common semiconductor layer.For example when making semiconductor layer, be meant the surface of amorphous semiconductor layer by vapour deposition method.In addition, be meant the flatness that obtains when laser annealing forms CG silicon by the amorphous semiconductor layer is carried out.Concavo-convex littler than the semiconductor layer thickness state of preferred semiconductor layer for example, more preferably concavo-convex size is below the 10nm.The present invention is meant such flatness.Have a mind to form its production of concavo-convex semiconductor layer and reduce, also can cause interelement characteristic deviation, this is undesirable.

Such semiconductor layer 161 forms the island of the size that can form memory component.Fig. 1 represents the example to each memory component separating semiconductor layer 161, but according to circumstances, also can be the mode of the memory component that makes a side in the diffusion layer region 112,113 or its two sides common adjacent.In addition, also can contain at least a portion of memory component and peripheral circuit usefulness TFT at an island semiconductor layer 161.

Stacked gate insulating film 162 on semiconductor layer 161, and stacked in order thereon gate electrode 131 with function of accumulating electric charge.The near interface of tagma 111 and gate insulating film 162 becomes the zone that forms inversion layer at transistor during for on-state, promptly so-called channel region 110.It constitutes the semiconductor storage of first embodiment of the invention, changes the electric current that flows through between two diffusion layer regions by accumulating in the number of the electric charge on the gate insulating film.Particularly, because the magnitude of current is little under write state, the magnitude of current is big under erase status, therefore, can read store status by the number of this magnitude of current.

Interlayer insulating film 103 is formed at the top at the memory component of this structure, makes its overlaying memory element and entire substrate.

Dielectric substrate 101 is made of glass substrate or resin substrates, if transparent, then can be used as display uses such as transmissive type liquid crystal panel, therefore, preferably uses transparent glass substrate and transparent resin substrates.In addition, when having used resin substrates, make substrate have flexible and lightweight easily, and improve resistance to impact, thus preferably it.For the thickness of dielectric substrate 101, be generally about 1mm during for glass substrate at it.And, on glass substrate, made after the semiconductor element of the present invention by semiconductor technology, for making display unit lightweight, slimming, substrate back can be ground and cut about several 100 μ m.Under the situation that is resin substrates, equally can be after having made semiconductor element of the present invention on the substrate, substrate back ground cut about several 100 μ m.

Particularly under the good situation of the thermal insulation of dielectric substrate 101, as described later, have following advantage, that is, write and fashionablely can the temperature of semiconductor element be risen effectively, can improve writing speed by this hot effect.Therefore,, on silicon substrate, formed its fine heat radiation property of substrate of insulating barrier as the SOI substrate, therefore, inapplicable to the substrate that is used for semiconductor element of the present invention.

When considering the semiconductor element on the common silicon substrate, also according to its crystalline state and difference, but, the value of the higher pyroconductivity about 160W/mK is arranged as typical value as the pyroconductivity of the silicon metal of substrate.Therefore, even produce heat during the overcurrent of semiconductor element upper reaches, this heat promptly is diffused in the Semiconductor substrate.

On the other hand, as first execution mode, when the material that thermal insulation is high used as substrate 101, the heat that produces in semiconductor element was difficult to spread in downwards the substrate.When carrying out write activity, as described later, the current direction semiconductor element, the Joule heat that produce this moment is difficult to spread downwards because of the thermal insulation of substrate 101, and consequently the temperature of semiconductor element rises effectively.

Therefore, the thermal insulation of the dielectric substrate of using among the present invention 101 is high more to be compared with silicon substrate more for preferred, and as long as pyroconductivity is lower than it.But, as the thermal insulation dielectric substrate better, can use glass substrate, resin substrates in the reality than silicon substrate.

Its maximum feature of the memory component of first execution mode is, has to write the character that efficient improves when device temperature is high, that is, the thermal insulation height of dielectric substrate 101 can bring height to write efficient.

For example, when using for example quartzy substrate, can be set at the pyroconductivity value 8～9W/mK lower than Semiconductor substrate as dielectric substrate 101.

In addition, when using glass substrate, have lower pyroconductivity, get the following value of 2W/mK, get pyroconductivity value about 0.5～1.5W/mK as representative value, therefore, substrate 101 can have high thermal insulation.

In addition, as resin substrates, for example resins such as polycarbonate resin, polysulfone resin, polymethylpentene resin, polyarylate resin, polyimide resin, phenol aldehyde resin have higher thermal endurance, can more effectively use.Though the pyroconductivity of these resins is according to material and density and difference, but provide on the market and have the low following pyroconductivity value of 2W/mK that reaches, the lower resin that reaches the pyroconductivity value about 0.1～0.2W/mK obtains the pyroconductivity lower than glass substrate.Therefore, make the heat that produces in the semiconductor more be difficult to deviate from, and bring the high efficient that writes.

Above-mentioned pyroconductivity can be measured by for example laser flash method (レ one ザ Off ラ Star シユ method).Laser flash method is open in TOHKEMY 2003-065982 communique etc.

The pyroconductivity of substrate is low value more, can suppress the diffusion of the heat of generation in the semiconductor element more, bring the high efficient that writes, as long as, select suitable material to get final product according to the specification of each rerum natura that backing material had, the semiconductor element that will form and purposes etc.For example, then as mentioned above,,, the memory component and the display of first execution mode can be produced on the same substrate so its display such as liquid crystal panel as transmission-type can be used because substrate is transparent if use glass substrate.The pyroconductivity of glass substrate is very low, and therefore, it also has can access the high advantage that writes efficient, and has with using Semiconductor substrate and compare, and can make the advantage of semiconductor element with low cost.When using resin substrates, its thermal conductivity ratio glass substrate is lower usually, and compares with glass substrate, and is strong aspect shock-resistant.Particularly if use polycarbonate resin and polyarylate resin, then transmitance is good, therefore, can be suitable for display.

The substrate that as above has low thermal conductivity is like that being write the promotion that writes efficient that the fashionable performance effectively torrid zone is come.About this hot auxiliaring effect, the back is described in detail again.

Underlayer insulating film 102 may not need.But, when using glass substrate,, preferably use silicon oxide film, silicon oxynitride film, silicon nitride film or their stacked film as underlayer insulating film 102 as dielectric substrate 101.Under this situation, underlayer insulating film 102 becomes the barrier layer, can prevent to be polluted by the semiconductor element that the impurity from the glass substrate diffusion will be formed on the glass substrate.Usually, though the pyroconductivity of silicon nitride film is according to its structure and different, but because it has the pyroconductivity higher than glass, so when using silicon nitride film as underlayer insulating film a part of, be made as preferably that for example 1 μ m is with interior thickness, it can not cause big infringement to the thermal insulation that substrate possessed.In addition, the superiors of underlayer insulating film use the low film of pyroconductivity such as silicon oxide film effective especially at least.

Semiconductor layer 161 for example can use amorphous silicon, polysilicon, monocrystalline silicon.Preferably crystal grain boundary is increased, when using (Continuous Grain: continuous crystallisation) during silicon, can obtain effect of the present invention significantly near the such CG of single crystals characteristic by amorphous silicon being carried out laser annealing.

The semiconductor element of first execution mode uses the technology of lower temperature to form, and compares with the situation of using high-temperature technology to form element on monocrystalline substrate, and the interface state of the crystalline state of semiconductor layer, semiconductor layer and gate insulating film is bad.Therefore, the degree of excursion in raceway groove is lower, becomes the higher element of channel resistance.For example, in the element of first execution mode, state has in the early stage promptly been made the charge carrier degree of excursion that do not carry out after the element in write-once action or raceway groove erasing move, that be in the charge neutrality state and be determined as 60～120cm under linear areas, normal temperature ²Value about/Vs.Cross low and channel resistance when too high when degree of excursion, write the fashionable magnitude of current and reduce, Joule heat is difficult to produce, and therefore, preferred charge carrier degree of excursion is 30cm ²More than/the Vs.On this point, for the structure of semiconductor layer, with the amorphous phase ratio, polycrystalline and monocrystalline are more suitable.

Except that these semiconductors, also can use semiconductor material such as SiGe, germanium.Preferred 30nm～the 150nm of the thickness of semiconductor layer 161.During deficiency 30nm, be difficult to guarantee the uniformity of thickness, when surpassing 150nm, the semiconductor layer during transistor action under the raceway groove can not exhaust sometimes fully, thus characteristic degradation.But, in the action of memory component of the present invention owing to do not need exhausting fully, so when only on this semiconductor layer 161, forming memory component, also can for more than the 150nm, several μ m.

In first execution mode, because two diffusion layer regions 112,113 are for the P-type conduction type, so element is the P channel-type.Among the present invention, as described later by element being made as the P channel-type, write and erasing move becomes at a high speed, therefore, memory window increases, and can have good retention performance.Tagma 111 preferred N type conduction type or intrinsics.

The gate insulating film 162 that forms on the channel region 110 in the semiconductor layer 161 has the function of accumulating electric charge.Preferred 20nm～the 150nm of its thickness.During deficiency 20nm, be difficult to guarantee the uniformity of thickness, and withstand voltage insufficient.In addition, when above above 150nm, it is very high that threshold value becomes, and making current significantly reduces.

Gate insulating film 162, more particularly have the bottom insulating film 121 that constituted by silicon oxide film and the structure of top dielectric film 123 clampings as the silicon nitride film 122 of electric charge accumulation dielectric film.

Have under the situation about comprising at gate insulating film 162 as the three-layer structure of the silicon nitride film 122 of electric charge accumulation dielectric film, underlayer insulating film 121 and top layer insulating film 123 hinder the flow of charge outside that keeps in the silicon nitride film 122, therefore, the advantage that has the retention performance raising of electric charge.

Particularly using under glass substrate or the situation of resin substrates as dielectric substrate 101, its thermal endurance is lower than Semiconductor substrate, when making semiconductor element, can not use the high-temperature technology identical with the situation of using Semiconductor substrate.Therefore, the film of bottom insulating film 121 is formed the degree that the film that can not form high density reaches the situation of formation semiconductor element on Semiconductor substrate.Therefore, compare, be easy to generate defective with highdensity film.Such defective may become the leakage path that keeps electric charge.

On the other hand, as the electric charge accumulation zone that is used for information stores, when adopting the so-called floating grid that is made of electric conductors such as polysilicons to construct replacing electric charge accumulation dielectric film 122, electric charge accumulation is on electric conductor.Therefore,, keep electric charge to flow out successively since then even when a part produces charge leakage path on bottom insulating film, finally can not stored information.Therefore, bottom insulating film need not form and can produce leakage path.

On this point,,, preferably use electric charge accumulation dielectric films 122 such as silicon nitride film as the electric charge accumulation zone as first execution mode.By in dielectric film, capturing and keeping electric charge, prevent to keep electric charge moving in film, on the contrary, even defective enters the local of bottom insulating film 121 and produces charge leakage path, near the electric charge that also just exists defective flows out, and most of electric charge stays in the electric charge accumulation dielectric film.Therefore, obtain the memory component that anti-defective is strong, reliability is high.

In the situation of first execution mode,, bottom insulating film 121 is made as 5nm～20nm, silicon nitride film 122 are made as 10nm～50nm, top dielectric film 123 is made as 5nm～50nm etc. as preferred thickness example.When making bottom insulating film 121 or top dielectric film 123 thinner than 5nm, prevent that the electric charge self charge from keeping the effect of the outflow of film to reduce, the retention time may shorten.In addition, when the gate insulating film that is made of these films 162 was thick, the grid electric field weakened the effect that raceway groove causes, and therefore, writing speed slows down.In addition, particularly about bottom insulating film 121, owing to inject charge carrier by this film, when thickness was thick, the electric charge injection efficiency reduced.In addition, owing to increase, the influence of raceway groove 110 is reduced relatively, memory window is reduced so accumulate electric charge as the distance of the silicon nitride film 122 of electric charge accumulation film and raceway groove 110.That is, when gate insulating film 162, particularly bottom insulating film 121 were blocked up, window edge reduced.Therefore, above-mentioned thickness is preferred.

As preferred thickness, bottom insulating film 121 is made as 5nm～20nm, silicon nitride film 122 are made as 10nm～30nm, top dielectric film 123 is made as 5nm～20nm etc.Make gate insulating film 162 thinner by each thickness of such attenuate, after in the write activity of explanation, can strengthen the grid electric field, make it to the channel region effect, particularly the transverse direction electric field of drain electrode end can be relaxed.Thus, can be suppressed at with doing one's utmost and write that the high-octane charge carrier of fashionable generation reaches because transistorized snowslide etc. causes the degree of damage to semiconductor element.Therefore, the reliability height of memory component.

In addition,, replace silicon nitride film 122, also can use the film that in high dielectric film such as hafnium oxide and zirconia or silicon oxide film, contains electric conductor grain or nitride grain etc. as the electric charge accumulation film.In addition, on the other hand, gate insulating film 162 can be the monofilm of silicon nitride film, it also can be this two membranes of silicon oxide film and silicon nitride film, but from preventing that electric charge from flowing out and realize long-term maintenance aspect, the more preferably stacked film of the stacked film of trilamellar membrane as described above or its more multi-layered film from silicon nitride film.

On gate insulating film 162, be formed with gate electrode 131.The material of gate electrode 131 can be semiconductors such as metals such as W, Ta, Al, TaN, TaAlN, amorphous silicon, polysilicon, but is not limited thereto.

The interlayer dielectric 103 representational stacked films that are to use silicon oxide film, silicon oxide film and silicon nitride film, but also can be other dielectric film.This dielectric film 103 realizes being suppressed at the effect of the heat-barrier material of the diffusion of the heat of generation in the semiconductor element, helps heat described later auxiliary.Particularly preferably be, be made as the low resin material of pyroconductivity, can further improve thermal insulation, and can realize it easily by a part with interlayer dielectric.In addition, omitted the diagram of interlayer dielectric 103 among Figure 1B.

The memory component of first embodiment of the invention can form according to the order that forms common thin-film transistor (TFT).That is, silicon semiconductor layer 161, bottom insulating film 121, silicon nitride film 122, top dielectric film 123 can form by plasma CVD method.

But the impurity that will give the P-type conduction type by ion implantation or solid phase diffusion method imports the zone that should become two diffusion layer regions 112 and 113.Afterwards, suitably carry out annealing in process, form diffusion layer region 112,113.As the impurity that gives the P-type conduction type, for example can use boron or aluminium etc., but use boron among the present invention.In addition, impurity concentration when using boron, preferred 1 * 10 ¹⁹Cm ^-3～3 * 10 ²⁰Cm ^-3

Afterwards, by contact layer and upper strata metal wiring (diagram slightly) are set, obtain the memory component of this first execution mode.

Among the present invention, need not form the complicated step of such projection 942 grades of Figure 29 completely on semiconductor layer 161 surfaces.

Secondly, the method for operation as the information stores of the memory component of relevant first embodiment of the invention describes wiring method.As shown in Figure 2, apply first reference voltage from 180 pairs of DC power supply with p type diffused layer zone 112 terminals that are connected 152 via first voltage applying circuit 181.Via second voltage applying circuit 182 from 180 pairs of DC power supply and another p type diffused layer zone 113 terminals that are connected 153 apply with respect to reference voltage for negative write voltage (for example with respect to reference voltage be-6V～-14V).Via tertiary voltage apply circuit 183 from 180 pairs of terminals 151 that are connected with gate electrode 131 of DC power supply apply with respect to reference voltage for negative voltage (for example with respect to reference voltage for-6V～-18V).

Above-mentioned first voltage applying circuit 181, second voltage applying circuit 182, tertiary voltage apply circuit 183 and constitute respectively and possess switch element, and these switch elements are by the not shown decoding circuit order that applies of the timing that applies of Be Controlled voltage and voltage application time and voltage optionally.

At this moment, the channel region between diffusion zone 112～113 produces electric current, but because channel region is a kind of resistive element, so there is Joule heat to produce.Have following effect, that is,, generate and to have the hole that is used to fully to inject as the energy of the gate insulating film 162 of electric charge accumulation film by this heat.(hole 171) writes in the gate insulating film 162 by being injected into.

Under this situation, not with raceway groove pinch off (ピ Application チオ Off).But, no matter be the situation of pinch off under the situation behind the pinch off or not, as described above, all produce Joule heat.By this heat, generate hole in the whole parts of raceway groove with abundant energy, therefore, hole 171 is injected into the region-wide of the gate insulating film 162 that is positioned at the channel region top.

As at this preferred voltage application method, compare the absolute value height of the negative voltage that gate electrode 131 is applied with the negative voltage that another diffusion layer region 113 is applied.Fashionable when writing under such condition, the transverse direction electric field of diffusion layer region 113 ends is relaxed by the electric field of gate electrode 131, and therefore, near the impact ionization diffusion layer region 113 ends etc. causes the hot carrier formation efficiency to reduce.Therefore, give gate insulating film 162, and the possibility of the interface damage in gate insulating film 162 and tagma 111 reduce.

Like this,, then the transverse direction electric field of diffusion layer region 113 ends can be relaxed, can suppress hot carrier and generate, therefore, have the effect that suppresses its damage if use the said method that applies high negative voltage by gate electrode 131.Fashionable writing of the memory component of first execution mode, the main hole that produces in the whole tagma 111 of 112～113 of diffusion zones that utilizes is injected, and therefore, even suppressed impact ionization at diffusion layer region 113 ends, also can write fully.And this method for implanting is because damage is few, so become the high memory component of reliability.Describe in detail for these advantage back.

Read in the action, for example be source electrode, be drain electrode, make transistor action with diffusion layer region 112 with diffusion layer region 113.Carrying out under the above-mentioned state that writes, when implementing to read, the read current that flows through between diffusion layer region 112 and the diffusion layer region 113 reduces than situation about writing.Therefore, can read write state by the size of read current.

In addition, writing fashionable said reference voltage also can be consistent with earthing potential, in addition, as required, also can use earthing potential current potential in addition.For example, in above-mentioned each the voltage example under the situation that with the reference voltage is 14V, another diffusion layer region 113 is 8V～0V, gate electrode 131 be 8V～-4V.Under this situation, owing to the absolute value of the voltage that can suppress to apply on each terminal, so have the advantage of the peripheral circuit simplification that can be used for service voltage.

At this, first execution mode is characterised in that as so-called P channel-type semiconductor element and forms that this point is of crucial importance to guaranteeing memory window.Below this point is described.

Fig. 3 be represent as a reference, have a figure with the write diagnostics of the N channel-type semiconductor element of memory component identical construction of the present invention.At this, it is identical with P channel shape semiconductor element to have material, film component, each thickness that same structure is meant grid length, grid width, gate insulating film.In addition, in forming technology, be to form N channel-type element, except that the ion injecting process difference that is used to form diffusion layer region etc., film making process, etching work procedure, thermal technology's preface etc. all are common.

The semiconductor element that is used for the mensuration of Fig. 3 has the structure shown in the plane graph of the profile of Figure 1A, Figure 1B.It is the dielectric substrate 101 that constitutes of the glass substrate of 1W/mK, the CG silicon semiconductor layer 161 of thickness 40nm, the channel region 110 of channel width 2.5 μ m, channel length 0.45 μ m that this semiconductor element possesses by pyroconductivity.In addition, gate insulating film 162 is by being made of silicon oxide film and the silicon nitride film 122 of the bottom insulating film 121 of thickness 10nm, thickness 20nm, being made of and the top dielectric film 123 of thickness 15nm constitutes silicon oxide film.Top dielectric film and bottom insulating film use the so-called TEOS oxide-film that forms by the plasma CVD method that has adopted tetraethoxysilane.Gate electrode 131 is made of tungsten, and interlayer dielectric 103 is made of silicon oxide film.This semiconductor element uses the write circuit of Fig. 2, apply 16V as grid voltage Vg, apply 10V as drain voltage Vd, apply 0V as source voltage Vs.

That Fig. 3 represents to write is preceding, 1 millisecond of Id-Vg characteristic after writing back, 10 milliseconds and writing back, 100 milliseconds and write.As Fig. 3 finding, when the write time was 100 milliseconds, the threshold value displacement was about 1V.

On the other hand, compare with the employed semiconductor element of the mensuration of Fig. 3 for the memory component of the present invention of P channel-type, except that the conduction type difference, other parts are all identical.Preceding as writing among Fig. 4,1 millisecond write back, 10 milliseconds and write shown in back, the 100 milliseconds of Id-Vg characteristics after writing, the write time, the threshold value displacement surpassed 6V when being 100 milliseconds.In addition, with regard to both writing with regard to the voltage, opposite in sign but absolute value is identical.That is, with the reference voltage that is applied for to a diffusion layer region and tagma, the absolute value of establishing grid voltage is 16V, and the absolute value of the voltage that another diffusion layer region is applied is 10V.

From Fig. 3 and Fig. 4 as can be seen, for the semiconductor memory component of the present invention of P channel-type is compared with N channel-type semiconductor memory component, writing speed is at a high speed, therefore, can increase memory window, maybe can carry out high speed motion.In addition, for making the writing speed high speed of N channel-type element, can make the so-called double grid structure (ダプ Le ゲ one ト Agencies makes) that possesses a plurality of gate electrodes.But when becoming the double grid structure, manufacturing process obviously complicates, and therefore, manufacturing cost increases significantly.When considering production, as the present invention, the advantage that makes the P channel-type is big.

As mentioned above, being characterized as the P type semiconductor element of semiconductor memery device of being located at first execution mode on the dielectric substrate forms, and thus, can obtain following the good characteristic that can not obtain of situation that forms as the N type semiconductor element.The memory component of first execution mode also has following such specific characteristic, unique mechanism.This is embodied in following situation as mentioned above, flows through electric current by the channel region 112～113 of diffusion layer regions, produces Joule heat, generates by this heat to have the sufficient hole of injecting institute's energy requirement.

For it is confirmed, element shown in Figure 1 is heated with heater test.That is, absorption and mounting are used for the semiconductor element of the mensuration of Fig. 4 on the plate of imbedding having heaters and thermocouple, measure heating-up temperature by thermocouple and test.Fig. 5 represents to write fashionable threshold value displacement with different heating-up temperatures.As shown in Figure 5, learn that make heter temperature when 30 ℃ change to 200 ℃, the high more writing speed of temperature is high more.That is, the temperature with semiconductor element is high more, and the hole is to the high more feature of the injection efficiency of gate insulating film, and has by heating semiconductor element limit, limit and carry out write activity, can will write the advantage of high speed or lower voltage.

In addition, element uses the element that is configured to top dielectric film (TEOS film) 15nm, silicon nitride film 20nm, bottom insulating film (TEOS film) 10nm of channel length 0.7 μ m, channel width 2 μ m, gate insulating film as used herein.Writing condition is, with respect to reference voltage (source voltage), establishes grid voltage for-15V, drain voltage are-8V, carries out 100 milliseconds write, and the element of A-stage is write.Temperature with mark writes, and at room temperature reads.

At this, for carrying out demonstration test, imbedding on the plate of having heaters the element of settling Fig. 1, but also can make near configuration resistive element or channel resistance semiconductor element, and making electric current flow through the structure that this resistive element or channel resistance heat semiconductor element.By channel resistance heating semiconductor element the time, semiconductor element of the present invention becomes and the auxiliary same state of heat.

At this, in the first embodiment,, use the materials that pyroconductivity is low and thermal insulation is high such as glass as dielectric substrate 101, this has important effect to the raising that writes efficient.Writing fashionablely, is channel region by making a kind of resistive element of current direction, thereby produces Joule heat, but because the thermal insulation height of substrate 101, so the heat that produces is suppressed to the diffusion of substrate side, thermal capacitance easily is closed in the semiconductor element, thereby the semiconductor element temperature rises effectively.Consequently, identical with the situation of heater heats substrate, the effect of bringing promotion to write.

Fig. 6 represents to write the fashionable threshold value displacement and the relation of channel width.Employed semiconductor element is except that channel width in the mensuration of Fig. 6, and is identical with employed semiconductor element in the mensuration of Fig. 5, and the voltage conditions that writes and read is also identical.Use the different semiconductor element of channel width to measure, under the situation of 100 milliseconds of write times, 1 second, 10 seconds, describe channel width and the relation that writes displacement.According to Fig. 6, learn that channel width is big more, displacement is big more, and it is high more to write efficient.Like this, the channel width of element is big more, and the absolute value of writing the electric current that flows in the fashionable element is also big more, and therefore, the full Joule heat that produces in each of semiconductor element of the present invention increases.Therefore, semiconductor element of the present invention raises owing to writing fashionable device temperature, so can realize the higher efficient that writes.When electric current was excessive, excessive temperature rose, and became the high temperature of the degree that can give dielectric substrate 101 and semiconductor layer 161 damages.Therefore, when the device that drives as memory component, improve by thermal effect and to write efficient, and current value is set at the degree that can not become the high temperature that produces degree of injury.

In addition, by semiconductor layer 161 being set at the interlayer dielectric 165 that island and formation have thermal insulation, the diffusion that the heat of writing fashionable generation reaches direction in the horizontal direction also is suppressed, and the temperature of writing fashionable semiconductor element is more effectively risen, and promotes to write.That is, can write with lower voltage.

The main writing mechanism of first execution mode is not a FN type channel current, and the generation of the hot carrier that neither near the so-called raceway groove snowslide diffusion layer region 113 ends causes etc.Writing mechanism of the present invention has utilized being subjected to writing the auxiliary whole channel region of heat that fashionable electric current produces, and produces the so special mechanism of charge carrier.Be described below.

Fig. 7 A, Fig. 7 B represent with higher drain voltage, Id-Vg characteristic when Vds=-4V reads.Among Fig. 7 A, Fig. 7 B, the initial stage characteristic before chain-dotted line is represented to write.After solid line is illustrated in and has carried out writing, be drain electrode, read characteristic when being source electrode with diffusion layer region 113 with diffusion layer region 112.On the contrary, dotted line is represented to be source electrode, to serve as the characteristic of reading in when drain electrode with diffusion layer region 113 with diffusion layer region 112.Therefore, the characteristic of reading of two directions after will writing among Fig. 7 compares.The Writing condition here is, Fig. 7 A writes the situation of grid voltage for-12V, and Fig. 7 B writes the situation of grid voltage for-15V.And drain electrode (diffusion layer region 113) voltage is-12V that source electrode (diffusion layer region 112) voltage is 0V.

When being source electrode with diffusion layer region 113 read characteristic and opposite when being source electrode with diffusion layer region 112 to read characteristic all more consistent in any figure.For example, the point that fully begins to connect as element, the grid voltage of read current 10 μ A/ μ m is defined as threshold value Vth, when read value, among Fig. 7 A with respect to A-stage Vth=-1.54V, after writing, Vth=-6.04V when diffusion zone 113 is source electrode (threshold value displacement Δ Vth=-4.50V), Vth=-5.91V when diffusion layer region 112 is source electrode (threshold value displacement Δ Vth=-4.37V).Therefore, two differences of reading condition are no more than 0.13V.That is, be about 3% with respect to two differences of reading condition from the threshold value displacement Δ Vth of A-stage.Identical with the situation among Fig. 7 B, the difference of reading condition with respect to two of Δ Vth is about 2%.Like this, two conditions of reading show very near characteristic.This expression be that the paper left and right directions (orientation) that is distributed among Fig. 2 in the gate insulating film 162 on being injected between the diffusion layer region 112～113 and captive hole is roughly that left and right symmetrically distributes.

In addition, in the employed semiconductor element of the mensuration of Fig. 7 A, Fig. 7 B, channel length is that 0.7 μ m, channel width are 4 μ m, the structure of gate insulating film is, the thickness of top oxide-film (TEOS oxide-film) 123 is 15nm, the thickness of silicon nitride film 122 is 20nm, and the thickness of bottom oxide film (TEOS oxide-film) 121 is 10nm.

At this, if being the generation of the hot carrier that causes because of near the so-called drain avalanche diffusion layer region 113 ends, the mechanism that writes produces, then near diffusion layer region 113 ends, cause, also mainly be confined near the gate insulating film 162 of diffusion layer region 113 ends so accumulate electric charge owing to charge generation.Under this situation, when drain voltage is set and read than the highland, become the transistor action under so-called zone of saturation or the approaching with it state.Therefore, drain electrode end becomes pinch off state or approaching with it state, exists by the limitation of accumulating electric charge to be in drain side or to be in source side, and it is poor to produce in read current.

At first, when reading, be that diffusion layer region 113 is source electrode, serves as drain electrode when reading with another diffusion layer region 112 to accumulate a side that the electric charge part exists, be present near the source electrode owing to accumulate electric charge, so read current is subjected to the influence of its electromotive force easily, cause read current to reduce.On the other hand, be source electrode with diffusion zone 112, serving as drain electrode when reading with diffusion zone 113 that drain voltage raises on the contrary, drain electrode end becomes pinch off state or approaching with it state.Therefore, reduce the degree of situation before read current can not be reduced in the local influence that electric charge gives read current of accumulating that exists of drain side.Consequently, read between condition two, it is poor significantly that read current produces.

But, in the reading under the high drain voltage of first execution mode, to read between condition two, such characteristic difference does not produce.This means that the distribution of accumulating electric charge in the gate insulating film 162 is not near the asymmetrical CHARGE DISTRIBUTION in the left and right sides (be meant among Fig. 2 on the paper about) that is confined to the diffusion layer region 113 about this, and be left-right symmetric roughly.That is, think that electric charge roughly similarly accumulates across the whole face of orientation.This be because, the main writing mechanism of first execution mode is whole special mechanism that produces charge carrier of channel region of having utilized after being subjected to writing heat that fashionable electric current produces auxiliary.By utilizing this mechanism to write, can carry out high speed and damage few writing.

Write fashionable carrying out this, in first execution mode, when being set at grid voltage with respect to reference potential (source potential) when higher, relaxing near the drain electrode end transverse direction electric field by the grid electric field, thereby more effectively be suppressed near the hot carrier of the part the drain electrode end than drain voltage.Therefore, the damage of semiconductor element can be prevented, and the reliability of memory can be improved.In addition, even attenuate gate insulating film 162 also can make the grid electric field more effectively work, therefore, similarly, local hot carrier generates and is suppressed, and the reliability of memory is improved.

Fig. 7 C, Fig. 7 D are with identical with Fig. 7 B Id-Vg characteristic when writing voltage conditions the semiconductor element that has used the gate insulating film thicker than Fig. 7 B being write and reads.In addition, identical with Fig. 7 B.The structure of the gate insulating film that is made of top oxide-film/silicon nitride film/bottom oxide film is respectively: thickness is 20nm/30nm/10nm in Fig. 7 C, is 40nm/40nm/10nm in Fig. 7 D.Channel length, channel width are identical.Learn that from these figure thickness is thick more, the characteristic that two directions read can produce some poor more, and the situation (representing with solid line) of writing fashionable diffusion layer region 113 for drain electrode become source electrode when reading becomes low slightly electric current.When carrying out the calculating identical with Fig. 7 A, Fig. 7 B, threshold value displacement Δ Vth when being source electrode from A-stage with diffusion layer region 113, two read condition difference with it is respectively, and is about 4% among Fig. 7 C, be about 9% among Fig. 7 D, the variance yields that thickness is thick is big.

This is illustrated in the thick semiconductor element of thickness, exists in diffusion layer region 113 sides and accumulates concentrating of electric charge.That is, mean that not only the main writing mechanism of the memory component of first execution mode promptly utilizes heat auxiliary from the injection of whole generation of channel region electric charge, and the hot carrier that takes place in the part of drain electrode end also produces in some part.That is, the effect grid thickness that relaxes near the transverse direction electric field the drain electrode end by the grid electric field is thick more then weak more, because in the generation of the high-energy hot carrier of drain electrode end, semiconductor element may can sustain damage thus.From this point, the preferred electrolemma of gate insulating film is thick in thinner, can more effectively suppress the generation of the high-energy hot carrier of drain electrode end.CHARGE DISTRIBUTION after writing is not limited to drain electrode end, evenly distributes and roughly become, and, becomes the roughly Potential Distributing of symmetry between two diffusion layer regions that is, therefore, as mentioned above, even switching source electrode and drain electrode are read, also can be approximating characteristic.Potential Distributing is even more good more, and therefore, both characteristic differences are the smaller the better.Both threshold difference are preferably below 10% with respect to writing the threshold variation amount that obtains.

As above, among the present invention, the electric charge from channel region whole auxiliary by heat injects, with electric charge accumulation in the electric charge accumulation film.But the invention is not restricted to accumulate in the electric charge of electric charge accumulation film all is to inject by the auxiliary electric charge from whole of channel region of heat.If the degree that semiconductor element is injury-free then also can be injected the hot carrier that generates to drain electrode end.

Among Fig. 7 D, the electrolemma that converses by dielectric constant is thick to be scaled about 60nm by silicon oxide film, preferably thinner than it.More preferably, shown in the situation of Fig. 7 C,, more effectively suppress the generation of drain electrode end hot carrier by becoming the gate insulating film that is scaled 45nm with silicon oxide film.In addition, shown in Fig. 7 A, Fig. 7 B, if thick the reducing to by silicon oxide film of electrolemma of gate insulating film is scaled 35nm, it is roughly even on raceway groove then to accumulate electric charge, the generation of drain electrode end hot carrier is very well suppressed, and obtains the high semiconductor element of reliability.

On the other hand, if gate insulator is lepthymenia, then the device property deviation may appear in the influence because of the thickness deviation, and in addition, the withstand voltage of gate insulating film may reduce, and may destroy device, in addition, as mentioned above, charge-retention property is worsened.Therefore, preferably top oxide-film/silicon nitride film/bottom oxide film is made as respectively more than the 5nm/10nm/5nm, that is, and with thick the counting more than the 15nm of electrolemma of silicon oxide film conversion.Therefore, the thick 15nm of counting of the electrolemma～45nm that converts with silicon oxide film is a preferred range.

Perhaps, preferably make the electrolemma of gate insulating film thick in approaching and not making its actual thickness thin excessively, therefore, as the electric charge accumulation film, it also is effective using high hafnium oxide of permittivity ratio silicon nitride film or zirconia etc.

As above, in the first embodiment, when using glass substrate,, get the value about 0.5～1.5W/mK as typical pyroconductivity value.Like this, owing to use the high material of thermal insulation as substrate 101, so can not break away from substrate side by the heat of writing fashionable electric current generation, this heat can promote the temperature of semiconductor element effectively with doing one's utmost.Improve because of improving temperature owing to write efficient, so can realize utilizing effectively writing of heat that semiconductor element self sends.

Semiconductor layer 161 formed island and then forms 165 pairs of interlayer dielectrics that heat is concentrated on memory component is effective.That is, as first execution mode, when using glass substrate or resin substrates, can realize the advantage of following two aspects, promptly owing to the substrate cheapness, so can be with low-cost production as substrate; Because pyroconductivity is low and thermal insulation is high, so can make the high speed that writes that utilizes heat as mentioned above.

In addition, as shown in Figure 6, channel width is big more, can access high writing speed more.This be because, electric current is big and caloric value is big between the source electrode-drain electrode of semiconductor element of the present invention, so temperature rises easily.Therefore, it is big more to obtain channel width, more the advantage that can write with low-voltage more at a high speed or more.

Channel width is being set at greater than 100 μ m, for example during 200 μ m etc., it is very big to write the fashionable magnitude of current, therefore, be subjected to the influence that voltage that dead resistance causes descends easily, in addition, because the area self of semiconductor element also increases, thereby radiating effect also improves, therefore, be that the situation of 100 μ m is compared with channel width, not too big raising of writing speed.On the other hand, because the increase of the magnitude of current, may also can produce the increase of the increase that consumes electric power and periphery circuit area or, preferably channel width is made as below the 100 μ m the damage and the destruction of distribution.

In addition, channel width is being set at less than 0.5 μ m, for example during 0.3 μ m etc., the deviation between each semiconductor element increases.Therefore, preferred channel width is greater than 0.3 μ m.

As above, as preferred channel width, get 0.5 μ m～100 μ m.In addition, as preferred channel width, particularly can suppress the deviation and the magnitude of current also can be less, can select the value of 2 μ m～20 μ m, in the first embodiment, as one of preferred channel width example, is set at 5 μ m.

About channel length, if channel length is excessive, then there is the very slow problem of writing speed, preferably be made as below the 5 μ m.On the other hand, less than 0.1 μ m, then the influence of short channel effect increases as if channel length, and the deviation between semiconductor element also increases, and therefore, preferred channel length is more than the 0.1 μ m.

Secondly, about writing speed channel length L, channel width W and the dependence that writes drain voltage Vds are described.Fig. 8 represents various channel length L, channel width W, writes the example of the write diagnostics under the drain voltage Vds.The structure of gate insulating film is top oxide-film (TEOS film) 15nm, silicon oxide film 20nm, bottom oxide film (TEOS) 10nm.Write fashionable voltage and be, source voltage 0V, grid voltage Vgs-15V reads drain voltage and is-0.05V.Among the figure, transverse axis represents to write the voltage application time, and the longitudinal axis is represented by writing threshold value from the amount of A-stage displacement, owing to be to inject for the hole of P channel-type semiconductor element, so threshold value is because of writing to the negative direction displacement.

Fig. 8 A be drain voltage Vds for-9V ,-12V ,-during 15V, the write diagnostics of the semiconductor element of the semiconductor element of L=1.2 μ m/W=2 μ m, L=2.7 μ m/W=10 μ m is measured (being represented by circle, triangle, four jiaos respectively) and example relatively respectively.According to this figure, under arbitrary drain voltage, the write diagnostics of the semiconductor element of the semiconductor element of L=1.2 μ m/W=2 μ m, L=2.7 μ m/W=10 μ m is approximate.

In addition, Fig. 8 B also represents three different channel length L, channel width W, writes the example of the write diagnostics under the drain voltage Vds.

(a) Vds=-9V of the semiconductor element of L=0.7 μ m/W=10 μ m is write and the Vds=-12V of the semiconductor element of L=0.7 μ m/W=4 μ m is write, be approaching write diagnostics (curve that the figure orbicular spot is represented).

(b) Vds=-12V of the semiconductor element of L=0.7 μ m/W=2 μ m is write and the Vds=-15V of the semiconductor element of L=1.2 μ m/W=4 μ m is write, be approaching write diagnostics (curve that the figure intermediate cam is represented).

(c) Vds=-6V of the semiconductor element of L=0.7 μ m/W=4 μ m is write and the Vds=-9V of the semiconductor element of L=1.2 μ m/W=4 μ m is write, be approaching write diagnostics (four jiaos of curves of representing among the figure).

Can read above-mentioned (a) (b) feature of (c).

Like this, channel length is more little or channel width is big more or drain voltage is high more, and then writing speed is high more, on the basis of such feature, also can obtain the following rule of thumb.That is, writing speed roughly depends on following value, and 3/2 power that is about to the absolute value of drain voltage value Vds multiply by the square root of value of channel width W and the value that obtains divided by the value of channel length L.It is shown in Fig. 9.Expression suitably is located at 0.7 μ m～2.8 μ m, channel width with channel length and suitably is located at 2～10 μ m, drain voltage and suitably is located at-6～-15V between, write the fashionable displacement that writes respectively.Transverse axis represents | Vds| ^3/2* W ^1/2The value of ÷ L, the longitudinal axis represent that 100 milliseconds are write fashionable displacement (unit of Vds is that the unit of V, channel width W is that the unit of μ m, channel length L is μ m).At this moment, in this measurement range, both values are not subjected to have correlation about the value of W at least, | Vds| ^3/2* W ^1/2The value of ÷ L is high more, and writing speed is high more.

This tendency is an experience rule at most, can following qualitatively understanding.For writing speed, the temperature of groove is influential to it as mentioned above, but the transverse direction electric field of groove is helpful to it, can think that the transverse direction electric field is strong more, and it is high more to write efficient.At this, raceway groove is regarded as with simple resistance approximate, if resistance value is R, then caloric value P is by P=|Vds| ²/ R represents that R is directly proportional with L, is inversely proportional to W.Therefore, P depends on | Vds| ²* W/L, device temperature also depends on | Vds| ²* W/L.In addition, for groove transverse direction electric field, when also regarding raceway groove as uniform resistive element approx, by | Vds|/L represents.

Writing speed be subjected to these two parameters, | Vds| ²The value of * W/L and | the influence of the value of Vds|/L, therefore, finally be envisioned that, with respect to the dependence of L (L little, write efficient big), Vds one side's booster action (| Vds| is big, write efficient big) is bigger, but the booster action of W (W big, write efficient big) is big just like that as the influence of L.Therefore, can think, use with above-mentioned two square roots that parameter merely multiplies each other and obtains, promptly | Vds| ^3/2* W ^1/2The value of ÷ L, though not strict, but still can be used as the roughly parameter use that reflection writes efficient.

In addition, the voltage Vgs of gate electrode is also helpful to writing efficient.This be because: the absolute value of Vgs is high more, and channel resistance reduces, and therefore, have caloric value and increase, and the charge carrier that produces is pulled to the gate electrode direction more strongly, makes and writes the effect that efficient improves.Figure 10 A represent to the curve of Fig. 9 respectively with Vgs=-12V ,-15V ,-result that the writing speed separately of 18V is tested.By this figure as can be known, how to set Vds, Vgs, channel length, channel width for obtaining desirable writing speed.For example be set at 15V when above at absolute value with Vgs, be contemplated to if will | Vds| ^3/2* W ^1/2The value of ÷ L is set at more than 60, then obtains-threshold value displacement about 2V.In addition,, then envision the threshold value displacement and reach-4V, obtain big window if be set at more than 80.

In addition, the tendency of Fig. 9, Figure 10 A is very remarkable in the semiconductor element about 20 μ m at W, and the semiconductor element that is 100 μ m for the W value more than this, for example W may not be fit to.Like this, under the little situation of W, the area of the contact piston part that contacts with gate electrode and diffusion layer region etc. are big to the influence of semiconductor element size, even the different semiconductor element of W, himself does not have big difference device size yet.Therefore, caloric value is reflected on the device temperature better.But, on the other hand, think that when W was very big, the size of W directly was reflected on the device area, exothermal efficiency improves and writes the suitable amount of part that fashionable caloric value increases, and compares with the situation that W is little, and the caloric value dependence reduces.

The absolute value of Vgs is big more, and it is high more to write efficient, but its influence is big.This point is also relevant with the mechanism of the uniqueness that memory component had of first execution mode.Writing the memory that fashionable charge carrier injects the such type of main use drain avalanche, near the transverse direction electric field the drain electrode end has big influence to writing efficient.Therefore, the influence of drain voltage is big to writing speed, on the other hand, if improve grid voltage, the power enhancing that charge carrier pulls to the grid direction will take place then, on the contrary, and the direction action that the grid electric field relaxes at the transverse direction electric field with drain electrode end.Therefore, both effects are in the direction action of cancelling out each other, and consequently, grid voltage causes big influence to writing speed sometimes unlike drain voltage.

On the other hand, the main writing mechanism of the memory component of first execution mode is not the writing mechanism that has utilized drain avalanche, but as mentioned above, is to have utilized the charge carrier from whole of channel region of the heating effect of channel current to inject.Therefore, improve and to write the effect that complements each other that grid voltage can bring this two aspect of increase of the increase of the Joule heat that is caused by the reduction of channel resistance and the power by grid electric field attracts generation charge carrier.Thus, can significantly improve and write efficient.

Among Figure 10 B, Figure 10 C, the Vgs effect is further joined in the parameter of transverse axis, with | Vgs| ²* | Vds| ^3/2* W ^1/2÷ L value is transverse axis map (Vgs is that Vds unit is V, and W is that L unit is μ m).Figure 10 B is the figure when writing 100 milliseconds, and Figure 10 C is the figure when writing 1 second.At this moment, learn the figure of threshold value displacement of expression writing speed, have nothing to do with Vgs value and be depicted as roughly the same curve.In the parameter of transverse axis, compare with Vds, Vgs gets higher dimension (Vds is 1.5 powers, and Vgs is 2 powers), and this is meant that Vgs is very big for the influence that writes efficient.Consider such characteristic, get final product and carry out suitable designs.For example in the transverse axis parameter | Vgs| ²* | Vds| ^3/2* W ^1/2÷ L is 15000 when above, probably is-2V writing 1 second and can obtain the threshold value displacement, and therefore, it is preferred condition.On the other hand, when the value of transverse axis parameter surpassed 40000, device produced breakage sometimes, so must be noted that.

(second execution mode)

Use Figure 11 that second embodiment of the invention is described.

Figure 11 A is the A-B line generalized section of Figure 11 B, and Figure 11 C is a floor map.Profile construction is identical with above-mentioned first execution mode, in semiconductor layer 161, be provided with tagma 111 and p type diffused layer zone 112,113, and the surface of the body region 111 between the p type diffused

layer zone

112 and 113 becomes channel region 110, and then has electric charge accumulation film 162 and gate electrode 131 at an upper portion thereof.

At this, second execution mode is characterised in that to possess the electrode terminal (not shown) that contacts and be used to control the current potential in tagma with tagma 111.As particularly preferred mode, one example as shown in Figure 11 B, with the part in the tagma 111 is the body contact area 114 with N type conduction type, and according to the mode that at least a portion with this body contact area 114 contacts above-mentioned electrode terminal (diagram slightly) is set.As realizing this example of structure,, obtain above-mentioned structure on body contact area 114 by the contact plug (diagram slightly) that is made of metal is set.Thus, the contact resistance between electrode terminal and the tagma 111 reduces, and can carry out ohmic contact, can improve the controlled of bulk potential.In the semiconductor storage of second execution mode,, when carrying out erasing move,, can realize wiping of high speed with lower voltage thus by being located at the electrode terminal control volume current potential of this body contact area 114 as the back narration.

Figure 11 B schematically shows the planar configuration when being located at semiconductor layer 161 with diffusion layer region 112 same side in respect to gate electrode 131 above-mentioned body contact area 114.When adopting this structure, preferred body contact area 114 and diffusion layer region 112 are kept off, and are provided with the distance of certain degree.Like this, because semiconductor layer 161 is located on the dielectric substrate,, may contain crystal defect etc. so crystallinity may not be high.Therefore, at this, when the P type semiconductor zone that makes high concentration is that the N type semiconductor zone of diffusion layer region 112 and high concentration is that body contact area 114 is approaching, when forming the rapid PN junction of change in concentration, may produce because of defective cause in conjunction with leakage current.When driving a plurality of memory component, be that non-select storage unit also can take place particularly even such joint leaks.Its possibility of result can bring increase and the remarkable action that consumes electric power.

For preventing it, separate the above distance of 2 μ m between preferred body contact area 114 and the diffusion layer region 112, and have the semiconductor layer zone 115 of low concentration between the two.If the width of the semiconductor layer 115 of low concentration is big more, and body contact area 114 and diffusion layer region 112 may leave more, but excessive, the device area of semiconductor element is increased, and is therefore not preferred.Therefore, below the preferred 20 μ m.In addition, the concentration of semiconductor layer 115 is 5 * 10 ¹⁶Cm ^-3～2 * 10 ¹⁸Cm ^-3About.

In addition, body contact area 114 can be arranged on diffusion layer region 113 sides, also can be arranged on the both sides of gate electrode 131.

In addition, as the mode of preferred planar configuration, also can body contact area 114 be set with the such form of the plane graph of Figure 12.In the situation of this Figure 12, the form setting of gate electrode 131 so that diffusion layer region 112 is separated with diffusion layer region 113.Simultaneously, the form setting will also separating between body contact area 114 and the diffusion layer region 112,113.That is, semiconductor layer 161 is distinguished at least three zones of the part of the part that comprises diffusion layer region 112, the part that comprises diffusion layer region 113, occlusion body contact area 114 by gate electrode 131.Under the situation of this planar configuration, in the memory component of nonselection mode, the semiconductor layer 161 under the gate electrode 131 exhausts by the electromotive force of gate electrode 131, separates by this depletion layer between diffusion layer region 112,113 and the body contact area 114.Therefore, insulating properties height between the two is difficult to produce leakage current, therefore, can suppress to consume the increase of electric power and the generation of abnormal operation.

For obtaining above-mentioned structure,, among Figure 12 gate electrode 131 is formed the T font as an example.Under this situation, the position of preferred diffusion layer region 112,113 gate electrode 131 of horizontal line in being equivalent to the T word is left and is provided with, and has the semiconductor layer 116 of low concentration between the two.Like this, when the horizontal line in the T word of diffusion layer region 112,113 and gate electrode 131 contacts (Figure 13), when reading action, the semiconductor layer 161 the horizontal line subordinate of this T word produces leakage current 191 between two diffusion layer regions.The number of read current influences the maintenance electric charge of the electric charge accumulation film on the channel region 110, and thus, the element of second execution mode works as memory.But, even therefore such leakage current 191 compares the read current increase write state under owing to keep the influence of electric charge little and also have electric current flow through under the state that memory writes with the structure of Figure 12.

On the other hand, in the structure of Figure 12, the influence of this leakage current can be suppressed for littler, and can reduce the read current amount of write state.That is, the structure of Figure 12 can make the ratio of read current under the erase status and the read current under the write state bigger, therefore, can carry out stable reading, and obtains the higher storage device of reliability.Therefore, the two or at least one side of preferred diffusion zone 112,113 is only to dispose with the mode that gate electrode 131 contacts at the position towards channel region 110.

The memory component of this aspect second execution mode also can form by the technology identical with above-mentioned first execution mode, but also can be at the front and back or the while in formation p type diffused layer zone, organizator contact area 114 in semiconductor layer 161.The formation of this body contact area 114 is identical with the formation in p type diffused layer zone 112,113, can use ion implantation or solid phase diffusion method.The impurity that gives N type conduction type is imported the zone that should become body contact area 114, afterwards, suitably carry out annealing in process, the organizator contact area 114 thus.When carrying out above-mentioned annealing in process, the annealing in the time of can forming with p type diffused layer zone 112,113 is carried out simultaneously, also can carry out respectively.When carrying out at the same time, process number reduces, and is favourable aspect manufacturing cost.

Is benchmark as the wiring method of the method for operation of storage for information about of the memory component of second execution mode with the method for above-mentioned first execution mode.That is, as shown in figure 14, apply first reference voltage from 180 pairs of DC power supply with p type diffused layer zone 112 terminals that are connected 152 via first voltage applying circuit 181.Via second voltage applying circuit 182 from 180 pairs of DC power supply and another p type diffused layer zone 113 terminals that are connected 153 apply with respect to reference voltage for negative write voltage (for example with respect to reference voltage be-6V～-14V).Via tertiary voltage 183 apply circuit from 180 pairs of terminals 151 that are connected with gate electrode 131 of DC power supply apply with respect to reference voltage for negative voltage (for example with respect to reference voltage for-6V～-18V).Apply reference voltage via the 4th voltage applying circuit 184 from 186 pairs of terminals 154 that are connected with the body contact zone that is connected in tagma 111 of power supply.

Above-mentioned first voltage applying circuit 181, second voltage applying circuit 182, tertiary voltage apply circuit 183, and the formation of the 4th voltage applying circuit 184 identical with first execution mode, possess switch element respectively, these switch elements are optionally controlled the order that timing that voltage applies and voltage application time and voltage apply by not shown decoding circuit.

At this moment, channel region between diffusion zone 112～113 produces electric current, by this heat, generate and to have fully, be used to inject hole as the energy of the gate insulating film 162 of electric charge accumulation film, (hole 171) writes in the gate insulating film 162 by being injected into.

The action of reading of the memory component of this second execution mode is that benchmark carries out with the method for above-mentioned first execution mode, by making transistor action, detects the electric current that flows through between two diffusion layers, and reads write state by its number.

In addition, in second execution mode, be connected with terminal 154, but also can and read when write activity when moving, apply voltage from DC power supply 186 to this terminal 154 via the 4th voltage applying circuit 194 at body contact area 114.Perhaps also can be for not applying the so-called floating state of voltage.Consider from the aspect of device action control, preferably apply voltage, in second execution mode, writing fashionablely, apply the reference voltage identical with terminal 152.Thus, also discharge from body contact area 114 in a part of writing fashionable charge carrier with twice generation, therefore, the controlled raising of bulk potential has suppressed the action deviation between semiconductor element.In addition, in second execution mode, when reading, also terminal 154 is applied the voltage identical with source electrode.When reading, be source electrode, serve as drain electrode when making transistor action with diffusion layer region 112 with diffusion layer region 113, can apply the voltage identical with terminal 152.

Secondly, the operation as the information stores of the memory component of relevant first embodiment of the invention illustrates method for deleting.When wiping, as shown in figure 15, apply to the terminal 152,153 that is connected with two diffusion layers 112,113 from DC power supply 190 via the 5th and the 6th voltage applying circuit 191,192 and to wipe reference voltage.Applying with respect to wipe reference voltage from DC power supply 190 to the terminal 154 that is connected with tagma 111 via above-mentioned body contact area via the 7th voltage applying circuit 194 is that positive erasing voltage (is 6V～24V) with respect to wiping reference voltage for example.Applying with respect to wipe reference voltage from DC power supply 190 to the terminal 151 that is connected with gate electrode 131 via the 8th voltage applying circuit 193 is that positive erasing voltage (is 6～30V) with respect to wiping reference voltage for example.

The formation of above-mentioned the 5th voltage applying circuit 191, the 6th voltage applying circuit 192, the 7th voltage applying circuit 193, the 8th voltage applying circuit 194 is identical with first execution mode, possess switch element respectively, these switch elements are optionally controlled the order that timing that voltage applies and voltage application time and voltage apply by not shown decoding circuit.Above-mentioned the 5th voltage applying circuit 191, the 6th voltage applying circuit 192, the 7th voltage applying circuit 193, the 8th voltage applying circuit 194 apply voltage by adjusting, can apply circuit 183 with first voltage applying circuit 181, second voltage applying circuit 182, the tertiary voltage of second execution mode, the 4th voltage applying circuit 183 becomes common electric current.

At this moment, by the electromotive force of gate electrode 131, form the electronics accumulating layer in the tagma 111 of the near interface that is arranged in tagma 111 and gate insulating film 162.This electronics accumulating layer is controlled by above-mentioned erasing voltage by body terminal 154, forms the joint that has applied strong reverse biased having applied between the p type diffused layer zone 112,113 of wiping reference voltage.At this junction surface, because of above-mentioned strong reverse biased produces leakage current in the other direction, and then owing to be subjected to the acceleration of electric field, and secondary generates high-octane charge carrier.This a part of electronics that generates in the charge carrier is attracted by the electromotive force of gate electrode 131, is injected in the gate insulating film 162 (electronics 172), wipes.Like this, when implementing to read with the state that has carried out wiping, the read current that flows through between a diffusion layer region 112 and another diffusion layer region 113 increases than the read current under the write state.

When carrying out above-mentioned erasing move,, can carry out more wiping of high speed particularly by being set at the erasing voltage height in comparison tagma 111 to the erasing voltage of gate electrode 131.By the potential setting with gate electrode 131 is current potential height than diffusion zone 112,113 and tagma 111, can will generate electronics by its electric field and pull to gate electrode 131 directions (among Figure 15 on the paper direction) effectively, can will wipe high speed.

In addition, the said reference when wiping can be consistent with earthing potential, in addition, as required, also can use the current potential outside the earthing potential.For example, for above-mentioned each voltage example when establishing reference voltage for-12V, body contact area 113 is-6V～-12V, gate electrode 131 is-6V～-18V.Under this situation,, has the peripheral circuit simplification that can be used for service voltage owing to can suppress to put on the absolute value of the voltage of each terminal.

In addition, above-mentioned is that the voltage of two diffusion layer regions when having carried out wiping simultaneously applies, but also can one by one apply respectively.But, wipe simultaneously as mentioned above, finish the advantage of wiping in the short time but have.

Writing of previously described second execution mode is fashionable carrying out, the hole is injected into gate insulating film 162 from the whole face of channel region, relative with it, the electronics when the wiping of this explanation injects mainly the boundary vicinity generation in diffusion layer region 112,113 and tagma 111.But this electronics injects the diffusion that has to a certain degree, thus, can accumulate wiping of hole.Be described in detail below this point.

For investigation electronics when wiping is injected into the scope of which kind of degree from the diffusion layer region end towards the raceway groove central portion, carried out test shown in Figure 16.At this, be floating state with diffusion layer region 112, only apply erasing voltage in diffusion layer region 113 sides.Erasing voltage is-11V.Gate electrode 131 is applied 15V, tagma 111 is applied 10V.So according to above-mentioned erase mechanism, electronics only injects and produces near diffusion layer region 113 ends, does not in fact produce in diffusion layer region 112 sides.Such wiping used the different semiconductor element of channel length, and relatively it reads characteristic.When representing respectively that channel length is 0.45 μ m, 1.2 μ m, 1.7 μ m, Figure 17 A, Figure 17 B, Figure 17 C read the Id-Vg characteristic.Owing to keep the influence of electric charge to be reflected in sensitively on the threshold value of reading Id-Vg, so the condition of reading adopts linear condition, i.e. drain voltage-0.05V.In addition, the erasing time floats in the interval that is set in 1 μ second～10 second.Its channel width of semiconductor element all is 5 μ m as used herein, and the membrane structure of gate insulating film is top oxide-film (TEOS film) 40nm, silicon nitride film 40nm, bottom oxide film (TEOS film) 10nm.

At first, be that the characteristic of 0.45 μ m is paid close attention to the channel length of Figure 17 A, just to carry out 1 microsecond as can be known and wipe, the whole displacement of Id-Vg curve is to wiping side.This means that promptly, the electronics that takes place at one-sided diffusion layer end injects is diffused as whole of the raceway groove that covers 0.45 μ m as far as possible, has injected electronics whole of raceway groove.

On the other hand, be that the situation of 1.2 μ m is paid close attention to the channel length of Figure 17 B, wiping 1 microsecond and 1 millisecond of such short time when wiping, the Id-Vg curve erect a little almost not displacement, and find that the gradient of curve increases, i.e. Gm value rising.This expression be, near another diffusion layer region 112 ends of self-diffusion layer region 113 end injected electrons no shows.

Reading of this is that the linear areas of hanging down the Vds value is read, and therefore, in orientation, if local have the high part of threshold value, then the threshold value of this part reflects as the threshold value of semiconductor element self.That is, cause that near diffusion layer region 113 ends electronics injects, the local threshold value that produces reduces (because for the event of P type semiconductor element on the occasion of the direction displacement).But, near diffusion layer region 112 ends that inject the electronics no show, not producing the threshold value displacement, it is informed the threshold value of Id-Vg curve.Therefore, erecting a little of curve do not change.But near the threshold value reduction diffusion layer region 113 ends helps reducing of channel resistance, and therefore, the gradient of curve increases.

As mentioned above, in this semiconductor element,, almost can not confirm from diffusion layer region 113 to diffusion layer region wiping of 112 full channel region in 1 millisecond wipe.On the other hand, in wiping more than 100 milliseconds, confirmed curve erect a little displacement, be the injection of electronics to full channel region.That is, as can be known,, then also be injected into electronics at the point that leaves diffusion layer region end 1.2 μ m if be at least 100 milliseconds wipe.

In addition, the channel length shown in Figure 17 C is 1.7 μ m, before wiping 1 second, does not almost have the threshold value displacement, finds that mainly Gm increases.When wiping 10 seconds, the threshold value displacement takes place.That is, as can be known, if carry out wiping in 10 seconds, then the point at distance diffusion layer region end 1.7 μ m also is injected into electronics.

From such viewpoint, Figure 18 only represents the erasing time when one-sided diffusion layer is wiped and the relation of threshold value displacement.During up to 4.2 μ m, in measurement range, can not confirm the threshold value displacement in channel length.On the other hand, seen in Figure 17 B, Figure 17 C, when channel length was 1.2 μ m, 1.7 μ m, the threshold value displacement produced hardly in the wiping of short time, if the erasing time increases, then the threshold value displacement produces.That is, as can be known, inject,, also electronics can be injected into the position of leaving to a certain degree by prolonging the erasing time even produce electronics at the diffusion layer region end.If will be made as in the erasing time 10 seconds, then also be injected into electronics at the position of distance diffusion layer region 113 ends 1.7 μ m.

In this test, though just carried out the electronics injection from one-sided diffusion layer region one side, but inject if carry out such electronics, then electronics can be injected into apart from diffusion layer region 112 ends 1.7 μ m, apart from the position of diffusion layer region 113 ends 1.7 μ m at two diffusion layer region ends.That is,, then can carry out electronics and inject to full channel region if channel length is below the 3.4 μ m.If surpass it, channel length increases, even then wipe from two diffusion layer ends, the electronics when wiping injects also may not arrive the raceway groove central portion.

In the time will wiping, after wiping, the hole charge that writes also may remain in raceway groove central authorities on the actual effect to the memory element of write state.Because this hole hinders the electric current when reading, so with respect to write state, the read current of erase status can not fully increase, and the difference between current of write state and erase status, so-called window can diminish, and make the reliability reduction as memory.Erasable as if further repeating under this state, then the read current of erase status is lower, also can produce the possibility that write state and erase status are difficult to detect.For carried out erasable after, also increase the write/erase window, improve the reliability of memory, when wiping, electronics is injected into the raceway groove central portion and wipes that to accumulate the hole be important.But channel length is long more, and the erasing voltage or the erasing time that are used for electronics is injected into the raceway groove central portion are big more.

As above, below the preferred 3.4 μ m of channel length.In addition, among Figure 18, be in the semiconductor element of 1.2 μ m in channel length, be about 4.7V when obtaining wiping in 1 second, be the big threshold value displacement of 7.3V when wiping in 10 seconds.For accumulating the abundant charge neutrality in hole under the write state, repeat stable erasablely, consider that when both sides diffusion layer end was wiped, more preferably channel length at double was that channel length is below the 2.4 μ m.In addition, particularly be the data of the semiconductor element of 0.45 μ m according to channel length among Figure 18, in the wiping of 1 μ second, on whole of raceway groove, cause that strong electronics injects, there is big threshold value displacement to take place.That is, one-sided at the diffusion layer end, electronics can be injected into extremely at high speed the distance of 0.45 μ m, the result is, raceway groove length can be carried out high speed and wiped when 0.9 μ m is following, even or be lower voltage, also can carry out stable wiping.On this point more preferably channel length be below the 0.9 μ m.

As above, below the preferred 3.4 μ m of channel length, from repeating erasable stable aspect, more preferably channel length is below the 2.4 μ m.If channel length is below the 0.9 μ m, then obtain to carry out the high-performance semiconductor element that high speed is wiped, so preferred especially.

Like this, in channel length hour, because the electronics injection phase when wiping is near to the distance of raceway groove central portion, even so lower voltage, also the hole of accumulating can be wiped,, the read current value of erase status can be significantly improved with respect to write state in the raceway groove central portion.Therefore, obtain the memory that window is wide and reliability is high.

On the other hand, less than 0.1 μ m, then the influence of short channel effect increases as if channel length, and the deviation between semiconductor element also increases, and therefore, preferred channel length is more than the 0.1 μ m.According to channel length, suitable write, erased conditions is different, channel length is more little, can make more write, erasing voltage is low.For example when channel length is 0.5 μ m, example as Writing condition, with a diffusion layer region and tagma is reference potential, to gate electrode apply-12V～-16V, to another diffusion layer region apply-8V～-12V, example as erased conditions, with two diffusion layer regions is reference potential, and gate electrode is applied 12V～18V, the tagma is applied 10V～12V.

As above, compare, can carry out wiping of high speed with low-voltage with the method for deleting that has for example used the FN tunnel effect.Figure 19 represents dependent figure of the erasing time of threshold value displacement, and characteristic (" present embodiment " among the figure) under the situation about will wipe according to above-mentioned method for deleting and the characteristic (figure " FN injects and wipes 30V " reach " 18V is wiped in the FN injection ") of using the electronics of FN type channel current to inject under the situation of wiping compare.As applying voltage, under situation, be reference voltage with two diffusion layer regions according to the method for deleting of second execution mode, gate electrode is applied 18V, the tagma is applied 12V.Under the situation of " the FN raceway groove injects and wipes 30V ", to be that two diffusion layer regions and tagma are reference voltage than its high voltage, gate electrode is applied 30V, carry out the FN injection and wipe.Both are compared, and low voltage is used in wiping of second execution mode, and injects to wipe with the FN raceway groove and compare, and realizes inundatoryly wiping fast.Identical with second execution mode, gate electrode is being applied 18V, when trial FN wipes (" the FN raceway groove injects and wipes 18V " among the figure), almost can not the recognition threshold displacement.

About write activity, apply at the voltage of wiping par with above-mentioned FN in addition, (for example with respect to reference voltage, grid voltage is-30V) time, can cause hardly to write that in addition, if improve voltage, then semiconductor element produces and destroys.Relative with it, the wiring method of second execution mode has been realized write activity with lower voltage.Therefore, second execution mode has been realized the high performance memory component that can write and wipe with low voltage, high-speed ground.

At this, the feature of second execution mode is to form as so-called P channel-type semiconductor element, and this point is to guaranteeing that the window that writes, wipes is extremely important.Below this point is described.

About writing, as illustrated in above-mentioned first execution mode, the good write diagnostics that can not obtain in the situation that the element of the present invention that forms as P channel-type semiconductor element on dielectric substrate obtains forming as N channel-type semiconductor element.In addition, also following illustrated such about wiping, can obtain the good erasing characteristic that can not obtain in the N channel-type semiconductor element.

Figure 20 is expression to having the figure of N channel-type element with the memory component same configuration of the present invention characteristic when having applied erasing voltage.At this, have same structure and be meant identical with the structure that illustrates in first execution mode.As shown in figure 20, reach 10 seconds most even apply erasing voltage, also can cause the threshold value displacement hardly, this is more unexpected.Therefore, increase erasing voltage, as shown in figure 21, reduced making current on the contrary.This has represented element deterioration.From Figure 20 and Figure 21 as can be known, the storage unit of wiping the N channel-type is difficult.Like this, be the hole that aequum is wiped in generation, on its production efficiency, need the junction surface is applied to a certain degree high voltage, also in this process generate high-octane hole more.This high-octane hole can give gate insulating film and interface equivalent damage thereof usually, brings the device performance deterioration easily.When having adopted glass substrate or resin substrates etc., substrate is cheap, can make cheaply, but on the other hand, can not carry out the PROCESS FOR TREATMENT of high temperature during fabrication.Therefore, compare with the element that uses high-temperature technology to form on Semiconductor substrate, element reduces for the patience in high-energy hole, may sustain damage easily.Therefore, in this N channel-type element, by applying the hole injection that erasing voltage obtains, the deterioration that damage is brought takes place prior to wiping itself, causes that consequently electric current such among Figure 21 reduces.

On the other hand, the memory component of the present invention of P channel-type obtains the threshold value displacement and is about 3V shown in the erasing characteristic that shows among Figure 22 when the erasing time is 100 milliseconds.In addition, it is opposite that erasing voltage and the situation of Figure 20 of this moment compared is-symbol, but absolute value is identical.The absolute value of voltage that applies to two diffusion layer regions is that the absolute value of 10V, grid voltage is 2V, is 0V to the grid voltage in tagma.From Figure 20～Figure 22 as can be known, the erased element of the present invention of P channel-type is different with the N channel-type, can threshold value significantly be changed by wiping, and can increase memory window.Memory component of the present invention does not carry out the hole injection and carries out electronics and inject when wiping, big damage like that in the time of can not producing the hole injection.

At this, Figure 23 represents by applying the result that the N channel-type semiconductor element that strong erasing voltage reduces making current (channel length 0.7 μ m, channel width 2.5 μ m, gate insulator membrane structure are: top oxide-film 15nm, silicon nitride film 20nm, bottom oxide film 10nm, erasing voltage is: grid voltage-18V, tagma voltage-12V, diffusion layer region voltage 0V) carries out the short time annealing in process.Annealing in process is by carrying out in the annealing furnace that element is dropped into temperature in the stove and be set at 250 ℃.At first, under having carried out the state of strong erasing voltage after applying, the high-octane hole that semiconductor element produces when wiping sustains damage, therefore, and the electric current deterioration, but by this element is carried out annealing in process, electric current recovers significantly.That is, inject the electric current deterioration that causes and contain the key element of recovering by thermal annealing in a large number by this hole.

In the N channel-type semiconductor element, owing to injected hole when wiping, so the electric current deterioration that this damage causes is brought the reduction of wiping electric current.The reduction of wiping electric current directly makes window edge reduce.

On the other hand, P channel-type semiconductor element is in the memory component of second execution mode, and the charge carrier that injects when wiping is an electronics, injects with the hole injection at electronics and compares, and element is difficult to sustain damage.In the P channel-type semiconductor element, fashionable injection is only being write in the hole.This point becomes the i.e. advantage of the memory component of second execution mode of P channel-type semiconductor element.

That is, write fashionable owing between source electrode-drain electrode, flow through electric current, thus the semiconductor element heating, the temperature rising.Because hole injection process,, be difficult to sustain damage so the reduction of the occurrence frequency in high-octane hole is compared when N channel-type semiconductor element is applied erasing voltage for being assisted by this heating.

In addition, fashionable writing of second execution mode, even high-octane hole produces a part and semiconductor element sustains damage, the temperature height of the semiconductor element self during owing to write activity, so also have by this annealing effect, the effect that at least a portion of damage is recovered at once.

Figure 24 represents the write diagnostics that carries out with the various write times and erasing characteristic subsequently.Apply on 9V, the gate electrode in a diffusion layer region and tagma writing of this apply-6V, another diffusion layer region apply-3V and carrying out.In addition, apply wiping of this-3V, apply 15V on the gate electrode at two diffusion layer regions, the tagma applies 9V and carries out.As shown in figure 24, as can be known, in second execution mode, even distribute the amount of writing and hole injection rate, when after when wiping, also can obtain roughly the same electric current, the electric current deterioration takes place hardly.

Promptly, common high-octane hole brings damage for easily gate insulating film and interface thereof, and cause the device deterioration, but second execution mode write the heating that the resistance that utilizes semiconductor element self is injected in fashionable hole, in ablation process, generation with the high-energy hole that causes degree of injury is less, and therefore, the device deterioration is few.In addition, owing to write fashionable semiconductor element heating, directly bring the annealing effect thereby write behavior self, therefore, in second execution mode that adopts the P channel-type, even inject in part generation damage because of writing fashionable hole, this damage also has self-healing effect.Be erased to electronics and inject, therefore, be difficult to sustain damage.Can be implemented on the dielectric substrate such as glass substrate or resin substrates and to form and do not use high-temperature technology and the memory component that can make at an easy rate, and can realize strong with respect to the patience of damage deterioration, and the memory component that memory window is big, reliability is high.

As above being described in detail, the memory component of second execution mode is the memory component of being located on the dielectric substrate, it is characterized in that, have in the semiconductor layer on being located at dielectric substrate: control terminal, it has the tagma and contacts and be provided with the tagma, be surrounded by in this tagma for first diffusion layer region and second diffusion layer region of P-type conduction type and be clipped in first diffusion layer region and second diffusion layer region between channel region; Cover the electric charge accumulation film of channel region; Be positioned at the gate electrode of the opposition side in above-mentioned tagma across above-mentioned electric charge accumulation film.Owing to be so-called P channel-type semiconductor element, write so can inject by the hole, inject by electronics and wipe, bring following advantage thus.

In second execution mode, by the control volume current potential opposite direction electric current between tagma～diffusion layer region is produced, and generate high-octane hot carrier, carry out erasing move thus.Therefore, can wipe at high speed, but owing to be to form in second execution mode, so the hot carrier of injection is not hole but electronics when wiping as P channel-type element with low voltage.On the contrary, if N channel-type element, what inject when then wiping is the hole, but high-octane hole gives element damage easily.This damage can make read current reduce.On the other hand, in second execution mode, what inject when wiping is electronics, and the injection of high-energy electron is compared with the injection in high-octane hole, and is little to damage of elements.Therefore, the read current of erase status is reduced significantly.

Usually, the read current of erase status is big more, the read current of write state and erase status poor, be that so-called window is just big more, high more as the reliability of memory, thus preferably it.Element is difficult to sustain damage and the semiconductor element of second execution mode that read current is difficult to reduce is favourable in this when wiping.

On the other hand, the hole is infused in writes fashionable carrying out, but under this situation, owing between diffusion layer region, flow through electric current, thus element heating, and the bottom is dielectric substrate, the thermal insulation height, and therefore, component temperature rises.The main mechanism that the hole of the memory component of second execution mode is injected be subjected to should heat auxiliary, exist lessly to give element damage such high-octane hole.In addition, even produce the high-energy hole and element is caused damage in a part, because the temperature of element self rises, so also can make injury recovery by its annealing effect, the result is that the few hole of realization damage is injected.Because damage is few,, can keep electric charge for a long time so can not damage the electric charge hold facility by the earth.

Therefore, the memory component of second execution mode is by having said structure, thereby wide as its characteristic window edge, becomes the high memory component of reliability.Therefore, no matter write fashionablely when still wiping, damage is all lacked, and repeating still have big window edge after erasable, also can keep extremely long-time thus.

Particularly, when forming the memory component of second execution mode and driving the peripheral circuit of this memory component on identical dielectric substrate, peripheral circuit is made of TFT, has the advantage that can make at an easy rate, but then, each element of formation peripheral circuit has characteristic deviation.Therefore, the blind area of reading circuit also increases.From this point, as the memory component of second execution mode, big these characteristics of window edge become extremely important advantage aspect reliable in action.

Also as illustrated in above-mentioned first execution mode, gate insulating film is thin, can generate writing near the fashionable high-energy hot carrier that is suppressed at the drain electrode end.Therefore, can suppress damage to semiconductor element.As mentioned above,, can carry out injury recovery to a certain degree, but, then can accumulate, thereby may damage device reliability owing to repeating erasable damage if can not recover fully by writing fashionable heating.Therefore, the preferred generation that suppresses the big high-energy hot carrier of damage as much as possible.From this point, preferred attenuate gate insulating film.In addition, by making the gate insulating film filming, can when wiping, act on the grid electric field effectively to groove.In addition, because will taking place, charge carrier pulls to gate electrode side, so also have the advantage that can improve efficiency of erasing more powerfully.Therefore, preferably with the gate insulating film filming to can not cause that device destroys and excessive semiconductor element between the degree of deviation.

(the 3rd execution mode)

Third embodiment of the invention is to have adopted the memory component shown in the above-mentioned

execution mode

1,2 in liquid crystal indicator.

Liquid crystal indicator is to constitute across liquid crystal between a pair of substrate, shown in Figure 25 A, on a substrate, form scan line 512 and holding wire 513, the zone that surrounds with this scan line 512 and holding wire 513 is a pixel, possesses the drive circuit 510 of the optionally driving pixel electrode corresponding with this pixel.Each pixel electrode be formed at another substrate on opposite electrode toward each other, between have liquid crystal, optionally drive a pixel.

The 3rd execution mode is characterised in that, is formed with the memory component shown in first execution mode on the panel substrate of liquid crystal indicator.Under this situation, memory component of the present invention is used as the element of accumulating image information, and this image information offers the voltage generating circuit that the opposite electrode of liquid crystal indicator is applied voltage.

More particularly, shown in Figure 25 B, on the gate electrode of pixel TFT 511, be connected with scan line 512, be connected with holding wire 513, be connected with pixel electrode 514 at another diffusion layer region at a diffusion layer region of pixel TFT 511.Pixel electrode 514 is opposed with the opposite electrode 515 of shared panel via liquid crystal 516.On opposite electrode 515, apply the voltage of the regulation of voltage generating circuit 522 generations.The voltage that voltage generating circuit 522 takes place determines based on the image information of storing in the storage part 521 that possesses memory component of the present invention.

For suppressing the flicker of picture, opposite electrode 515 is applied the voltage that is taken place by voltage generating circuit 522, its magnitude of voltage is tackled each panel and is regulated.This voltage-regulation is normally regulated the outer variable resistance that is loaded on the panel.Owing to possess the memory component of first embodiment of the invention, thereby can cut down the cost of outer tape member self, the installation cost of outer tape member.In addition, because the automation of regulating is easy, so can cut down the inspection cost.In addition, because the simple structure of the gate insulating film of memory component of the present invention and necessary process number are few, so be favourable to cost cutting.

(the 4th execution mode)

Four embodiment of the invention is the display unit that possesses the such memory component shown in the above-mentioned execution mode 1,2.As display unit, exemplify liquid crystal panel and organic EL panel etc.

This display unit is characterised in that, digital information is imported on the above-mentioned panel substrate, and this display unit possesses the voltage that will be determined by this digital information and becomes the DA converter of simulation tonal signaling, the data of the correlation of the voltage of above-mentioned digital tone data of store predetermined and simulation tonal signaling in the memory component of above-mentioned first execution mode to the voltage follower circuit of above-mentioned opposite electrode output and with the digital tone data conversion.

More particularly, as shown in figure 26, display unit 6 possesses video data generation circuit 613, is that video data is delivered in the DA converter 612 with digital signal.DA converter 612 is that video data is transformed into analog signal with digital signal, delivers to display part 615 via output circuit 614.At this moment, need in DA converter 612, regulate the correlation of the voltage of digital tone data and simulation tonal signaling according to the mode that the color that makes the image that shows at display part reproduces naturally.Tackle each panel and regulate this correlation.The correlation of the voltage of digital tone data and simulation tonal signaling is stored in the storage part 611 that possesses memory component of the present invention.

The correlation of the voltage of digital tone data and simulation tonal signaling is stored in the non-volatile memory chip of tyre on the panel usually.By possessing memory component of the present invention, can cut down the cost of outer tape member self, the installation cost of outer tape member.In addition, because the automation of regulating is easy, so can cut down the inspection cost.In addition, because the simple structure of the gate insulating film of memory component of the present invention and necessary process number are few, so be favourable to cost cutting.

(the 5th execution mode)

Fifth embodiment of the invention is the receiver that possesses display unit, this receiver possesses the such memory component shown in the above-mentioned

execution mode

1,2, it is characterized in that, possesses display unit, the picture signal circuit that on the panel of this display unit, possesses the receiving circuit that receives picture signal and will supply with to display unit by the picture signal that this receiving circuit receives, for storage generates the required data of this picture signal, and be formed with above-mentioned memory component.

Particularly, as shown in figure 27, receiver 7 possesses display unit (display panels) 711, tuner 712, loud speaker 713, control part 714, antenna terminal 715.Figure 21 represents to be received by antenna the form of wireless signal, but by wired when coming received signal, antenna terminal replaces the cable splicing ear, and tuner replaces signal receiving part.Display unit 711 possesses memory component of the present invention.Can store the correlation etc. of the voltage of the magnitude of voltage, digital tone data and the simulation tonal signaling that are used for the opposite electrode to liquid crystal panel and apply in the nonvolatile memory that this display unit 711 possessed.In addition, by sending the signal behind the coding to display unit, and by display floater coding is decoded, the information that can realize is strengthened stably, the key letter of this moment can be stored in the memory component that display unit possesses.By possessing such display unit, can realize H.D receiver with low cost.

Claims

1. semiconductor element, it possesses:

Semiconductor layer, it is located on the dielectric substrate;

First diffusion layer region and second diffusion layer region, it is located in the described semiconductor layer, is the P-type conduction type;

The electric charge accumulation film, it covers the channel region between first diffusion layer region and second diffusion layer region at least, can be from this channel region iunjected charge;

Gate electrode, it is positioned at a side opposite with described channel region across described electric charge accumulation film,

The pyroconductivity of described dielectric substrate is 0.1W/mK～9W/mK,

The upper surface of being located at the described at least channel region of the semiconductor layer on the described dielectric substrate is smooth,

The electric charge that is injected into described electric charge accumulation film is: at electric current when first diffusion layer region flows to second diffusion zone by above-mentioned channel region, be subjected to assisting in the heat that channel region produces, be injected into the electric charge in the described electric charge accumulation film equably by described electric current.

2. semiconductor element as claimed in claim 1, wherein, the electric charge that is injected into described electric charge accumulation film is: at electric current when first diffusion layer region flows to second diffusion layer region by described channel region, be subjected to by described electric current auxiliaryly in the heat that channel region produces, charge carrier produces and the electric charge that causes on whole of channel region.

3. semiconductor element as claimed in claim 1, wherein, the electric charge that is injected into described electric charge accumulation film is: at electric current when first diffusion layer region flows to second diffusion layer region by described channel region, be subjected to assisting in the heat that channel region produces, at least by near the described electric charge accumulation film trapped charges first diffusion layer region by described electric current.

4. semiconductor element as claimed in claim 1, wherein, described electric charge accumulation film is being injected under the state of electric charge, and the difference of threshold value when first diffusion layer region has been applied reference potential and second diffusion layer region applied negative voltage and the threshold value when second diffusion layer region applied reference potential and first diffusion layer region applied negative voltage is below 10%.

5. semiconductor element as claimed in claim 1 wherein, also possesses at the interlayer dielectric that forms on the described semiconductor layer and on the described gate electrode.

6. semiconductor element as claimed in claim 5, wherein, at least a portion of described interlayer dielectric is made of resin.

7. semiconductor element as claimed in claim 1, wherein, the channel width of described channel region is 0.5 μ m～100 μ m.

8. semiconductor element as claimed in claim 1, wherein, the channel width of described channel region is 2 μ m～20 μ m.

9. semiconductor element as claimed in claim 1, wherein, described electric charge accumulation film has the stepped construction that is made of first dielectric film, the electric charge accumulation film with electric charge accumulation ability and second dielectric film at least.

10. semiconductor element as claimed in claim 9, wherein, the electric charge accumulation film with described electric charge accumulation ability is nitride film or high dielectric film.

11. semiconductor element as claimed in claim 1, wherein, described semiconductor layer is the island semiconductor layer that is formed on the described dielectric substrate.

12. semiconductor element as claimed in claim 1, wherein, the thickness of described semiconductor layer is 30nm～150nm.

13. semiconductor element as claimed in claim 1, wherein, described dielectric substrate is that pyroconductivity is the glass substrate of 0.5W/mK～2W/mK.

14. semiconductor element as claimed in claim 1, wherein, described dielectric substrate is that pyroconductivity is the resin substrates of 0.1W/mK～2W/mK.

15. semiconductor element as claimed in claim 1, wherein, described semiconductor layer also possesses the contact area for N type conduction type, and described contact area and control terminal join.

16. semiconductor element as claimed in claim 1, wherein, the channel length of described channel region is 0.1 μ m～3.4 μ m.

17. semiconductor element as claimed in claim 15 wherein, between described contact area and first diffusion layer region and second diffusion layer region, is formed with the impurity concentration semiconductor layer zone lower than the impurity concentration of described contact area.

18. semiconductor element as claimed in claim 17 wherein, has described gate electrode on the semiconductor layer zone of described low concentration.

19. semiconductor element as claimed in claim 1 wherein, also possesses display unit on the described dielectric substrate.

20. semiconductor element as claimed in claim 1 wherein, also possesses the heater of the described dielectric substrate of heating.

21. a liquid crystal indicator, it possesses liquid crystal indicator and liquid crystal display drive circuit on the panel substrate, wherein,

Described liquid crystal indicator has:

The scan line of rectangular configuration and holding wire,

With the zone that is surrounded by described scan line and holding wire is a pixel and the drive circuit that optionally drives the pixel electrode corresponding with this pixel,

Be located at the liquid crystal between described pixel electrode and the opposed with it opposite electrode;

Described liquid crystal display drive circuit has:

Input digit information and the voltage that will be determined by described digital information is to the voltage follower circuit of described opposite electrode output,

With the DA converter of digital tone data conversion for the tonal signaling of simulation,

The memory circuit that possesses semiconductor element, the correlation data of the voltage of described digital tone data of this semiconductor element store predetermined and simulation tonal signaling;

Described semiconductor element is the semiconductor element of record in the claim 1.

22. a receiver, it possesses: display unit and memory circuit,

Described memory circuit has:

Receive the receiving circuit of picture signal,

To supply with the picture signal circuit of display unit by the picture signal that described receiving circuit receives,

Storage generates the semiconductor element of described picture signal desired data;

23. a semiconductor device, it possesses:

The described semiconductor element of claim 1;

First voltage applying circuit that is connected with first diffusion layer region of described semiconductor element via first switch element;

Second voltage applying circuit that is connected with second diffusion layer region of described semiconductor element via the second switch element;

Apply circuit via the 3rd switch element with the tertiary voltage that the gate electrode of described semiconductor element is connected.

24. semiconductor device as claimed in claim 23, wherein, the voltage of voltage ratio first voltage applying circuit output that second voltage applying circuit and tertiary voltage apply circuit output is low.

25. semiconductor device as claimed in claim 23, wherein, the voltage of voltage ratio second voltage applying circuit output that tertiary voltage applies circuit output is low.

26. semiconductor device as claimed in claim 23 wherein, also possesses the 4th voltage applying circuit that is connected with the tagma of semiconductor element via the 4th switch element.

27. semiconductor device as claimed in claim 26, wherein, tertiary voltage applies the voltage height of voltage ratio first voltage applying circuit output of circuit and the output of the 4th voltage applying circuit.

28. semiconductor device as claimed in claim 26, wherein, tertiary voltage applies the voltage height of voltage ratio the 4th voltage applying circuit output of circuit output.

29. the driving method of a semiconductor element, use the described semiconductor element of claim 1, with respect to the reference voltage that puts on first diffusion layer region, second diffusion layer region and described gate electrode are applied negative voltage, make described channel region generation electric current and make its heating, the hole is injected in the described electric charge accumulation film thus.

30. the driving method of semiconductor element as claimed in claim 29 wherein, is compared with the negative voltage that puts on second diffusion layer region, the absolute value of negative voltage that puts on described gate electrode is big.

31. the driving method of semiconductor element as claimed in claim 29, wherein, with respect to the reference voltage that puts on first diffusion layer region, apply positive voltage by tagma to described gate electrode and described semiconductor element, electronics is injected in the described electric charge accumulation film.

32. the driving method of semiconductor element as claimed in claim 29, wherein, with respect to the reference voltage that puts on first diffusion layer region, apply and the idiostatic positive voltage of the current potential of second diffusion layer region by tagma, electronics is injected in the described electric charge accumulation film to described gate electrode and described semiconductor element.

33. the driving method of semiconductor element as claimed in claim 29 wherein, is compared with the positive voltage that tagma to described semiconductor element applies, the positive voltage height that applies to described gate electrode.