KR102188066B1 - Thin film transistor array substrate and manufacturing method of the same - Google Patents

Abstract

An embodiment of the present application is to provide a thin film transistor array substrate including a thin film transistor capable of easily dissipating heat generated during driving, and a thin film transistor array substrate including a plurality of thin film transistors corresponding to a plurality of pixel regions Wherein each thin film transistor includes: an active layer including a channel region and a source region and a drain region on both sides of the channel region; A gate insulating layer formed to cover the channel region; A gate electrode formed on the gate insulating layer; An interlayer insulating film formed to cover the active layer, the gate insulating layer, and the gate electrode; A source electrode formed on the interlayer insulating layer and connected to the source region; And a drain electrode formed on the interlayer insulating layer and connected to the drain region, wherein in the source region and the drain region into which impurities are implanted in the active layer, the drain region has a second width greater than the first width of the source region, The contact area between the drain region of the active layer and the buffer layer and the interlayer insulating film is larger than the contact area between the source region of the active layer and the buffer layer and the interlayer insulating film.

Description

Thin film transistor array substrate and its manufacturing method TECHNICAL FIELD {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD OF THE SAME}

The present application relates to a thin film transistor array substrate included in a display device of an active matrix driving mode. In particular, a thin film transistor array substrate including a thin film transistor having a structure capable of easily dissipating heat generated during driving And to a method of manufacturing the same.

As the information age enters in earnest, the field of displays that visually displays electrical information signals is rapidly developing. Accordingly, research is being conducted to develop performances such as thinner, lighter, and low power consumption for various flat display devices.

Typical examples of such flat panel display devices include Liquid Crystal Display device (LCD), Plasma Display Panel device (PDP), Field Emission Display device (FED), and electroluminescent display device. (Electro Luminescence Display device: ELD), an Electro-Wetting Display device (EWD), and an Organic Light Emitting Display device (OLED).

In common, such flat panel display devices essentially include a flat panel display panel for implementing an image. A flat panel display has a structure in which a pair of substrates with a unique light emitting material or a polarizing material interposed therebetween are bonded together.

In the case of a display device of an active matrix driving mode that individually drives a plurality of pixels, any one of the pair of substrates is a thin film transistor array substrate.

The thin film transistor array substrate is a plurality of thin film transistors formed in the crossing region between the gate line and the data line corresponding to the gate line and the data line and the plurality of pixel regions formed in directions that cross each other so that a plurality of pixel regions are defined. Includes.

Each thin film transistor includes a gate electrode, an active layer overlapping at least a portion of the gate electrode, and source and drain electrodes contacting both sides of the active layer.

Here, the gate electrode may be disposed under the active layer or may be disposed above the active layer.

When the gate electrode is disposed on the upper side of the active layer, there is an advantage of preventing leakage current due to light incident from the upper side by the gate electrode. However, since the gate electrode is disposed on a plane spaced apart from the substrate than the active layer, and the active layer is surrounded by an insulating material, there is a disadvantage that heat due to carriers moving through the channel region is accumulated in the active layer.

Particularly, when the active layer is formed of a semiconductor material with high carrier mobility, the heat generation rate increases accordingly. As heat of a high temperature is accumulated for a short period of time in the thin film transistor being driven, the thin film transistor deteriorates more rapidly. There is a problem that reliability is lowered.

As described above, if heat is not easily released from the thin film transistor being driven, the high speed driving of the thin film transistor and the reliability and life of the thin film transistor become a trade off relationship, and the reliability, life and operation of the thin film transistor array substrate There is a problem in that the speed is difficult to improve beyond the threshold.

The present invention is to provide a thin film transistor array substrate including a thin film transistor capable of easily dissipating heat generated during driving, and a method of manufacturing the same.

In order to solve such a problem, the present application provides a thin film transistor array substrate including a plurality of thin film transistors corresponding to a plurality of pixel regions, wherein each of the thin film transistors includes a channel region and a source region and a drain region on both sides of the channel region. An active layer including; A gate insulating layer formed to cover the channel region; A gate electrode formed on the gate insulating layer; An interlayer insulating layer formed to cover the active layer, the gate insulating layer, and the gate electrode; A source electrode formed on the interlayer insulating layer and connected to the source region; And a drain electrode formed on the interlayer insulating layer and connected to the drain region, wherein of the source region and the drain region into which impurities are implanted in the active layer, the drain region is a first width greater than a first width of the source region. Provides a thin film transistor array substrate having a width of 2 and a contact area between the drain region of the active layer and the buffer layer and the interlayer insulating layer is greater than the contact area between the source region of the active layer and the buffer layer and the interlayer insulating layer do.

In addition, the present application provides a method of manufacturing a thin film transistor array substrate including a plurality of thin film transistors corresponding to a plurality of pixel regions, the method comprising: forming a light shielding layer on the substrate; Forming a buffer layer on the substrate to cover the light blocking layer; Forming an active layer on the buffer layer that at least partially overlaps the light blocking layer; Forming a gate insulating layer on the channel region of the active layer corresponding to the light blocking layer, and forming a gate electrode on the gate insulating layer; Implanting impurities into both sides of the channel region of the active layer to form a source region and a drain region; Forming an interlayer insulating layer on the buffer layer, covering the active layer, the gate insulating layer, and the gate electrode; Forming a first contact hole exposing at least a portion of the source region and a second contact hole exposing at least a portion of the drain region by patterning the interlayer insulating layer; And forming a source electrode connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole on the interlayer insulating layer, wherein the active layer In the source region and the drain region into which impurities are implanted, the drain region has a second width greater than the first width of the source region, and a contact area between the drain region of the active layer and the buffer layer and the interlayer insulating layer is, It has a feature that is larger than a contact area between the source region of the active layer and the buffer layer and the interlayer insulating layer. A method of manufacturing a thin film transistor array substrate is further provided.

delete

delete

A contact portion between the source region and the source electrode connected through a first contact hole is spaced apart from the channel region by a first distance, and a contact portion between the drain region and the drain electrode connected through a second contact hole is separated from the channel region. It is spaced apart by a second separation distance longer than the first separation distance.

According to an exemplary embodiment of the present disclosure, the drain region of the active layer is formed to have a wider width than the source region. In addition, a part of the source region exposed by the first contact hole is spaced apart from the channel region by a first separation distance, and a part of the drain region exposed by the second contact hole is a second distance greater than the first separation distance from the channel region. It is separated by a separation distance.

Accordingly, it is possible to prevent heat at a temperature higher than that of the source region from accumulating in the drain region connected to the pixel electrode.

In addition, since the active layer is surrounded by aluminum oxide (Al ₂ O ₃ ) having a higher thermal conductivity than an inorganic insulating material such as SiNx or SiOy, heat of the active layer can be diffused more rapidly.

In this way, since the heat dissipation of the thin film transistor being driven becomes easy, the reliability, life, and driving speed of the thin film transistor and the thin film transistor array substrate including the thin film transistor can be improved.

1 is an equivalent circuit diagram showing a thin film transistor array substrate according to an embodiment of the present application.
2 is a plan view showing the thin film transistor of FIG. 1 according to an embodiment of the present application.
FIG. 3 is a cross-sectional view taken along line II′ of FIG. 2.
FIG. 4 exemplarily shows heating and heat dissipation rates compared to the distance ΔG spaced apart from the channel region in each of the source region and the drain region.
5 and 6 are plan views illustrating another example of the gate electrode of FIG. 2.
7 is a flow chart showing a method of manufacturing a thin film transistor array substrate according to an embodiment of the present application.
8A to 8G are process diagrams showing each step of FIG. 7.

Hereinafter, a thin film transistor array substrate and a method of manufacturing the same according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

A thin film transistor array substrate according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6.

1 is an equivalent circuit diagram showing a thin film transistor array substrate according to an embodiment of the present application. FIG. 2 is a plan view showing the thin film transistor of FIG. 1 according to an exemplary embodiment of the present application, and FIG. 3 is a cross-sectional view illustrating II′ of FIG. 2. FIG. 4 exemplarily shows heating and heat dissipation rates compared to the distance ΔG spaced apart from the channel region in each of the source region and the drain region. 5 and 6 are plan views showing another example of the gate electrode of FIG. 2.

As shown in FIG. 1, the thin film transistor array substrate 100 according to an exemplary embodiment of the present disclosure includes a gate line GL and a data line DL formed to cross each other so that a plurality of pixel areas PA are defined, And a plurality of thin film transistors TFT formed in a cross region between the gate line GL and the data line DL corresponding to the plurality of pixel regions PA.

Further, although not shown in detail in FIG. 1, the thin film transistor array substrate 100 further includes a plurality of pixel electrodes (not shown) corresponding to a plurality of pixel areas PA and connected to the plurality of thin film transistors TFT. do. For example, in the case of a liquid crystal display device, the pixel electrode (not shown) is for forming an electric field for changing the liquid crystal direction. Alternatively, in the case of an organic light emitting display device, a pixel electrode (not shown) is for supplying a driving current corresponding to each pixel region to the organic light emitting layer.

As shown in FIG. 2, each thin film transistor TFT includes an active layer ACT and an active layer ACT including a channel region CA, a source region SA and a drain region DA on both sides thereof. And a gate electrode GE overlapping the channel region CA of, and a source electrode SE and a drain electrode DE overlapping the source region SA and the drain region DA of the active layer ACT.

In addition, each thin film transistor TFT has a first contact formed in correspondence with a portion of the overlapping region between the source region SA and the source electrode SE so as to connect the source region SA and the source electrode SE. The hole CT1 and a second contact hole CT2 formed to correspond to a part of the overlapping region between the drain region DA and the drain electrode DE to connect the drain region DA and the drain electrode DE. ) More.

The active layer ACT may be formed of any one of an oxide semiconductor, polysilicon (crystalline silicon), and amorphous silicon (a-Si: amorphous silicon).

In particular, the active layer (ACT) can be formed in a low-temperature atmosphere compared to crystalline silicon (poly Silicon), and is formed of an oxide semiconductor having high carrier mobility and stable electrostatic characteristics compared to amorphous silicon (a-Si). Can be.

Exemplarily, the oxide semiconductor is AxByCzO(x, y, z ≥ 0), and each of A, B and C is selected from Zn, Cd, Ga, In, Sn, Hf, and Zr. For example, the oxide semiconductor may be any one of IGZO (In-Ga-Zn-Oxide), ITZO (In-Sn-Zn-Oxide), and IGO (In-Ga-Oxide).

In addition, of the active layer ACT, the source region SA and the drain region DA may be regions doped with more impurities than the channel region CA in order to further increase carrier mobility.

In addition, the drain region DA connected to the pixel electrode (not shown) through the drain electrode DE generates heat of a higher temperature as a larger amount of carriers are moved compared to the source electrode SA.

Accordingly, according to an exemplary embodiment of the present disclosure, in at least one direction (“left-right direction” in FIG. 2), the source region SA is formed to have a first width W1, while the pixel through the drain electrode DE The drain region DA connected to the electrode (not shown) is formed with a second width W2 greater than the first width W1. In this way, the high temperature heat generated in the drain region DA can be diffused to a wider area, so that concentration of the high temperature heat can be prevented.

In addition, according to an exemplary embodiment of the present disclosure, a portion of the source region SA exposed by the first contact hole CT1 in at least one direction (“left/right direction” in FIG. 2) is from the channel region CA. It is separated by the first separation distance (G1). In this case, the heat dissipation rate of the source region SA using the first contact hole CT1 and the source electrode SE connected thereto as a heat sink is set to be greater than or equal to the heating rate of the source region SA.

In addition, in at least one direction (“left/right direction” in FIG. 2), a portion of the drain region DA exposed by the second contact hole CT2 is greater than the first separation distance G1 from the channel region CA. It is separated by a long second separation distance (G2). At this time, the heat dissipation rate of the drain region DA using the second contact hole CT2 and the drain electrode DE connected thereto as a heat sink is set to be greater than or equal to the heating rate of the drain region DA.

In this way, it is possible to prevent the heat from being concentrated in the drain region DA where heat having a higher temperature than the source region SA is generated at a faster rate.

This will be described in more detail below with reference to FIG. 4.

As shown in FIG. 3, the thin film transistor array substrate 100 includes a substrate 101, a light blocking layer 110 formed on the substrate 101 to correspond to at least the channel region CA, and the substrate 101. A buffer layer 120 formed to cover the light blocking layer 110 is further included. In addition, each thin film transistor TFT is formed on the buffer layer 120.

The light blocking layer 110 is formed of a light blocking material that absorbs or reflects light. The light blocking layer 110 is for preventing a leakage current of the thin film transistor (TFT) due to light incident through the substrate 101.

Accordingly, the light blocking layer 110 is formed to overlap at least the channel region CA. Exemplarily, the light blocking layer 110 overlaps with the thin film transistor TFT of each pixel area PA, overlaps with the active layer ACT among the thin film transistors, or the channel area of the active layer ACT ( CA) and may be formed to overlap.

Alternatively, the light blocking layer 110 may be formed to further overlap a metal pattern disposed outside each pixel area PA, such as a gate line (GL in FIG. 1) and a data line (DL in FIG. 1). In this way, visibility of the metal pattern is reduced, and the image quality of the display device can be improved.

The buffer layer 120 is to insulate between the thin film transistor (TFT) and the light blocking layer 110. The buffer layer 120 may be formed of a single layer of insulating material on the entire surface of the substrate 101, or may be formed of multiple layers of insulating materials of different materials or different thicknesses.

In particular, the first buffer layer 121 of the buffer layer 120 that is in contact with the lower portion of the active layer ACT is formed of aluminum oxide (Al ₂ O ₃ ).

That is, the buffer layer 120 is a single layer including only the first buffer layer 121 of aluminum oxide (Al ₂ O ₃ ), or as shown in FIG. 3, the first buffer layer 121 of at least aluminum oxide (Al ₂ O ₃ ). ) Can be formed in multiple layers including. In this case, the other insulating layer 122 disposed between the first buffer layer 121 and the substrate 101 of the buffer layer 120 may be formed of an inorganic insulating material such as SiNx or SiOy.

In this way, heat generated in the active layer ACT is transferred to the buffer layer 120 by the first buffer layer 121 made of aluminum oxide (Al ₂ O ₃ ) having a higher thermal conductivity than an inorganic insulating material such as SiNx, SiOy, etc. Can spread faster to the side.

As mentioned above, each thin film transistor TFT is formed on the buffer layer 120 and includes an active layer ACT, a gate electrode GE, and source and drain electrodes SE and DE.

The active layer ACT is formed on the buffer layer 120 and includes a channel region CA and a source region SA and a drain region DA on both sides thereof.

The gate insulating layer 130 is formed on the buffer layer 120 to cover the channel region CA of the active layer ACT.

The gate insulating layer 130 may be formed of a single layer of insulating material on the channel region CA of the active layer ACT, or may be formed of multiple layers of insulating materials of different materials or different thicknesses. have.

In particular, among the gate insulating layers 130, the first gate insulating layer 131 in contact with the channel region CA of the active layer ACT is formed of aluminum oxide (Al ₂ O ₃ ).

That is, the gate insulating layer 130 is a single layer including only the first gate insulating layer 131 of aluminum oxide (Al ₂ O ₃ ), or as shown in FIG. 3, at least a made of aluminum oxide (Al ₂ O ₃ ). It may be formed of multiple layers including 1 gate insulating layer 131. In this case, the other insulating layer 132 disposed on the first gate insulating layer 131 of the gate insulating layer 130 may be formed of an inorganic insulating material such as SiNx or SiOy.

In this way, by the first gate insulating layer 131 made of aluminum oxide (Al ₂ O ₃ ) having a higher thermal conductivity than inorganic insulating materials such as SiNx and SiOy, heat generated in the active layer ACT is transferred to the gate electrode. It can spread faster to the (GE) side.

The gate electrode GE is formed on the gate insulating layer 130. Accordingly, the gate electrode GE overlaps the channel region CA with the gate insulating layer 130 therebetween.

The active layer ACT, the gate insulating layer 130 and the gate electrode GE are covered with an interlayer insulating layer 140 formed on the entire surface of the buffer layer 120.

The interlayer insulating layer 140 is to insulate the source and drain electrodes SE and DE from the gate electrode GE. The interlayer insulating layer 140 may be formed of a single layer of insulating material on the entire surface of the buffer layer 120, or may be formed of multiple layers of insulating materials of different materials or different thicknesses.

In particular, the first interlayer insulating layer 141 in contact with each of the source region SA and the drain region DA of the interlayer insulating layer 140 is formed of aluminum oxide (Al ₂ O ₃ ).

That is, the interlayer insulating layer 140 is a single layer including only the first interlayer insulating layer 141 of aluminum oxide (Al ₂ O ₃ ), or as shown in FIG. 3, at least made of aluminum oxide (Al ₂ O ₃ ). It may be formed of multiple layers including one interlayer insulating layer 141. In this case, the other insulating layer 142 disposed on the first interlayer insulating layer 141 among the interlayer insulating layers 140 may be formed of an inorganic insulating material such as SiNx or SiOy.

In this way, by the first interlayer insulating layer 141 made of aluminum oxide (Al ₂ O ₃ ) having a higher thermal conductivity than inorganic insulating materials such as SiNx and SiOy, heat generated in the active layer ACT is sourced and It may diffuse faster toward the drain electrodes SE and DE.

The first contact hole CT1 penetrates through the interlayer insulating layer 140 to expose at least a portion of the source region SA.

The second contact hole CT2 penetrates the interlayer insulating layer 140 to expose at least a portion of the drain region DA.

The source electrode SE is electrically connected to the source region SA of the active layer ACT through the first contact hole CT1.

The drain electrode DE is electrically connected to the drain region DA of the active layer ACT through the second contact hole CT2.

Each of the first and second contact holes CT1 and CT2 and the source and drain electrodes SE and DE serve as a heat sink for heat dissipation of the active layer ACT.

As mentioned above, in the driving thin film transistor TFT, heat in the drain region DA is generated at a higher temperature than the heat in the source region SA. This is because more carriers move toward the pixel electrode (not shown).

If the source electrode SE is connected to the pixel electrode (not shown) instead of the drain electrode DE, heat in the source region SA is generated at a higher temperature than the heat in the drain region DA. Will be

In addition, the heating rate for each region of the active layer ACT corresponds to a mobility of carriers in the active layer ACT, an amount of carriers in motion, and a distance from the channel region CA.

As shown in FIG. 4, in each of the source and drain regions SA and DA, the more the region is separated from the channel region CA by a longer separation distance ΔG, the lower the heating rate (Heating_SA, Heating_DA, The solid line and the thin dotted line) are decreased, and the heat dissipation rate (Cooling, shown by the thick solid line in Fig. 4) increases. Further, in a region spaced apart from the channel region CA by more than the critical separation distances Gth1 and Gth2, the heat dissipation rate (Cooling) is greater than the heating rate (Heating_SA, Heating_DA).

Accordingly, in order to use the first and second contact holes CT1 and CT2 and the source and drain electrodes SE and DE connected thereto as a more effective heat sink for heat dissipation of the active layer ACT, the first And a portion of each of the source and drain regions SA and DA exposed by the second contact holes CT1 and CT2 is spaced apart from the channel region CA by a threshold distance Gth1 and Gth2 or more.

Specifically, a portion of the source region SA exposed by the first contact hole CT1 is spaced apart from the channel region CA by a distance greater than or equal to the first critical separation distance Gth1. That is, the heat dissipation rate (Cooling) is higher than the heating rate (Heating_SA, shown by a thin dotted line in FIG. 4) by being spaced apart from the channel area (CA) by a distance greater than or equal to the first critical separation distance (Gth1) of the source area SA. In the region, a first contact hole CT1 and a source electrode SE connected to a part of the source region SA through the first contact hole CT1 are formed.

Accordingly, the first contact hole CT1 and the source electrode SE connected to a part of the source region SA through the first contact hole CT1 can be used as an effective heat sink for heat dissipation of the source region SA. It can prevent heat from accumulating.

Likewise, a portion of the drain region DA exposed by the second contact hole CT2 is spaced apart from the channel region CA by a distance greater than or equal to the second critical separation distance Gth2. That is, the heat dissipation rate (Cooling) is higher than the heating rate (Heating_DA, shown by a thin solid line in FIG. 4) by being spaced apart from the channel area (CA) by a distance greater than or equal to the second critical separation distance (Gth2) of the drain area DA. In the region, a second contact hole CT2 and a drain electrode DE connected to a portion of the drain region DA through the second contact hole CT2 are formed.

Accordingly, the second contact hole CT2 and the drain electrode DE connected to a portion of the drain region DA through the second contact hole CT2 can be used as an effective heat sink for heat dissipation of the drain region DA. It can prevent heat from accumulating.

In addition, as mentioned above, the drain region DA is connected to the pixel electrode (not shown), so that a larger amount of carriers is moved than the source region SA. Accordingly, even if the separation distance ΔG from the channel region CA is the same, the heating rate (Heating_DA) of the drain region (DA) is higher than the heating rate (Heating_SA) of the source region (SA). That is, the second critical separation distance Gth2 of the drain region DA is greater than the first critical separation distance Gth1 of the source region SA.

Therefore, a portion of the source region SA exposed by the first contact hole CT1 is spaced apart from the channel region CA by a first separation distance G1 equal to or greater than the first critical separation distance Gth1, and the drain region ( When a part of DA) exposed by the second contact hole CT2 is separated from the channel area CA by a second separation distance G2 equal to or greater than the second critical separation distance Gth2, the second separation distance G2 Is longer than the first separation distance G1.

In other words, the second contact hole CT2 is spaced farther from the channel area CA than the first contact hole CT1.

In this way, even if the drain region DA connected to the pixel electrode (not shown) generates heat at a higher heating rate than the source region SA, it can be radiated at the same or similar heat dissipation rate as the source region SA, It is possible to prevent heat from accumulating in the active layer ACT.

As described above, according to the exemplary embodiment of the present disclosure, in consideration of the fact that heat having a higher temperature than the source region SA is generated in the drain region DA connected to the pixel electrode (not shown), the drain region DA Silver is formed to have a wider width than the source region SA, and the second contact hole CT2 connecting the drain region DA and the drain electrode DE connects the source region SA and the source electrode SE. The first contact hole CT1 is further spaced apart from the channel area CA than the first contact hole CT1. Therefore, it is possible to prevent heat at a temperature higher than that of the source region SA from accumulating in the drain region DA.

In addition, according to an exemplary embodiment of the present disclosure, each of the first buffer layer 121, the first gate insulating layer 131, and the first interlayer insulating layer 141 surrounding the active layer ACT is an inorganic material such as SiNx and SiOy. Since it is formed of aluminum oxide (Al ₂ O ₃ ) having a higher thermal conductivity than the insulating material, heat generated in the active layer ACT can be diffused more rapidly to the surroundings.

Accordingly, since heat dissipation of the thin film transistor (TFT) being driven becomes easy, the reliability, life, and driving speed of the thin film transistor (TFT) and the thin film transistor array substrate 100 including the thin film transistor (TFT) can be improved.

Meanwhile, FIG. 2 illustrates that the planar shape of the gate electrode GE is a bar-shaped crossing the channel region CA of the active layer ACT, but the exemplary embodiment of the present disclosure is not limited thereto. .

That is, as shown in FIG. 5, the planar shape of the gate electrode GE' is a first bar crossing the channel region CA of the active layer ACT, and one side of the first bar. It may be a T-shaped including a second bar branching from and extending in a direction crossing the bar.

Alternatively, as shown in FIG. 6, the planar shape of the gate electrode GE" is a first bar crossing the channel region CA of the active layer ACT, and both sides of the first bar. It may be an I-shaped including second and third bars branching from and extending in a direction crossing the bar.

In this way, if the planar shape of the gate electrodes GE', GE" is T-type or I-type, the surface area of the gate electrode GE may be wider than that of the bar-type, and thus heat dissipation by the gate electrode GE This can be facilitated.

That is, as the width of the channel region CA increases, the threshold voltage of the thin film transistor TFT increases, so when the planar shape of the gate electrode GE is bar-shaped, it is limited to increase the surface area of the gate electrode GE. There is. However, when the gate electrodes GE', GE" become T-type or I-type, even if the width of the channel region CA is not increased and the width of the region allocated to the thin film transistor TFT is not greatly increased, The surface area of the gate electrodes GE', GE" may be slightly increased. As a result, the gate electrode GE is used as a more effective heat sink for heat dissipation of the active layer ACT while preventing an increase in the threshold voltage of the thin film transistor (TFT) and a decrease in the aperture ratio due to the thin film transistor (TFT). Can be.

Next, a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present disclosure will be described with reference to FIGS. 7 and 8A to 8G.

7 is a flowchart illustrating a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present application, and FIGS. 8A to 8G are process diagrams showing each step of FIG. 7.

As shown in FIG. 7, a method of manufacturing a thin film transistor according to an embodiment of the present application includes forming a light blocking layer 110 on the substrate 101 (S110), and the light blocking layer 110 on the substrate 101. ) Forming the buffer layer 120 covering (S120), forming an active layer ACT′ that at least partially overlaps the light blocking layer 110 on the buffer layer 120 (S130), and the active layer ACT Is divided into a channel region CA corresponding to the light blocking layer 110 and a source region SA and a drain region DA on both sides thereof, and the gate insulating layer 130 is formed on the channel region CA of the active layer ACT. ) And forming the gate electrode GE (S140), forming an interlayer insulating layer 140 covering the active layer ACT, the gate insulating layer 130 and the gate electrode GE on the buffer layer 120 ( S150, the interlayer insulating layer 140 is patterned to form a first contact hole CT1 exposing a portion of the source region SA, and a second contact hole CT2 exposing a portion of the drain region DA. Step S160, and forming the source and drain electrodes SE and DE on the interlayer insulating layer 140 (S170).

As shown in FIG. 8A, a light blocking layer 110 is formed on the substrate 101 (S110), and an insulating material is stacked on the entire surface of the substrate 101 to form the buffer layer 120. (S120).

The light blocking layer 110 corresponds to a part of each pixel area PA, and is formed to cover the channel area CA or the thin film transistor TFT. Alternatively, the light blocking layer 110 may be formed to further cover the outer periphery of each pixel area PA and further cover the gate line (GL of FIG. 1) and the data line (DL of FIG. 1 ).

The buffer layer 120 is formed as a single layer or multiple layers. In this case, the first buffer layer 121 of the buffer layer 120 in contact with the active layer ACT to be formed on the buffer layer 120 is formed of aluminum oxide (Al ₂ O ₃ ).

That is, the weapon, such as the buffer layer 120 is aluminum oxide (Al ₂ O ₃₎ The single layer, or aluminum oxide containing only the first buffer layer 121 (Al ₂ O ₃₎ the first buffer layer 121 and the SiNx, SiOy of It may be formed as a multilayer including the second buffer layer 122 made of an insulating material.

As shown in FIG. 8B, the semiconductor material layer stacked on the buffer layer 120 is patterned to form an active layer ACT'. (S130)

At this time, the active layer (ACT') can be formed in a low-temperature atmosphere compared to polysilicon, and is an oxide semiconductor having high carrier mobility and stable electrostatic characteristics compared to amorphous silicon (a-Si). Can be formed.

Exemplarily, the oxide semiconductor is AxByCzO(x, y, z ≥ 0), and each of A, B and C is selected from Zn, Cd, Ga, In, Sn, Hf, and Zr. For example, the oxide semiconductor may be any one of IGZO (In-Ga-Zn-Oxide), ITZO (In-Sn-Zn-Oxide), and IGO (In-Ga-Oxide).

Subsequently, by patterning at least one insulating material film (131 ′ and 132 ′ in FIG. 8C) and a metal film (133 in FIG. 8C) sequentially formed on the entire surface of the buffer layer 120, the gate insulating layer 130 and the gate electrode ( GE), and divides the active layer ACT into a channel region CA, a source region SA, and a drain region DA. (S140)

That is, as shown in FIG. 8C, at least one insulating material layer 131 ′ and 132 ′ and a metal layer 133 covering the active layer ACT′ are formed on the entire surface of the buffer layer 120.

At this time, of the at least one insulating material layer 131 ′ and 132 ′, the layer 132 ′ in contact with the metal layer 133 is made of aluminum oxide (Al ₂ O ₃ ).

As shown in FIG. 8D, the gate insulating layer 130 covering the channel region CA of the active layer ACT by simultaneously patterning at least one insulating material layer 131 ′ and 132 ′ and the metal layer 133. ) And a gate electrode GE on the gate insulating layer 130.

At the same time, the active layer ACT has a channel region CA overlapping the gate electrode GE with the gate insulating layer 130 interposed therebetween, and the source region SA and the drain region ( DA). Here, the source region SA is formed with a first width W1, and the drain region DA is formed with a second width W2 that is greater than the first width W1.

In addition, as shown in FIGS. 2, 5, and 6, the planar shape of the gate electrode GE is any one of a bar-shaped, T-shaped, and I-shaped. Can be

The gate insulating layer 130, a first gate insulating layer 131 of the first gate insulating layer 131, only a single layer, or aluminum oxide (Al ₂ O ₃₎ containing aluminum oxide (Al ₂ O ₃₎ and It may be formed as a multilayer including the second gate insulating layer 132 made of an inorganic insulating material such as SiNx, SiOy, or the like.

Subsequently, by using the gate insulating layer 130 and the gate electrode GE as a mask, impurities may be further implanted into the exposed source region SA and the drain region DA of the active layer ACT.

Next, as shown in FIG. 8E, by stacking at least one insulating material on the buffer layer 120, the interlayer insulating layer 140 covering the active layer ACT, the gate insulating layer 130, and the gate electrode GE. ) To form. (S150)

An interlayer insulating layer 140 is the first interlayer insulating layer 141, the first interlayer insulating layer 141, only a single layer, or aluminum (Al ₂ O ₃₎ oxide including an aluminum oxide (Al ₂ O ₃₎ and SiNx, It may be formed as a multilayer including the second interlayer insulating layer 142 made of an inorganic insulating material such as SiOy.

As shown in FIG. 8F, a first contact hole CT1 exposing a part of the source region SA and a second contact exposing a part of the drain region DA by patterning the interlayer insulating layer 140 A hole CT2 is formed. (S160)

At this time, a portion of the source region SA exposed by the first contact hole CT1 is spaced apart from the channel region CA by a first separation distance G1, and a second contact hole CT2 of the drain region DA A portion exposed by) is spaced apart from the channel area CA by a second separation distance G2 that is longer than the first separation distance G1.

As shown in FIG. 8G, a metal film (not shown) on the interlayer insulating layer 140 is patterned to form a source electrode SE connected to the source region SA through a first contact hole CT1, and 2 A drain electrode DE connected to the drain region DA through the contact hole CT2 is formed. (S170)

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes are possible within the scope of the technical spirit of the present invention. It will be obvious to those who have the knowledge of.

100: thin film transistor array substrate
GL: gate line DL: data line
TFT: thin film transistor
ACT: active layer CA: channel region
SA: source region DA: drain region
CT1, CT2: first and second contact holes
W1: width of source region W2: width of drain region
G1, G2: separation distance from channel area (CA)
GE, GE', GE": gate electrode
SE: source electrode DE: drain electrode
101: substrate 110: light blocking layer
120: buffer layer 130: gate insulating layer
140: interlayer insulating layer
Heating_SA: Heating rate in the source area
Heating_DA: Heating rate in the drain area
Cooling: Radiation speed

Claims (15)

In the thin film transistor array substrate comprising a plurality of thin film transistors corresponding to a plurality of pixel regions,
Each of the thin film transistors
A buffer layer formed on the substrate;
An active layer formed on the buffer layer and including a channel region and a source region and a drain region on both sides of the channel region;
A gate insulating layer formed to cover the channel region;
A gate electrode formed on the gate insulating layer;
An interlayer insulating layer formed to cover the active layer, the gate insulating layer, and the gate electrode;
A source electrode formed on the interlayer insulating layer and connected to the source region; And
A drain electrode formed on the interlayer insulating layer and connected to the drain region,
In the source region and the drain region into which impurities are implanted in the active layer, the drain region has a second width greater than the first width of the source region
A thin film transistor array substrate in which a contact area between the drain region of the active layer and the buffer layer and the interlayer insulating layer is larger than a contact area between the source region of the active layer and the buffer layer and the interlayer insulating layer. The method of claim 1,
Each of the thin film transistors
A first contact hole passing through the interlayer insulating layer to expose at least a portion of the source region; And
Further comprising a second contact hole penetrating the interlayer insulating layer so as to expose at least a portion of the drain region,
The source electrode is connected to the source region through the first contact hole,
The drain electrode is connected to the drain region through the second contact hole,
The source region connected through the first contact hole and the contact portion of the source electrode are spaced apart from the channel region by a first distance,
A thin film transistor array substrate, wherein the contact portions of the drain region and the drain electrode connected through the second contact hole are spaced apart from the channel region by a second separation distance longer than the first separation distance. The method of claim 1,
The planar shape of the gate electrode is any one of a bar-shaped, T-shaped, and I-shaped thin film transistor array substrate. The method of claim 1,
A thin film transistor array substrate further comprising a light blocking layer formed between the substrate and the buffer layer to correspond to at least the channel region. The method of claim 4,
The buffer layer is a thin film transistor array substrate formed of a single layer including a first buffer layer made of aluminum oxide (Al ₂ O ₃ ) in contact with the lower portion of the active layer, or a multi-layer including at least the first buffer layer. The method of claim 1,
The gate insulating layer is a thin film transistor formed of a single layer including a first gate insulating layer made of aluminum oxide (Al ₂ O ₃ ) in contact with the upper portion of the channel region, or a multi-layer including at least the first gate insulating layer Array substrate. The method of claim 1,
The interlayer insulating layer is formed of a single layer including a first interlayer insulating layer made of aluminum oxide (Al ₂ O ₃ ) in contact with each of the source region and the drain region, or a multi-layer including at least the first interlayer insulating layer Thin film transistor array substrate. In the method of manufacturing a thin film transistor array substrate including a plurality of thin film transistors corresponding to a plurality of pixel regions,
Forming a light blocking layer on the substrate;
Forming a buffer layer on the substrate to cover the light blocking layer;
Forming an active layer on the buffer layer and at least partially overlapping the light blocking layer;
Forming a gate insulating layer on the channel region of the active layer corresponding to the light blocking layer, and forming a gate electrode on the gate insulating layer;
Implanting impurities into both sides of the channel region of the active layer to form a source region and a drain region;
Forming an interlayer insulating layer on the buffer layer, covering the active layer, the gate insulating layer, and the gate electrode;
Forming a first contact hole exposing at least a portion of the source region and a second contact hole exposing at least a portion of the drain region by patterning the interlayer insulating layer; And
Forming a source electrode connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole, on the interlayer insulating layer,
In the source region and the drain region into which impurities are implanted in the active layer, the drain region has a second width greater than the first width of the source region
A method of manufacturing a thin film transistor array substrate in which a contact area between the drain region of the active layer and the buffer layer and the interlayer insulating layer is larger than a contact area between the source region of the active layer and the buffer layer and the interlayer insulating layer. The method of claim 8,
In the step of forming the first and second contact holes,
The source region connected through the first contact hole and the contact portion of the source electrode are spaced apart from the channel region by a first distance,
A method of manufacturing a thin film transistor array substrate, wherein the contact portions of the drain region and the drain electrode connected through the second contact hole are spaced apart from the channel region by a second separation distance longer than the first separation distance. The method of claim 8,
In the step of forming the gate electrode,
The planar shape of the gate electrode is any one of a bar-shaped, T-shaped, and I-shaped thin film transistor array substrate. The method of claim 8,
In the step of forming the buffer layer,
The buffer layer is formed of a single layer including a first buffer layer made of aluminum oxide (Al ₂ O ₃ ), or a multilayer including at least the first buffer layer,
The first buffer layer is a method of manufacturing a thin film transistor array substrate in contact with the lower portion of the active layer. The method of claim 8,
In the step of forming the gate insulating layer,
The gate insulating layer is formed of a single layer including a first gate insulating layer made of aluminum oxide (Al ₂ O ₃ ), or a multilayer including at least the first gate insulating layer,
The first gate insulating layer is a method of manufacturing a thin film transistor array substrate in contact with an upper portion of the channel region. The method of claim 12,
Forming the gate insulating layer and the gate electrode comprises:
Stacking an insulating material film of aluminum oxide (Al ₂ O ₃ ) and a metal film on the entire surface of the buffer layer;
Patterning the insulating material film and the metal film to form the gate insulating layer corresponding to the channel region of the active layer and including the first gate insulating layer, and the gate electrode on the gate insulating layer. and,
The forming of the source region and the drain region of the active layer comprises:
And forming the source region and the drain region by implanting the impurities into a region of the active layer exposed to both sides of the channel region using the gate insulating layer and the gate electrode as masks Method of manufacturing. The method of claim 8,
In the step of forming the interlayer insulating film,
The interlayer insulating layer is formed of a single layer including a first interlayer insulating layer made of aluminum oxide (Al ₂ O ₃ ), or a multilayer including at least the first interlayer insulating layer,
The first interlayer insulating layer is a method of manufacturing a thin film transistor array substrate in contact with each of the source region and the drain region. delete

Images