JP2000294662A - Nonvolatile semiconductor memory element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the structure of a nonvolatile semiconductor memory to be injected with charge from a gate electrode and the manufacture method, and raise the yield, by forming the oxide of gate electrode material on the surface of the gate electrode of a memory transistor, and adding compressive stress to the interface between a channel region and a gate insulating film. SOLUTION: A nonvolatile semiconductor memory element includes a semiconductor consisting of a channel region and source and drain regions containing impurities to serve as a donor or an acceptor, and a transistor having at least a gate insulating film 4, a gate electrode 5, and source and drain electrodes 10 and 11. This is a nonvolatile semiconductor memory element which works as a memory by injecting the gate insulating film 4 with charge from the semiconductor layer or the gate electrode 5. Moreover, it is put in such a condition that carrier is easy to be injected into the gate insulating film by adding compressive stress to the interface between the channel region and the gate insulating film, by forming the oxide of the gate electrode material on the surface of the gate electrode 5 of the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a writable and erasable nonvolatile semiconductor memory device for various recording applications and a method of manufacturing the same.

[0002]

2. Description of the Related Art Heretofore, as a conventional nonvolatile semiconductor memory device, MNOS (Metal Nitride Oxide Semiconductor) has been used.
r) to EPROM (Erasable and Programmable Read On)
An example of application to ly memory will be described with reference to the drawings.

In recent years, in the field of electrically writable and erasable nonvolatile semiconductor memory devices, the MNOS type is mainly used. For example, the physics of VLSI devices (Maruzen Co., Masatake Kishino, Mitsumasa Koyanagi, pp189-19
FIG. 4 shows a conventional example of the MNOS type EPROM described in 4).
This will be briefly described with reference to FIG. A thin SiO ₂ film 17 of 1 to ₄ nm and a thick Si ₃ N capable of directly tunneling electrons
The double layer of the _four films 18 is used as a gate insulating film. The stored information is written by injecting carriers into traps spread on the SiO ₂ —Si ₃ N ₄ interface and the Si ₃ N ₄ side. That is, the p-well 16 and the source electrode 21 of the memory cell are grounded, a high positive voltage Vp is applied to the gate electrode 19-1, electrons are injected from the channel into the insulating film, and SiO ₂ —Si ₃ N ₄ Electrons are captured by a trap spread on the interface and on the Si ₃ N ₄ side.
Since the trap that has captured the electrons is negatively charged, the threshold voltage shifts in the positive direction. When erasing the written information, the gate electrode 19-1 is grounded, Vp is applied to the p-well 16, holes are injected from the p-well into the insulating film, and the holes are captured.

For erasing stored information, carriers trapped in a trap are released to the substrate or gate electrode 19 side, or
Alternatively, the injection is performed by injecting carriers of the opposite conductivity type. As a result, the holes neutralize the electrons trapped in the traps in the insulating film by writing, so that the threshold voltage shifts in the negative direction.

At the time of reading, a voltage Vr for turning on the gate 19-2 of the switching transistor is applied, and a reading potential is applied to the source electrode 21. If the memory transistor is written, the memory transistor is turned off. When the information "0" is not written to the drain of the switching transistor and the memory transistor is not written, the memory transistor is turned on, and the information "1" is read to the drain 22 of the switching transistor.

[0006]

The conventional EP shown in FIG.
In ROM, the gate insulating film is SiO ₂
And a double layer of Si ₃ N ₄ and the switching transistor is S
It is more of iO _2. Therefore, there is a problem that not only the structure becomes complicated, but also the manufacturing process becomes complicated, and the yield becomes low. In addition, in the conventional example, since an expensive single-crystal silicon substrate is used as a substrate, the present invention also has a problem that the manufacturing cost is increased. It is an object of the present invention to provide an inexpensive nonvolatile semiconductor memory device and a method for manufacturing the same.

[0007]

In order to solve these problems, the inventors of the present invention have conducted various studies. As a result, the stress applied to the interface between the semiconductor and the gate insulating film of a thin film transistor using a glass substrate as a substrate is reduced. It has been found that by controlling the stress, a state in which carriers can be easily injected into the gate insulating film can be created. Accordingly, the nonvolatile semiconductor memory element of the present invention includes a transistor having at least a channel region, a semiconductor layer including source and drain regions containing impurities serving as donors or acceptors, a gate insulating film, a gate electrode, and a source and drain electrode. A nonvolatile semiconductor memory element which functions as a memory by injecting electric charge from a semiconductor layer or a gate electrode into a gate insulating film of the transistor, wherein an oxide of the gate electrode material is formed on a surface of the gate electrode of the memory transistor. By being formed, a compressive stress is applied to the interface between the channel region and the gate insulating film, and a nonvolatile semiconductor memory device having a simple structure, a high yield, and a low manufacturing cost can be provided. And

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a semiconductor layer comprising a channel region, source and drain regions containing impurities serving as donors or acceptors, a gate insulating film, a gate electrode, and source and drain electrodes are formed. A method for manufacturing a non-volatile semiconductor memory device including a transistor having at least a transistor and injecting electric charge from a semiconductor layer or a gate electrode into a gate insulating film of the transistor to act as a memory, wherein the gate electrode is formed of molybdenum. Selectively forming a metal film containing at least one metal selected from the group consisting of tantalum, aluminum and tungsten, and oxidizing the surface of the metal film.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory device according to claim 1 of the present invention has a semiconductor layer comprising a channel region, a source and a drain region containing impurities serving as donors or acceptors, a gate insulating film, a gate electrode and a source. And a transistor having at least a drain electrode, a non-volatile semiconductor memory element that acts as a memory by injecting electric charge from a semiconductor layer or a gate electrode into a gate insulating film of the transistor, Is characterized in that an oxide of the gate electrode material is formed to apply a compressive stress to the interface between the channel region and the gate insulating film. The structure is simple, so the yield is high, and the manufacturing cost is low. Has the function of providing a simple nonvolatile semiconductor memory device.

According to a second aspect of the present invention, there is provided the nonvolatile semiconductor memory element according to the first aspect, wherein the gate electrode contains at least one metal selected from molybdenum, tantalum, aluminum and tungsten. Since a metal having a low resistance is used, it is suitable for miniaturization and has an effect that higher density and higher integration can be easily achieved.

According to a third aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a semiconductor layer comprising a channel region, source and drain regions containing impurities serving as donors or acceptors, a gate insulating film, a gate electrode, and source and drain electrodes. Including at least two transistors,
One of the two transistors operates as a switching transistor, and the other is a nonvolatile semiconductor memory element operating as a memory transistor, and an oxide of the gate electrode material is formed on a surface of a gate electrode of the memory transistor. A compressive stress is applied to the interface between the channel region and the gate insulating film, and the nonvolatile memory includes a switching transistor and a memory transistor. This has the function of providing a highly reliable nonvolatile semiconductor memory element.

According to a fourth aspect of the present invention, there is provided the nonvolatile semiconductor memory element according to the third aspect, wherein the gate electrode contains at least one metal selected from molybdenum, tantalum, aluminum and tungsten. Since a metal having a low resistance is used, it is suitable for miniaturization and has an effect that higher density and higher integration can be easily achieved.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, comprising: a semiconductor layer comprising a channel region and source and drain regions containing impurities serving as donors or acceptors; a gate insulating film; a gate electrode; A method for manufacturing a nonvolatile semiconductor memory element including a transistor having at least a drain electrode, and acting as a memory by injecting electric charge from a semiconductor layer or a gate electrode into a gate insulating film of the transistor, wherein the gate electrode is a gate electrode. The method includes a step of selectively depositing and forming an electrode material and a step of oxidizing the surface of the gate electrode, thereby providing a method of manufacturing a nonvolatile semiconductor memory device with a high yield in a simple manufacturing process. Having.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device according to the seventh aspect, wherein the gate electrode comprises at least one of molybdenum, tantalum, aluminum and tungsten. A step of selectively depositing and forming a metal film containing at least one type of metal, and a step of oxidizing the surface of the metal film. This has the effect of enabling a method of manufacturing a nonvolatile semiconductor memory element suitable for high density and high integration.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, comprising: a semiconductor layer comprising a channel region and source and drain regions containing impurities serving as donors or acceptors; a gate insulating film; a gate electrode; A method for manufacturing a non-volatile semiconductor memory device including two transistors having at least a drain electrode, wherein one of the two transistors operates as a switching transistor, and the other has a cell to be a memory transistor. The electrode includes at least a step of selectively forming a gate electrode material and a step of oxidizing the surface of the gate electrode. Since the nonvolatile memory includes a switching transistor and a memory transistor, reading of the memory is performed. Operation is reliable We, an effect that can be provided a method of manufacturing more operations reliable nonvolatile semiconductor memory device.

According to a eighth aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device according to the seventh aspect, wherein the gate electrode of the memory transistor has molybdenum, tantalum, aluminum, A step of selectively depositing a metal film containing at least one kind of metal of tungsten; and a step of oxidizing the surface of the metal film. It has an effect that a method for manufacturing a nonvolatile semiconductor memory element suitable for high integration and high density and high integration can be performed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a process sectional view for explaining a nonvolatile semiconductor memory device and a method of manufacturing the same according to a first embodiment of the present invention.

On a substrate 1 (# 1737 glass manufactured by Corning Incorporated) having a SiO ₂ film as a buffer layer 2 for preventing diffusion of impurities in a glass substrate, a thickness of 30 to 20 is applied.
An island-shaped poly-Si3 of 0 nm is formed (FIG. 1A).

Here, since a glass substrate is used for poly-Si3, the glass substrate is inexpensive, but the heat resistance is not so high. Therefore, boron is first formed after forming amorphous Si to adjust the threshold voltage. Was implanted and crystallized by excimer laser annealing to form poly-Si3.

Then, for example, after depositing SiO ₂ to be the gate insulating layer 4 to a thickness of 100 nm over the entire surface by a normal pressure CVD method, the gate electrode 5 is formed using, for example, a MoW alloy. Since Mo alone has weak acid resistance to the acid used in the cleaning step, W was added. In this example, the W concentration is about 15%, but the concentration can be changed as appropriate.

Then, a plasma of diborane (B ₂ H ₆ ) diluted with hydrogen is generated, and the acceleration voltage is set to 70 k without performing mass separation.
Ion doping is performed under the condition that the total dose is 1 × 10 ¹⁵ cm ^{−2 and} the p ⁺ region 6 serving as a source region and a drain region is formed (FIG. 1B).

Thereafter, a heat treatment was performed at 450 ° C. for 15 minutes in an air atmosphere to form an oxide film 7 on the surface of the MoW gate electrode (FIG. 1C).

SiO ₂ is deposited on the entire surface as an interlayer insulating layer 8 by a normal pressure CVD method, then a contact hole 9 is formed, and for example, aluminum (Al) is sputtered as a source electrode 10 and a drain electrode 11. Then, by patterning by photolithography and etching, a nonvolatile semiconductor memory element composed of a p-channel thin film transistor is completed (FIG. 1D).

Next, the operation will be described. FIG. 2 shows the gate voltage dependence of the drain current of the thin film transistor formed according to the above (Embodiment 1) and the voltage after applying, for example, -20 V to the gate of the thin film transistor to inject holes into the gate insulating film. 4 shows the gate voltage dependence of the drain current. The threshold voltage is largely negatively shifted by hole injection.

Therefore, for example, when the gate voltage is set to 0 V, this thin film transistor is in an ON state before hole injection and is in an OFF state after hole injection. This difference is used as a memory. To erase the injected holes, a method such as application of a positive voltage to the gate, heat treatment, and irradiation of ultraviolet light from the back surface of the substrate to the channel region if the substrate transmits ultraviolet light such as glass can be used. it can.

In the above (Embodiment 1), a glass substrate is used as the substrate. However, the substrate is not specified, and for example, a quartz substrate, a sapphire substrate, a single-crystal silicon substrate, another type of glass substrate, etc. Can also be used. In addition, although poly-Si is used as the semiconductor, a compound semiconductor such as amorphous Si, single crystal Si, or SiGe may be used. In addition, although SiO ₂ by normal pressure CVD was used as the gate insulating film, this method does not specify a deposition method or a material. Therefore, another CVD method such as plasma CVD or LPCVD or a thermal oxide film can be used. It is. However, when a glass substrate is used as the substrate, it is inexpensive but has poor heat resistance, so that a thermal oxide film cannot be used under conditions that substantially increase the substrate temperature. Although the MoW alloy material is used for the gate electrode, other materials such as molybdenum, tantalum, aluminum, tungsten, alloy materials thereof, and poly-Si containing a large amount of impurities can also be used. A point to be noted about the gate insulating film and the gate electrode material is that it is important to apply a compressive stress by oxidizing the gate electrode, and it is not preferable to use a material having a high tensile stress or a deposition method. is there.

In the above (Embodiment 1), Mo
Although the surface of the W alloy is thermally oxidized, for example, when Al, Ta, or an alloy thereof is used as the gate electrode material, anodic oxidation or the like can be used.

Further, although SiO _{2 formed} by the normal pressure CVD method is used as the interlayer insulating layer 8, the plasma C using TEOS is used.
SiO ₂ or LTO (Low Temperature Oxid) by VD method
e), needless to say, SiO ₂ or the like by ECR-CVD may be used. In addition, silicon nitride, tantalum oxide, aluminum oxide, or the like can be used as a material, and a stacked structure of these thin films may be used. Further, as a material of the source electrode 10 and the drain electrode 11, Al
However, a metal such as tantalum (Ta), molybdenum (Mo), chromium (Cr), titanium (Ti) or an alloy thereof may be used, or poly containing a large amount of impurities may be used.
A transparent conductive layer such as -Si or poly-SiGe alloy or ITO may be used.

Although a P-channel transistor is formed by using boron as an impurity, arsenic or the like serving as an acceptor may be used similarly, or an N-channel transistor may be formed by using phosphorus or aluminum serving as a donor as an n-type transistor. A transistor may be formed.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

(Embodiment 2) FIG. 3 is a process sectional view for explaining a nonvolatile semiconductor memory device and a method of manufacturing the same according to a second embodiment of the present invention.

On a substrate 1 (# 1737 glass manufactured by Corning Incorporated) on which an SiO ₂ film is applied as a buffer layer 2 for preventing diffusion of impurities in a glass substrate, a thickness of 30 to 20 is applied.
An 0-nm island-shaped poly-Si3 is formed (FIG. 3A).

Here, since a glass substrate is used for poly-Si3, the glass substrate is inexpensive, but does not have high heat resistance. Therefore, boron is first formed after forming amorphous Si to adjust the threshold voltage. Was implanted and crystallized by excimer laser annealing to form poly-Si3.

Then, for example, after depositing SiO ₂ to be the gate insulating layer 4 to a thickness of 100 nm over the entire surface by a normal pressure CVD method, the gate electrode 5 is formed using, for example, a MoW alloy. Since Mo alone has weak acid resistance to the acid used in the cleaning step, W was added. In this example, the W concentration is about 15%, but the concentration can be changed as appropriate.

Then, a plasma of hydrogen-diluted diborane (B ₂ H ₆ ) is generated, and the acceleration voltage is set to 70 k without performing mass separation.
Ion doping is performed at a total dose of 1 × 10 ¹⁵ cm ⁻² at V to form ap ⁺ region 6 serving as a source region and a drain region (FIG. 3B).

[0037] Thereafter, the plasma C the SiN _X antioxidant mask 12 on the gate electrode of the switching transistor
After the formation by the VD method, an oxide film 7 was formed on the surface of the MoW gate electrode by performing a heat treatment at 450 ° C. for 15 minutes in an air atmosphere (FIG. 3C).

Thereafter, the antioxidant mask is removed, and then SiO ₂ is deposited on the entire surface as an interlayer insulating layer 8 by a normal pressure CVD method, and then a contact hole 9 is formed.
By depositing, for example, aluminum (Al) as the 0 and drain electrodes 11 by sputtering, and then patterning by photolithography etching, a p-channel memory thin film transistor 13
And a switching thin film transistor 14 are completed (FIG. 3D).

Next, the operation will be described. Although not shown, the memory thin film transistor 13 shows the same gate voltage dependence of the drain current as in the above (Embodiment 1), and the threshold voltage shifts significantly negatively by hole injection in the same manner.

Therefore, for example, when the gate voltage is set to 0 V, this thin film transistor is in an ON state before hole injection and is in an OFF state after hole injection. This difference is used as a memory. In the second embodiment, since the switching thin film transistor 14 is added for reading the memory, an electrical load is not applied to the memory thin film transistor 13 when reading the memory. That is, at the time of reading, the gate of the switching thin film transistor 14 is turned on.
And a read potential is applied to the source electrode 1.
0, the memory thin film transistor 13 is turned off when the memory thin film transistor 13 is written, and the drain electrode 1 of the switching thin film transistor is turned off.
When “0” information is not written in the memory thin film transistor 13, the memory transistor 13 is turned on and the switching thin film transistor 14 is turned on.
"1" information is read out to the drain of.

In order to erase the injected holes, a positive voltage is applied to the gate electrode of the memory thin film transistor 13 and heat treatment is performed, as in the first embodiment. A technique such as ultraviolet light irradiation from the back surface to the channel region can be used.

In the above (Embodiment 2), a glass substrate is used as a substrate. However, the substrate is not specified, and for example, a quartz substrate, a sapphire substrate, a single-crystal silicon substrate, another type of glass substrate, etc. Can also be used. In addition, although poly-Si is used as the semiconductor, a compound semiconductor such as amorphous Si, single crystal Si, or SiGe may be used. In addition, although SiO ₂ by normal pressure CVD was used as the gate insulating film, this method does not specify a deposition method or a material. Therefore, another CVD method such as plasma CVD or LPCVD or a thermal oxide film can be used. It is. However, when a glass substrate is used as the substrate, it is inexpensive but has poor heat resistance, so that a thermal oxide film cannot be used under conditions that substantially increase the substrate temperature. Although the MoW alloy material is used for the gate electrode, other materials such as molybdenum, tantalum, aluminum, tungsten, alloy materials thereof, and poly-Si containing a large amount of impurities can also be used. A point to be noted about the gate insulating film and the gate electrode material is that it is important to apply a compressive stress by oxidizing the gate electrode, and it is not preferable to use a material having a high tensile stress or a deposition method. is there.

In the above (Embodiment 2), Mo
Although the surface of the W alloy is thermally oxidized, for example, when Al, Ta, or an alloy thereof is used as a gate electrode material, anodic oxidation or the like can be used. Therefore, a photoresist is used as an oxidation prevention mask for a switching thin film transistor. You can also. Further, another material can be used as a gate electrode material of the thin film transistor for switching. When a different material is used, if a material having a different oxidation temperature, for example, Ta is selected, the material is not oxidized by the heat treatment at about 450 ° C., so that there is no need to use an oxidation prevention mask.

Further, although SiO _{2 formed} by the normal pressure CVD method is used as the interlayer insulating layer 8, the plasma C using TEOS is used.
SiO ₂ or LTO (Low Temperature Oxid) by VD method
e), needless to say, SiO ₂ or the like by ECR-CVD may be used. In addition, silicon nitride, tantalum oxide, aluminum oxide, or the like can be used as a material, and a stacked structure of these thin films may be used. Further, as a material of the source electrode 10 and the drain electrode 11, Al
However, a metal such as tantalum (Ta), molybdenum (Mo), chromium (Cr), titanium (Ti) or an alloy thereof may be used, or poly containing a large amount of impurities may be used.
A transparent conductive layer such as -Si or poly-SiGe alloy or ITO may be used.

Although a P-channel transistor is formed by using boron as an impurity, arsenic or the like serving as an acceptor may be used similarly, or an N-channel transistor may be formed by using phosphorus or aluminum serving as a donor as an n-type transistor. A transistor may be formed.

[0046]

As described above, according to the nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention, the nonvolatile semiconductor memory device can be manufactured with a simple structure at a high yield and at low cost.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of each of main processes for describing a nonvolatile semiconductor memory device and a method of manufacturing the same according to a first embodiment of the present invention;

FIG. 2 shows a gate voltage dependency of a drain current of a thin film transistor constituting a nonvolatile semiconductor memory device according to a first embodiment of the present invention, and a voltage of −20 V is applied to a gate of the thin film transistor to gate a hole. Diagram showing gate voltage dependence of drain current after injection into insulating film

FIG. 3 is a schematic cross-sectional view showing main steps for describing a nonvolatile semiconductor memory device and a method of manufacturing the same according to a second embodiment of the present invention;

FIG. 4 shows an MNO as a conventional nonvolatile semiconductor memory device.
Schematic sectional view for explaining an S-type EPROM

[Explanation of symbols]

REFERENCE SIGNS LIST 1 glass substrate 2 buffer layer 3 poly-Si 4 gate insulating film 5 gate electrode 6 p + region 7 MoW oxide film 8 interlayer insulating film 9 contact hole 10 source electrode 11 drain electrode 12 antioxidant mask 13 memory thin film transistor 14 switching thin film transistor 15 n-type Si substrate 16 P well 17 SiO ₂ 18 Si ₃ N ₄ 19-1 Gate electrode 19-2 Gate electrode 20 n + region 21 Source electrode 22 Drain electrode 23 MNOS memory transistor 24 Switching transistor

Continued on the front page F term (reference) 5F001 AA16 AB02 AC02 AD12 AD41 AD70 AE02 AE08 AG02 AG12 AG21 5F083 EP17 EP22 EP33 ER11 ER21 ER25 ER30 GA27 GA28 HA02 HA06 JA36 JA39 PR12 PR33 PR36

Claims (8)

[Claims] 1. A transistor having at least a channel region, a semiconductor layer including source and drain regions containing an impurity serving as a donor or an acceptor, a gate insulating film, a gate electrode, and a source and drain electrode. A non-volatile semiconductor memory device that acts as a memory by injecting charges from a semiconductor layer or a gate electrode into the transistor, wherein an oxide of the gate electrode material is formed on a surface of a gate electrode of the transistor. A non-volatile semiconductor memory device, wherein a compressive stress is applied to a region and an interface of the gate insulating film. 2. The non-volatile semiconductor memory device according to claim 1, wherein the gate electrode contains at least one metal selected from the group consisting of molybdenum, tantalum, aluminum, and tungsten. 3. A transistor comprising: a channel region; a semiconductor layer including source and drain regions containing impurities serving as donors or acceptors; a gate insulating film; a gate electrode; and two transistors having at least source and drain electrodes. One operates as a switching transistor and the other operates as a memory transistor, and the oxide of the gate electrode material is formed on a surface of a gate electrode of the memory transistor. And a compressive stress applied to an interface of the gate insulating film. 4. The non-volatile semiconductor memory device according to claim 3, wherein the gate electrode of the memory transistor includes at least one metal selected from the group consisting of molybdenum, tantalum, aluminum, and tungsten. 5. A transistor having at least a channel region, a semiconductor layer including source and drain regions containing an impurity serving as a donor or an acceptor, a gate insulating film, a gate electrode, and a transistor having at least a source and a drain electrode. A method for manufacturing a nonvolatile semiconductor memory element that acts as a memory by injecting electric charge from a semiconductor layer or a gate electrode therein,
A method for manufacturing a nonvolatile semiconductor memory device, comprising: a step of selectively forming a gate electrode material on the gate electrode; and a step of oxidizing a surface of the gate electrode. 6. The gate electrode, wherein the gate electrode selectively forms a metal film containing at least one metal of molybdenum, tantalum, aluminum, and tungsten, and oxidizes a surface of the metal film. 6. The method according to claim 5, comprising at least steps. 7. A transistor comprising: a channel region; a semiconductor layer including source and drain regions containing impurities serving as donors or acceptors; a gate insulating film; a gate electrode; and two transistors having at least source and drain electrodes. One of which operates as a switching transistor, and the other is a method of manufacturing a nonvolatile semiconductor memory element having a cell to be a memory transistor, wherein the gate electrode of the memory transistor selectively forms a gate electrode material; And a method of oxidizing the surface of the gate electrode. 8. A step of selectively forming a gate electrode of the memory transistor on a metal film containing at least one metal selected from the group consisting of molybdenum, tantalum, aluminum, and tungsten; The method for manufacturing a nonvolatile semiconductor memory device according to claim 7, further comprising a step of oxidizing the non-volatile semiconductor memory device.