CN101424723A - Optimizing method based on four-needle flying-needle test path - Google Patents
Optimizing method based on four-needle flying-needle test path Download PDFInfo
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- CN101424723A CN101424723A CNA2008103061980A CN200810306198A CN101424723A CN 101424723 A CN101424723 A CN 101424723A CN A2008103061980 A CNA2008103061980 A CN A2008103061980A CN 200810306198 A CN200810306198 A CN 200810306198A CN 101424723 A CN101424723 A CN 101424723A
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Abstract
The invention relates to a circuit testing technology, in particular to an optimizing method based on a four-needle flying testing path. Aiming at solving the defects of the prior art, the invention provides the optimizing method which reduces testing times and the testing path and is based on the four-needle flying testing path. The invention has the technical proposal that after testing point information is extracted, testing points are divided to generate a positive testing point assembly and a positive testing point assembly and are matched after bidimensional arrangement once, the second bidimensional arrangement is carried out after being matched to generate an initial testing queue divided by using N rows as a subqueue, each subqueue adopts a shortest path interpolation method to new subqueues, and every two new subqueues are connected end to end to finally generate the testing path. The invention has the advantages that the testing times are reduced, the testing path is reduced, and consequently, the testing efficiency is increased.
Description
Technical field
The present invention relates to Circuit Measurement Technology, relate in particular to a kind of optimization method based on four-needle flying-needle test path.
Background technology
At present, external many manufacturers have obtained very big progress at aspects such as the design of printed circuit board (PCB) (be called for short PCB) and manufacturability analysis.Progress along with microelectric technique, the component placement increase in density, walking distance between centers of tracks constantly dwindles, complexity constantly increases, the monolithic pcb board test duration reaches a few hours, even several days, by the PCB on-line testing of manually finishing with the electric circuit inspection pilot is set, more and more can not satisfy the requirement of production, greatly influence the production cycle of product.Domestic PCB Production manufacturer is also working hard aspect the test path optimization in order to improve testing efficiency, but the effect that obtains is not very desirable.
The test path file of flying probe tester is the core of flying probe tester, it directly determines the testing time and the test path distance of test machine, just can improve test speed as long as reduce testing time with the length of dwindling test path, the shortening production cycle also reduces production costs.
At present, for test path optimization, main employing is that tabu search algorithm comes solving-optimizing on commercial Application, though the general easy realization of this algorithm, and understand easily, the field structure and just separating but its search performance places one's entire reliance upon especially can be absorbed in local minimum and can't guarantee global optimization, is difficult to guarantee that it optimizes efficient.Because in the flying probe path optimization, the path line number is capable to hundreds of thousands from tens row, span is very big, taking to set it just separates and reaches preferably test path with field structure to optimize effect be difficult the realization, and can't restrain, optimize the extremely low situation of efficient and take place along with algorithm may appear in constantly being increased in of test point quantity in the optimizing process, thereby can't arrive desirable optimization degree and efficient, increase the test duration to a certain extent, cause testing efficiency low; Also be because the flying needle path testing of prior art does not match to test point, cause the very long line number of promptly testing of test path a lot, also increased the test duration.
Summary of the invention
Technical matters to be solved by this invention is: propose a kind of optimization method based on four-needle flying-needle test path that reduces testing time and test path at the deficiencies in the prior art.
The technical scheme that the present invention solves the problems of the technologies described above employing is: the optimization method based on four-needle flying-needle test path may further comprise the steps:
A. read in the IPC356 formatted file, extract test point information and adjacent networks information;
B. add up the number of consolidated network number same test sign same test point, obtain the reverse side test point and count, positive test point is counted, and the through hole test point is counted;
C. according to the size that positive test point is counted, the reverse side test point is counted, the through hole test point according to making positive test point count and the count mode of difference minimum of reverse side test point is divided, is generated positive test point set and reverse side test point and gathers;
D. respectively positive test point set and the set of reverse side test point are carried out sorting based on the two dimension of X coordinate and Y coordinate, generate positive test point formation and the formation of reverse side test point;
E. positive test point formation and the formation of reverse side test point are matched respectively:
E1. when positive test point queue length and reverse side test point queue length all greater than 0 the time, positive test point formation, the formation of reverse side test point are all adopted and are got two and go out one, get two and go out two modes and alternately fall out and match, generate formation of positive test point row and the formation of reverse side test point row;
E2. when reverse side test point queue length is 0, take positive test point formation to get two and go out a mode and match, generate the formation of positive test point row;
E3. when positive test point queue length is 0, take the formation of reverse side test point to get two and go out a mode and match, generate the formation of reverse side test point row;
F. respectively formation of positive test point row and the formation of reverse side test point row are matched, take to get two and go out two modes and go pairing;
G. all test points are carried out sorting based on the two dimension of X coordinate and Y coordinate, generate an initial test queue;
H. this test queue is divided in the mode of a subqueue of N behavior;
I. adopt the shortest path method of interpolation to generate new subqueue to each subqueue;
J. to the head and the tail connection between any two of new subqueue, finally generate test path.
Among the described step h, be that test queue is divided in the mode of a subqueue of 5000 behaviors
Beneficial effect of the present invention: reduce testing time, dwindle test path, and then improved testing efficiency.
Embodiment
The present invention causes that at not carrying out test point pairing in the flying needle path testing of the prior art tabu search algorithm that the test line number reaches employing more is not easy to restrain and causes the deficiency that testing efficiency is low, a kind of optimization method based on four-needle flying-needle test path is proposed, this method adopts the interlock of four pins that test point is matched, make the flying probe line number shorten greatly, and the heuristic optimized Algorithm of employing innovation, can find more excellent test path fast, make the flying probe effect improve.
On concrete enforcement, take following steps to realize: a. reads in the IPC356 formatted file, extracts test point information and adjacent networks information; B. add up the number of consolidated network number same test sign same test point, obtain the reverse side test point and count, positive test point is counted, and the through hole test point is counted; C. according to the size that positive test point is counted, the reverse side test point is counted, the through hole test point according to making positive test point count and the count mode of difference minimum of reverse side test point is divided, is generated positive test point set and reverse side test point and gathers; D. respectively positive test point set and the set of reverse side test point are carried out sorting based on the two dimension of X coordinate and Y coordinate, generate positive test point formation and the formation of reverse side test point; E. positive test point formation and the formation of reverse side test point are matched respectively: e1. when positive test point queue length and reverse side test point queue length all greater than 0 the time, positive test point formation, the formation of reverse side test point are all adopted and are got two and go out one, get two and go out two modes and alternately fall out and match, generate formation of positive test point row and the formation of reverse side test point row; E2. when reverse side test point queue length is 0, take positive test point formation to get two and go out a mode and match, generate the formation of positive test point row; E3. when positive test point queue length is 0, take the formation of reverse side test point to get two and go out a mode and match, generate the formation of reverse side test point row; F. respectively formation of positive test point row and the formation of reverse side test point row are matched, take to get two and go out two modes and go pairing; G. all test points are carried out sorting based on the two dimension of X coordinate and Y coordinate, generate an initial test queue; H. this test queue is divided in the mode of a subqueue of N behavior, generally we adopt and divide in the mode of a subqueue of 5000 behaviors; I. adopt the shortest path method of interpolation to generate new subqueue to each subqueue; J. to the head and the tail connection between any two of new subqueue, finally generate test path.
Innovative point of the present invention is: in the flying probe pairing, propose to adopt four pin interlock modes to generate the match point method, a to f is the process of four pins interlock matching method in the above-mentioned steps, when positive test point queue length and reverse side test point queue length all greater than 0 the time, positive test point formation, the formation of reverse side test point is all adopted and is got two and go out one, getting two goes out two modes and alternately falls out and match, generate formation of positive test point row and the formation of reverse side test point row, this method also is optimum matching method through the mathematical derivation checking having guaranteed in connective, and what obtain is that optimum line number is separated.Above-mentioned steps g to j can be classified as the heuristic optimized Algorithm of the innovation that we adopt, it is to adopt first polymerization classification earlier, divide again and a kind of heuristic algorithm autonomous and that combine with the shortest path method of interpolation, can find fast, improve testing efficiency than shortest path.In addition, we have adopted steps d and twice two dimension ordering of step g to make that the distance between the test line is immediate when pairing, have reached the effect of " four pin normalizings " substantially, have also improved testing efficiency to a certain extent.The shortest path method of interpolation of being mentioned among the present invention is a prior art, often occurs in scientific paper and in the algorithm field study course, no longer it is given unnecessary details here.
Claims (2)
- [claim 1] is characterized in that based on the optimization method of four-needle flying-needle test path: may further comprise the steps,A. read in the IPC356 formatted file, extract test point information and adjacent networks information;B. add up the number of consolidated network number same test sign same test point, obtain the reverse side test point and count, positive test point is counted, and the through hole test point is counted;C. according to the size that positive test point is counted, the reverse side test point is counted, the through hole test point according to making positive test point count and the count mode of difference minimum of reverse side test point is divided, is generated positive test point set and reverse side test point and gathers;D. respectively positive test point set and the set of reverse side test point are carried out sorting based on the two dimension of X coordinate and Y coordinate, generate positive test point formation and the formation of reverse side test point;E. positive test point formation and the formation of reverse side test point are matched respectively:E1. when positive test point queue length and reverse side test point queue length all greater than 0 the time, positive test point formation, the formation of reverse side test point are all adopted and are got two and go out one, get two and go out two modes and alternately fall out and match, generate formation of positive test point row and the formation of reverse side test point row;E2. when reverse side test point queue length is 0, take positive test point formation to get two and go out a mode and match, generate the formation of positive test point row;E3. when positive test point queue length is 0, take the formation of reverse side test point to get two and go out a mode and match, generate the formation of reverse side test point row;F. respectively formation of positive test point row and the formation of reverse side test point row are matched, take to get two and go out two modes and go pairing;G. all test points are carried out sorting based on the two dimension of X coordinate and Y coordinate, generate an initial test queue;H. this test queue is divided in the mode of a subqueue of N behavior;I. adopt the shortest path method of interpolation to generate new subqueue to each subqueue;J. to the head and the tail connection between any two of new subqueue, finally generate test path.
- [claim 2] optimization method based on four-needle flying-needle test path as claimed in claim 1 is characterized in that: among the described step h, be that test queue is divided in the mode of a subqueue of 5000 behaviors.
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| CN2008103061980A CN101424723B (en) | 2008-12-12 | 2008-12-12 | Optimizing method based on four-needle flying-needle test path |
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| CN2008103061980A CN101424723B (en) | 2008-12-12 | 2008-12-12 | Optimizing method based on four-needle flying-needle test path |
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| CN101424723B CN101424723B (en) | 2011-01-19 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667219B (en) * | 2009-09-29 | 2011-07-06 | 重庆大学 | Optimization method of printed-circuit board test path |
| CN102193043A (en) * | 2010-03-08 | 2011-09-21 | 瑞统企业股份有限公司 | Testing integration method for bare board of circuit board |
| CN103344905A (en) * | 2013-06-18 | 2013-10-09 | 深圳市大族激光科技股份有限公司 | Moving needle bed testing machine and testing method |
| CN104422845A (en) * | 2013-08-28 | 2015-03-18 | 深圳麦逊电子有限公司 | Intelligent four-wire point selection method of PCB electrical performance test point |
| CN105911450A (en) * | 2016-03-22 | 2016-08-31 | 重庆大学 | Flying probe tester open-circuit test path optimization method |
| CN107942238A (en) * | 2017-12-30 | 2018-04-20 | 大族激光科技产业集团股份有限公司 | The test point distribution method and device of printed circuit board (PCB) |
-
2008
- 2008-12-12 CN CN2008103061980A patent/CN101424723B/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667219B (en) * | 2009-09-29 | 2011-07-06 | 重庆大学 | Optimization method of printed-circuit board test path |
| CN102193043A (en) * | 2010-03-08 | 2011-09-21 | 瑞统企业股份有限公司 | Testing integration method for bare board of circuit board |
| CN103344905A (en) * | 2013-06-18 | 2013-10-09 | 深圳市大族激光科技股份有限公司 | Moving needle bed testing machine and testing method |
| CN104422845A (en) * | 2013-08-28 | 2015-03-18 | 深圳麦逊电子有限公司 | Intelligent four-wire point selection method of PCB electrical performance test point |
| CN104422845B (en) * | 2013-08-28 | 2017-06-23 | 深圳麦逊电子有限公司 | A kind of intelligence four line selection point methods of PCB electric performance tests point |
| CN105911450A (en) * | 2016-03-22 | 2016-08-31 | 重庆大学 | Flying probe tester open-circuit test path optimization method |
| CN107942238A (en) * | 2017-12-30 | 2018-04-20 | 大族激光科技产业集团股份有限公司 | The test point distribution method and device of printed circuit board (PCB) |
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| Publication number | Publication date |
|---|---|
| CN101424723B (en) | 2011-01-19 |
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