CN104536867A - System and method for debugging multiple field-programmable gate arrays - Google Patents
System and method for debugging multiple field-programmable gate arrays Download PDFInfo
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Abstract
The invention provides a system and a method for debugging multiple field-programmable gate arrays (FPGAs). The method comprises the following steps: selecting and grouping to-be-tested signals according to a clock domain by virtue of a signal selection and transmission module for instantiating each to-be-tested FPGA, and configuring a high-speed serial transceiver bus port of signal transmission; performing logic synthesis and location wiring on the design logic of the to-be-tested FPGAs and the signal selection and transmission module together; finding displacement information aligned with all channels according to the longest time delay in high-speed serial bus channels of all the to-be-tested FPGAs by using a special tested FPGA in a channel alignment operating mode selected by a debugging host; and selecting a to-be-tested signal group of the to-be-tested FPGA by the debugging host, and configuring the channel time delay value by using frequency information of the to-be-tested signal group. According to the system and the method disclosed by the invention, the cross-FPGA chip signal is observed and captured by using a special tested FPGA, and the fault tracing and positioning efficiency of a debugging system is improved.
Description
Technical field
The present invention relates to the debugging technique of field programmable gate array (FPGA, Field Programmable Gate Array), particularly relate to the system and method realizing multiple FPGA debugging.
Background technology
In recent years, large-scale F PGA range of application is more and more extensive, and application scenarios is increasingly sophisticated.For IC prototype verification, the IC design of ten million gate leve needs to realize with multi-disc (i.e. multi-chip) FPGA usually.Like this, just need to carry out combined debugging to multiple FPGA.And the latter is a difficult problem in FPGA debugging always.
At present, conventional solution sets up embedded logic analyser in each FPGA.Due to these logic analysers by logical division in different FPGA sheets, there is no physical couplings each other, so just cannot go to capture the signal to be observed in another sheet FPGA as trigger pip with the signal of a slice FPGA.Meanwhile, when IC design update, along with the increase of amount of logic, FPGA resource is tending towards nervous, quantity and the degree of depth of embedded online logic analyser tracking signal all can be greatly reduced, and cause normal signal debug function to be difficult to realize, even cannot complete placement-and-routing.Another kind of conventional solution uses traditional external logic analyser to follow the trail of the signal to be observed in different FPGA sheets.But external logic analyser also exists Instrument purchase costly, and it is many and affect the shortcomings such as FPGA function application to take FPGA pin.
The current design to large scale digital logic function often could realize with multiple FPGA.A complicated wrong scene is positioned, usually needs observation to follow the trail of signal in different FPGA, such as, to catch the observation signal in FPGA 2 with the signal in FPGA 1 as trigger pip.Traditional embedded online logic analyser is often helpless to this.Simultaneously embedded logic analyzer can take more storage resources, when FPGA resource utilization rate higher than 80%, then insert embedded logic analyser and also can bring very large adverse effect to FPGA placement-and-routing.In addition, after upgrading the signal acquisition of online logic analyser each time, all need again to compile whole design, consuming time very long.With external logic analyser, often take more pin, especially wider to observation signal bit wide scene, this problem is especially obvious.
Therefore, need to provide a kind of system realizing the debugging of multi-disc field programmable gate array, can when multiple FPGA combined debugging to sheet between signal to observe and intersection is caught, only take less FPGA pin to be measured simultaneously, improve measurability and the extensibility of system.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of system and method realizing the debugging of multi-disc field programmable gate array, can when multiple FPGA combined debugging to sheet between signal to observe and intersection is caught
In order to solve the problems of the technologies described above, the invention provides the system of a kind of multi-disc field programmable gate array debugging, comprising a special test field programmable gate array, multi-disc field programmable gate array to be measured and debug host, wherein:
Field programmable gate array to be measured, be connected with special test field programmable gate array respectively by high-speed serial bus, and be connected with debug host respectively by universal serial bus, press clock zone selection and the measured signal that divides into groups for the signal behavior of exampleization this film and sending module under passage alignment mode of operation; Sent by high-speed serial bus according to the measured signal group of the selection of debug host by this film under test job pattern;
Special test field programmable gate array, be connected with debug host by universal serial bus, for finding the shift information of all passages that aligns under passage alignment mode of operation by the most long delay in the high-speed serial bus passage of all field programmable gate arrays to be measured; Receive under test job pattern and all passages that aligns, the inner online logic analyser of exampleization catches with observation from the measured signal in field programmable gate array difference to be measured;
Debug host, for selecting the mode of operation of field programmable gate array to be measured and special test field programmable gate array, and selects the measured signal group in field programmable gate array to be measured, with the frequency information collocation channel delay value of measured signal group.
Further,
Second special register of the frequency information of measured signal group write special test field programmable gate array, by writing the way selection measured signal group of the first special register of field programmable gate array to be measured, is carried out collocation channel delay value by debug host simultaneously;
The bit wide of signal is often organized after the signal behavior of field programmable gate array exampleization to be measured and sending module determine grouping according to the signal bit wide that high-speed serial bus can send; The signal group wide for bit wide splits into multiple signal group further according to test scene or function scene; Measured signal group is sent by high-speed serial bus by the first special register according to reading debug host access.
Further, the design logic of field programmable gate array to be measured is carried out logic synthesis and placement-and-routing with signal behavior together with sending module; The universal serial bus wherein connecting field programmable gate array to be measured and debug host and the universal serial bus being connected special test field programmable gate array and debug host all use UART Universal Asynchronous Receiver Transmitter.
Further,
Debug host makes field programmable gate array to be measured and special test field programmable gate array admission passage alignment mode of operation or test job pattern by sending order;
Under passage alignment mode of operation,
Field programmable gate array to be measured injects pseudo-random binary sequence code with the most high workload clock frequency of this film to high-speed serial bus transmitting terminal by signal behavior and sending module;
After special test field programmable gate array receives pseudo-random binary sequence code by the receiving end of high-speed serial bus, send into fifo queue by passage alignment module and carry out shifting processing, till the pattern alignment of all passages; By configuration module, shift information record is kept in the register of confession debug host access.
Further, shift information to be configured to the buffer area of each signal group by special test field programmable gate array carry out passage alignment under test job pattern before.
In order to solve the problems of the technologies described above, the invention provides the method for a kind of multi-disc field programmable gate array debugging, comprising:
The signal behavior of each field programmable gate array to be measured of exampleization and sending module are pressed clock zone and are selected and grouping measured signal, and are signal transmission configuration high-speed serial transceiver bus port;
Together with sending module, logic synthesis and placement-and-routing are carried out with signal behavior to the design logic of field programmable gate array to be measured;
Passage alignment step: under the passage alignment mode of operation that debug host is selected, find the shift information of all passages that aligns by the most long delay in the high-speed serial bus passage of all field programmable gate arrays to be measured with special test field programmable gate array;
Debug host selects the measured signal group of field programmable gate array to be measured, and with the frequency information collocation channel delay value of measured signal group.
Further, the method also comprises:
Under the debugging efforts pattern that debug host is selected, measured signal group is sent by high-speed serial bus interface according to the selection of debug host by signal behavior and sending module; Special test field programmable gate array Received signal strength all signalling channels of aliging, exampleization online logic analyser seizure simultaneously and the measured signal in observing different field programmable gate array to be measured.
Further, the signal behavior of field programmable gate array exampleization to be measured and sending module often organize the bit wide of signal after determining to divide into groups according to the signal bit wide that high-speed serial bus can send; For the signal group that bit wide is wide, split into multiple signal group further according to test scene or function scene.
Further, passage alignment step specifically comprises:
The signal behavior of field programmable gate array to be measured and sending module inject pseudo-random binary sequence code with the most high workload clock frequency of this film to high-speed serial bus transmitting terminal;
After special test field programmable gate array receives this pseudo-random binary sequence code, send into fifo queue and carry out shifting processing, till the pattern alignment of all passage measured signals; Then this shift information record is kept in the register for debug host access.
Further,
Debug host selects measured signal group by the first special register in access field programmable gate array to be measured, simultaneously by the second special register in the frequency information of measured signal group write special test field programmable gate array is carried out collocation channel delay value;
According to the first special register reading debug host access, measured signal group is sent by high-speed serial bus interface after signal behavior and sending module enter test job pattern; Shift information was also configured to the buffer area of each signal group by special test field programmable gate array carry out passage alignment under test job pattern before.
The present invention's a slice special test FPGA replaces multiple logic analyser of being in the past embedded in each FPGA or external logic analyser, the output being realized different test FPGA internal signals by debug host and its connection is selected, greatly can save the compiling number of times of design, and save debug time.Connect FPGA to be measured and special test FPGA by high-speed serial bus, the pin of FPGA can be saved thus, observe more signal with minimum Resources Consumption.And when special test FPGA resource has surplus, also available its bears a part of design logic.The present invention by across fpga chip signal observation and catch, improve measurability and the extensibility of system, improve the efficiency of debug system fault trace and location.
Accompanying drawing explanation
Fig. 1 is the structured flowchart realizing the system embodiment of multiple FPGA debugging of the present invention;
Fig. 2 is the structured flowchart of special test FPGA embodiment of the present invention in the system embodiment shown in Fig. 1;
Fig. 3 is the signal behavior of FPGA to be measured in the system embodiment shown in Fig. 1 and the structured flowchart of sending module;
Fig. 4 is the process flow diagram realizing the embodiment of the method for multiple FPGA debugging of the present invention.
Embodiment
With preferred embodiment, technical scheme of the present invention is described in detail with reference to the accompanying drawings.Should be appreciated that, the embodiment below enumerated only for instruction and explanation of the present invention, and does not form the restriction to technical solution of the present invention.
As shown in Figure 1, illustrate the structure of the system embodiment of multiple FPGA of the present invention debugging, comprise a special test FPGA, multi-disc FPGA to be measured and debug host, wherein:
FPGA to be measured, is connected with special test FPGA respectively by high-speed serial bus, and is connected with debug host respectively by universal serial bus, presses clock zone select and grouping measured signal for the signal behavior of example this film and sending module; Sent by high-speed serial bus according to the measured signal group of the selection of debug host by this film under test job pattern;
Special test FPGA, is connected with debug host by universal serial bus, for finding the shift information of all passages that aligns under passage alignment mode of operation by the most long delay in the high-speed serial bus passage of all FPGA to be measured; Receive under test job pattern and all passages that aligns, the inner online logic analyser of exampleization catches with observation from the measured signal in FPGA difference to be measured;
Debug host, for selecting the mode of operation of FPGA to be measured and special test FPGA, and selects the measured signal group in FPGA to be measured, and with the frequency information collocation channel delay value of measured signal group.
Fig. 2 illustrates the structure of an embodiment of special test FPGA in said system embodiment of the present invention, and Fig. 3 then illustrates the signal behavior of FPGA to be measured and the structure of sending module in system embodiment; The universal serial bus wherein connecting FPGA to be measured and debug host and the universal serial bus being connected special test FPGA and debug host all use UART Universal Asynchronous Receiver Transmitter (UART, Universal AsynchronousReceiver Transmitter).
In said system embodiment,
The special register 2 of the frequency information of measured signal group write special test FPGA, by writing the measured signal group of the way selection FPGA to be measured of the special register 1 of FPGA to be measured, is carried out collocation channel delay value by debug host simultaneously;
The bit wide of signal is often organized after the signal behavior of FPGA exampleization to be measured and sending module determine grouping according to the signal bit wide that high-speed serial bus can send; For the signal group that bit wide is wide, split into multiple signal group further according to test scene or function scene; The measured signal group of this film is sent by high-speed serial bus by the special register 1 according to reading debug host access.
In said system embodiment,
The design logic of FPGA to be measured is carried out logic synthesis and placement-and-routing with signal behavior together with sending module.
In said system embodiment,
Debug host makes FPGA to be measured and special test FPGA admission passage alignment mode of operation or test job pattern by sending order;
Under passage alignment mode of operation,
FPGA to be measured injects pseudo-random binary sequence (PRBS, Pseudo-Random Binary Sequence) code with the most high workload clock frequency of this film to high-speed serial bus transmitting terminal by signal behavior and sending module;
After special test FPGA receives PRBS code by the receiving end of high-speed serial bus, send into fifo queue (FIFO, First-In First-Out) by passage alignment module and carry out shifting processing, till the pattern alignment of all passages; By configuration module, this shift information record is kept in the register of confession debug host access.
In said system embodiment,
This shift information to be configured to the buffer area of each signal group by special test FPGA carry out passage alignment under test job pattern before, for compensating time delay between each signal group different sheet.
The present invention is directed to said system embodiment, correspondingly additionally provide the embodiment of the method for multiple FPGA debugging, its flow process as shown in Figure 4, comprises the steps:
110: the signal behavior of each FPGA to be measured of exampleization and sending module are pressed clock zone and selected and grouping measured signal, and be signal transmission configuration high-speed serial transceiver bus port;
The bit wide of signal is often organized after the signal behavior of FPGA exampleization to be measured and sending module determine grouping according to the signal bit wide that high-speed serial bus can send; For the signal group that bit wide is wide, split into multiple signal group further according to test scene or function scene.
120: together with sending module, logic synthesis and placement-and-routing are carried out with signal behavior to the design logic of FPGA to be measured;
130: the shift information finding all passages that aligns under passage alignment mode of operation with special test FPGA by the most long delay in the high-speed serial bus passage of all FPGA to be measured;
140: debug host selects the measured signal group of FPGA to be measured, and with the frequency information collocation channel delay value of measured signal group.
Said method embodiment also comprises:
150: under debugging efforts pattern, signal behavior and sending module are sent by high-speed serial bus interface according to the measured signal group of the selection of debug host by this film; Special test FPGA Received signal strength all signalling channels of aliging, exampleization online logic analyser seizure simultaneously and the measured signal observed in different FPGA to be measured.
In said method embodiment,
Debug host makes FPGA to be measured and special test FPGA admission passage alignment mode of operation or test job pattern by sending order.
In said method embodiment, step 130 specifically comprises:
The signal behavior of FPGA to be measured and sending module inject PRBS code with the most high workload clock frequency of this film to high-speed serial bus transmitting terminal;
After special test FPGA receives PRBS code with this film maximum clock frequency, send into FIFO and carry out shifting processing, till the pattern alignment of all passage measured signals; Then this shift information record is kept in the register for debug host access.
In said method embodiment,
This shift information to be configured to the buffer area of each signal group by special test FPGA carry out passage alignment under test job pattern before, for compensating time delay between each signal group different sheet.
In said method embodiment,
Step 140 debug host is accessed special register 1 in FPGA to be measured and is selected measured signal group, the special register 2 in the frequency information of measured signal group write special test FPGA is carried out collocation channel delay value simultaneously;
The measured signal group of this film is sent by high-speed serial bus according to the special register 1 reading debug host access by step 150 FPGA to be measured.
Claims (10)
1. a system for multi-disc field programmable gate array debugging, is characterized in that, comprise a special test field programmable gate array, multi-disc field programmable gate array to be measured and debug host, wherein:
Field programmable gate array to be measured, be connected with special test field programmable gate array respectively by high-speed serial bus, and be connected with debug host respectively by universal serial bus, press clock zone selection and the measured signal that divides into groups for the signal behavior of exampleization this film and sending module under passage alignment mode of operation; Sent by high-speed serial bus according to the measured signal group of the selection of debug host by this film under test job pattern;
Special test field programmable gate array, be connected with debug host by universal serial bus, for finding the shift information of all passages that aligns under passage alignment mode of operation by the most long delay in the high-speed serial bus passage of all field programmable gate arrays to be measured; Receive under test job pattern and all passages that aligns, the inner online logic analyser of exampleization catches with observation from the measured signal in field programmable gate array difference to be measured;
Debug host, for selecting the mode of operation of field programmable gate array to be measured and special test field programmable gate array, and selects the measured signal group in field programmable gate array to be measured, with the frequency information collocation channel delay value of measured signal group.
2., according to system according to claim 1, it is characterized in that,
Described debug host is by measured signal group described in the way selection of writing the first special register of described field programmable gate array to be measured, and the second the special register simultaneously frequency information of described measured signal group being write described special test field programmable gate array carrys out collocation channel delay value;
The bit wide of signal is often organized after the described signal behavior of described field programmable gate array exampleization to be measured and sending module determine grouping according to the signal bit wide that high-speed serial bus can send; The signal group wide for bit wide splits into multiple signal group further according to test scene or function scene; Described measured signal group is sent by high-speed serial bus by the first special register according to reading debug host access.
3., according to system according to claim 2, it is characterized in that,
The design logic of described field programmable gate array to be measured is carried out logic synthesis and placement-and-routing with described signal behavior together with sending module; The universal serial bus wherein connecting described field programmable gate array to be measured and described debug host and the universal serial bus being connected described special test field programmable gate array and described debug host all use UART Universal Asynchronous Receiver Transmitter.
4., according to the system described in any one of claims 1 to 3, it is characterized in that,
Described debug host makes field programmable gate array to be measured and special test field programmable gate array enter described passage alignment mode of operation or described test job pattern by sending order;
Under passage alignment mode of operation,
Described field programmable gate array to be measured injects pseudo-random binary sequence code with the most high workload clock frequency of this film to high-speed serial bus transmitting terminal by described signal behavior and sending module;
After special test field programmable gate array receives pseudo-random binary sequence code by the receiving end of high-speed serial bus, send into fifo queue by passage alignment module and carry out shifting processing, till the pattern alignment of all passages; By configuration module, described shift information record is kept in the register of the described debug host access of confession.
5., according to system according to claim 4, it is characterized in that,
Described shift information to be configured to the buffer area of each signal group by described special test field programmable gate array carry out passage alignment under described test job pattern before.
6. a method for multi-disc field programmable gate array debugging, is characterized in that, comprising:
The signal behavior of each field programmable gate array to be measured of exampleization and sending module are pressed clock zone and are selected and grouping measured signal, and are signal transmission configuration high-speed serial transceiver bus port;
Together with sending module, logic synthesis and placement-and-routing are carried out with signal behavior to the design logic of field programmable gate array to be measured;
Passage alignment step: under the passage alignment mode of operation that debug host is selected, find the shift information of all passages that aligns by the most long delay in the high-speed serial bus passage of all field programmable gate arrays to be measured with special test field programmable gate array;
Debug host selects the measured signal group of field programmable gate array to be measured, and with the frequency information collocation channel delay value of measured signal group.
7. in accordance with the method for claim 6, it is characterized in that, also comprise:
Under the debugging efforts pattern that debug host is selected, described measured signal group is sent by high-speed serial bus interface according to the selection of described debug host by described signal behavior and sending module; Described special test field programmable gate array Received signal strength all signalling channels of aliging, exampleization online logic analyser seizure simultaneously and the measured signal in observing different field programmable gate array to be measured.
8. in accordance with the method for claim 7, it is characterized in that,
The bit wide of signal is often organized after the described signal behavior of described field programmable gate array exampleization to be measured and sending module determine grouping according to the signal bit wide that high-speed serial bus can send; For the signal group that bit wide is wide, split into multiple signal group further according to test scene or function scene.
9. according to the method described in claim 7 or 8, it is characterized in that, described passage alignment step specifically comprises:
The described signal behavior of described field programmable gate array to be measured and sending module inject pseudo-random binary sequence code with the most high workload clock frequency of this film to high-speed serial bus transmitting terminal;
After described special test field programmable gate array receives this pseudo-random binary sequence code, send into fifo queue and carry out shifting processing, till the pattern alignment of all passage measured signals; Then this shift information record is kept in the register for debug host access.
10. in accordance with the method for claim 9, it is characterized in that,
Described debug host selects measured signal group by the first special register in access field programmable gate array to be measured, simultaneously by the second special register in the frequency information of described measured signal group write special test field programmable gate array is carried out collocation channel delay value;
According to the first special register reading the access of described debug host, described measured signal group is sent by high-speed serial bus interface after described signal behavior and sending module enter test job pattern; Described shift information was also configured to the buffer area of each signal group by described special test field programmable gate array carry out passage alignment under described test job pattern before.
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