CN101410964A - 用于半导体qfn/son器件的铝引线框架 - Google Patents

用于半导体qfn/son器件的铝引线框架 Download PDF

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CN101410964A
CN101410964A CNA2007800112895A CN200780011289A CN101410964A CN 101410964 A CN101410964 A CN 101410964A CN A2007800112895 A CNA2007800112895 A CN A2007800112895A CN 200780011289 A CN200780011289 A CN 200780011289A CN 101410964 A CN101410964 A CN 101410964A
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lead
chip
layer
aluminum
aluminium
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D·C·阿博特
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

一种具有铝引线框架(105)的后成型镀层半导体器件，所述铝引线框架带有包括芯片安放垫和多个引线段的结构，其中多个引线段不带有悬臂引线部分。半导体芯片(210)被附着在芯片安放垫上，并且导电连接(212)从芯片跨越到引线段的铝。聚合封装材料(220)如成型化合物覆盖芯片、连接以及铝引线段的部分，不留下悬臂段部分。优选通过非电镀方法将锌层(301)和镍层(302)镀在引线段上没有被封装材料覆盖的那些部分，那些部分包括通过器件单粒化步骤形成的铝段表面(在203b处)，并且在所述镍层上有优选为钯的贵金属层(303)。

Description

用于半导体QFN/SON器件的铝引线框架
技术领域
【0001】本发明一般地涉及半导体器件和工艺领域，更具体地涉及用于小集成电路器件和半导体元件的引线框架的材料和加工。
背景技术
【0002】自从引入用于半导体器件的方形扁平无引脚(QFN)和小外形无引脚(SON)封装的概念，这些封装已处于小型化的陡学习曲线(steep learning curve)上。今天，由于小的封装尺寸(面积和厚度)，这些类别的一些类别在半导体应用中是受欢迎的。然而另一方面，随着封装尺度的降低，在保持封装可靠性以及优化电阻以抵抗分层、腐蚀、扭曲以及热机械应力方面增加了技术上的挑战。这些可靠性努力中的决定性因素是封装的引线框架。
【0003】半导体器件的引线框架在封装体内提供用于稳固地放置半导体芯片(通常是集成电路(IC)芯片)的稳定支撑垫。普遍实行的是从金属薄片(大约120μm到250μm)制造单块引线框架。为了便于制造，通常选择的起始金属是铜、铜合金或铁镍合金(如所谓“合金42”)；在需要外部引线弯曲的器件中铝是难以起作用的。所需的引线框架形状从原始片中压印或刻蚀出来。
【0004】除芯片垫外，引线框架提供多个导电段，从而把多个电导体带到接近芯片的周边。段的内端点和IC表面上接触垫之间的剩余空间被连接器桥接，这些连接器通常是例如金的细金属线，该细金属线被单独键合到IC接触垫和引线框架段。由此，内段端点的表面在冶金学上应适合于针脚附着(stitch-attaching)到连接器上。
【0005】远离IC芯片的引线段的端点(外端)需要电连接和机械连接到如印刷电路板的外电路。这种附着通常在高于200℃的回流温度下用锡合金焊料焊接完成。由此，外段端点的表面需要具有冶金学上的配置以适应回流附着到外部部分。
【0006】最终，引线框架提供用于封装敏感芯片和脆弱连接线的硬件。使用塑料材料而不是金属壳或陶瓷进行封装是优选的方法。在175℃下用于环氧基热固化合物的转换成型工艺已经实践了很多年；175℃的成型与模型固化(聚合)温度与大于200℃的焊料回流温度是兼容的。
【0007】在潮湿环境下的器件应用需要在封装引线框架部分和成型化合物之间(molding compound)具有良好的粘附性。良好粘附的两个主要贡献者是成型化合物和引线框架的金属表面(metal finish)之间的化学亲和性，以及引线框架的表面粗糙度。
【0008】近年来，很多技术趋势使得找到保持良好粘附性的满意方案变得越来越复杂。因此，使用无引脚焊料的需求将回流温度范围推到大约260℃附近。
发明内容
【0009】申请人发现依照本发明使用铝作为引线框架提供了优于现有引线框架的许多优势，这是因为未镀层的铝提供了对金线的强键合以及对成型化合物极好的附着力。此外，在封装后和器件单粒化(singulation)后仍然暴露的所有引线框架部分可以被镀上可软焊金属层，这些可软焊金属层同时保护引线框架免受腐蚀。这种引线框架及其加工方法足够灵活，从而应用于不同的半导体产品系列和宽范围的设计与装配变化，特别是对于QFN和SON器件。这一方法也可以实现朝向更高的加工成品率和更高器件稳定性这两个目标的改进。
【0010】本发明的一个实施例是带有铝引线框架的后成型镀层(plated)半导体器件。该引线框架结构包括芯片安放垫和不带有悬臂引线的多个引线段。半导体芯片被附着在芯片安放垫上，并且导电连接从芯片跨越到引线段的铝表面。聚合封装材料如成型化合物覆盖芯片、连接以及铝引线段的部分。镍层位于没有被封装材料覆盖的那些引线段部分，且在镍层上有优选为钯的贵金属层。
【0011】本发明涉及高密度集成电路，包括那些具有大量输入输出的集成电路，并涉及不带有悬臂引线的器件封装，特别是无引线器件封装。这些器件可以在多个半导体系列中找到，如标准的线性逻辑产品、处理器、数字与模拟器件、高频与高功率器件，以及大面积和小面积芯片类别。本发明也表现出与具有传统的铜(或铁镍合金)引线框架的半导体封装相比显著的半导体封装成本降低。
【0012】本发明的另一个实施例是加工半导体器件的方法。提供铝片并从这个铝片刻蚀出引线框架结构。这一结构包括芯片安放垫和不带有悬臂引线的多个引线段。带有焊盘的半导体芯片被安放在芯片安放垫上，并且芯片焊盘与各自引线段的铝表面互连。芯片、互连以及引线段的部分被封装在聚合物材料中。接下来，没有被聚合物材料覆盖的那些引线段部分被进行锌酸盐处理并(通过非电镀方法)镀上镍层，随后镀上优选为钯的贵金属层。
【0013】本发明的一个技术优势是提供铝引线框架，从而可以继续使用基于用于附着引线部分(通过不需要冲洗步骤的水可溶助融剂或温和助融剂)的焊接的表面安放技术。半导体产品的终端用户可以继续采用已安装的组装设备基础。
【0014】其另一个技术优势是在由精细间距键合限定的条件下提供简单的可键合性。
【0015】进一步的优势是，本发明提供铝引线框架，这样它们展现出对于用于塑料封装的成型化合物的良好粘附性，因此避免了湿气进入和腐蚀，并同样展现出对通过后成型镀层工艺的引线的腐蚀保护。
【0016】通过下面对本发明优选实施例的描述并结合考虑附图及所附权利要求阐述的新特点，本发明的某些实施例代表的技术优势将变得明显。
附图说明
【0017】图1是带有成形引线框架结构的部分铝引线框架条的基本金属结构的示意性剖面图。
【0018】图2图示说明了本发明器件实施例的示意性剖面图，其显示了依照本发明实施例制备的部分引线框架条以及组装并封装在一个引线框架表面上的多个半导体芯片。
【0019】图3图示说明了QFN/SON类型的单粒化器件的示意性剖面图，该器件包括依照本发明制备的后成型镀层引线框架。
具体实施方式
【0020】在用于半导体器件的传统表面安放封装中，这些封装具有弯曲成小外形的S形或J形悬臂引线，引线框架材料预期提供延展性以延长至少5到10％，从而满足外段成形的需要，其通常是加工流程的最后工艺步骤。成形工艺需要的金属延展性已经很容易地由作为起始材料的铜或铜合金的延展性提供。另一方面，用铝作为引线框架的起始材料来提供相似的金属延展性是很具有挑战性的。材料特性如受热历史、合金混合或已镀的表面金属层需要被小心地选择以使铝适合于作为带有悬臂引线的引线框架的基础材料。
【0021】申请人发现这些需求和限制在缺少悬臂引线的引线框架中变得不重要，所述引线框架如具有方形扁平无引脚(QFN)和小外形无引脚(SON)封装的器件中的引线框架。申请人还发现支配QFN和SON器件的其它具体需求可通过作为引线框架材料的未处理的铝来特别地满足。这些具体的需求属于引线框架表面和封装聚合材料之间的强粘附性(可用于粘附的面积被最小化)，以及用于附着键合引线的良好键合特性。最后，未封装的引线框架部分应适用于低成本的镀层技术以便淀积可软焊的金属层。
【0022】依照本发明，这些不同需要可以通过将铝作为引线框架基础金属来满足。本发明描述引线框架的基础金属、在这些引线框架上组装和封装半导体芯片以及在封装后处理基础材料的工艺，从而使器件变得适用于板组装和其它应用。
【0023】铝或铝合金的密度是2.7g/cm3，杨氏模量是72.5×103N/mm2，而热膨胀系数是24.7ppm/℃。相对的，铜和铜合金的密度是8.93g/cm3，杨氏模量是120×103N/mm2，而热膨胀系数是17.6ppm/℃。当铜被用作半导体引线框架的基础材料时，这些铜的性质会产生以下问题：引线框架基础金属的大质量；硅芯片的高热机械应力水平；以及板附着中焊接点的高热机械应力水平。
【0024】大致上，铝的密度是铜的1/3，这将降低引线框架基础材料的质量(重量)。铝的更低的杨氏模量将帮助补偿与热机械应力相关的更高的热膨胀系数。因为铝合金的热膨胀系数与杨氏模量的乘积小于铜合金的热膨胀系数与杨氏模量的乘积，所以与铜合金相比铝合金的应力水平将降低。铝的热导率与铜相似。对于给定的典型引线框架的尺寸，与在细键合引线中不可避免的导电损失相比，铝的更低的电导率显得并不重要。
【0025】此外，原料成本的不同是显著的。对于铜和铜合金，现在的原料价格大约是2.13$/kg，对于铝或铝合金仅是1.08$/kg。结合上文说明的密度进行考虑，铝有大约6.5倍的成本优势。
【0026】用于QFN和SON器件的铝制引线框架具有用于支撑半导体芯片的芯片垫，该芯片垫被具有接近芯片垫的内端和远离芯片垫的外端的非悬臂段围绕。内段端点适合键合附着到连接线；外段端点可被制备(见下文)以使其适合于焊接附着到外部部分。未处理的铝表面特别是氧化表面应适合于粘附到成型化合物。
【0027】通过一工艺流程使未封装的引线框架部分变得对腐蚀不敏感，该工艺流程不留下暴露的铝并生成淀积在铝表面的一系列保护层，特别是镍层和随后作为最外层的贵金属层(或多层)。
【0028】依照本发明的教导，首先对组装的半导体芯片和引线框架部分进行封装，然后在未封装的铝部分淀积锌层、镍层和最外面的贵金属层，由此实现铝引线框架的可焊接性。当贵金属在焊接操作中融解时，在镍表面形成焊接点。
【0029】本发明通过将金线直接键合到引线框架材料的铝上来满足引线框架的可键合需要。
【0030】申请人的实验已经显示可以实现聚合封装料或成型化合物以及铝和/或氧化铝之间的极好的粘合性。这种粘合性的强度足以经受在潮湿环境和高温下的加速可靠性器件测试，并避免引线框架和聚合封装料之间的分层。
【0031】对于QFN/SON器件，由于铝和优选成型化合物相对接近的匹配热膨胀系数，本发明提供了低的器件扭曲。
【0032】图1图示说明了依照本发明意在被用于半导体器件的加工的引线框架条(整体标示为100)的示意性剖面图。该引线框架条具有由金属片制成的结构，其中该结构具有多个表面：第一表面101，第二表面102，以及多个侧边表面110a，110b，110c，110d，...110n。而表面101和102源于起始材料片的表面，侧边表面110a到110n通过引线框架结构的成形工艺产生。在图1的示例中，所描述的引线框架部分包含多个部分103以及多个部分104，部分103将成为芯片安放垫，而部分104将成为待植入器件的引线段。
【0033】引线框架由基础金属105制成。如本文定义，引线框架的起始材料被称为“基础金属”，其指代金属的类型。因此，术语“基础金属”并不希望从电化学意义(与‘贵金属’相对)或结构意义上进行解读。
【0034】引线框架的基础金属105是优选厚度在100μm到300μm范围内的铝片。这些片是可购买的，如从凯泽铝公司(Kaiser AluminumCorporation，Jackson，TN，USA)的分公司“Tennalum”购买。本发明优选的材料是含有锰的铝合金(3xxx系列，如3004，其中合金标记中的数字指代合金的变化)。其他合金用例如铜、硅、锰和锌制造。这些铝和铝合金片经过多个受热历史的变更，如回火、退火、应变硬化，由此导致多种硬度。
【0035】当引线框架将被用于QFN/SON器件时，基础金属的机械强度不是重要因素，这是因为没有未支持的引线，并且成型化合物提供了机械上可靠的器件封装。
【0036】引线框架部分如芯片安放垫、引线段、连接轨道(图1未显示，但用虚线表示)优选在起始金属片中刻蚀出来。优选的低成本和快速刻蚀方法使用腐蚀性刻蚀剂如非氧化的盐酸HCl(铝溶于HCl并产生氢气)。如前所述，这些刻蚀工艺产生引线框架部分的多个侧边110a、110b、...、110n。
【0037】图2图示说明依照本发明加工半导体器件的下一个步骤，以QFN或SON器件为例，其仍处于在器件单粒化之前的具有多个组装和封装器件的引线框架这一阶段。在图2的阶段中，器件具有引线框架，所述引线框架带有由铝基础金属片105制成的结构；所述片具有第一表面201a和第二表面210b。图2中的引线框架结构包括芯片安放垫202和多个引线段203。每个引线段203具有靠近芯片安放垫202的第一端203a和远离芯片安放垫202的第二端203b。第一引线框架表面201a和该结构的全部侧边具有铝或氧化铝表面，因此提供带有对聚合材料的可靠粘附性和对金线键合的冶金学亲和性的引线框架。
【0038】半导体芯片210例如硅集成电路芯片通过粘附层211被附着到每个芯片安放垫202上。导电连接212如优选由金或金合金构成的键合线(或带)从芯片210延伸到引线段203并互连芯片与引线段的第一端203a(作为替代，连接212可以是铜线或铝线)。针脚键合212a被压力键合到铝，从而提供可靠的针脚附着。
【0039】聚合封装材料220例如环氧基成型化合物覆盖芯片210、键合线212以及引线段203的部分。聚合材料220也填充芯片210和引线段的第一端203a之间的空隙并因此覆盖引线框架侧边。在QFN/SON器件中，聚合化合物220形成与第二引线框架表面201b共面(在同一表面)的表面221。聚合材料220留下第二引线框架表面201b未覆盖。因此第二引线框架表面的这些暴露部分可以被焊接回流金属接触。
【0040】在图2中，虚线230指代一些位置，在这些位置锯将把完成的引线框架条切割成(或冲压机将该引线框架条单粒化成)QFN/SON封装类型的独立器件。锯(或冲压机)切断封装材料420和铝引线框架条。因此，锯开(冲压)步骤在远处的段端点203b处新产生铝引线框架金属的侧表面。
【0041】有利的是执行所述条的封装单元的切割步骤，以使所选择的聚合支撑板继续连接单元，并因此保护条的一致性(图2未显示)。通过连接板，所述条可以作为单一实体通过后续加工步骤被处理，这允许全部工艺步骤的成本有效实行。在最后工艺步骤(贵金属层的形成)完成后，聚合物支撑板可被断开以分离完成的器件。作为替代，板的断开可以被延期直到末端用户车间的最终器件应用。
【0042】当在器件加工流程开始时引线框架就已经是独立单元而不是单元条，则不需要锯开(冲压)步骤来产生单粒化的器件。
【0043】在器件加工的下一个工艺步骤中，芯片垫的暴露的表面201b和引线段以及锯开/冲压动作新形成的侧壁将被准备来淀积回流焊接合金层。器件首先在20℃到90℃的碱性预清洗溶液内浸泡几秒到3分钟的时间。以此将任何油或其它污染物从铝表面除去。
【0044】在清洗后，器件随后在室温的酸性活化浴中浸泡几秒到5分钟的时间。浴液由硝酸溶液或硝/硫磺酸溶液组成，优选浓度为约30-60g/l。这种溶液除去氧化铝并使金属铝表面处于活化状态，准备接受金属锌的淀积。
【0045】对于锌淀积，活化的铝或铝合金片被浸入锌酸盐溶液，如“Bondal”溶液，这种溶液可以从Canning Gumm公司(Kearny，NJ，USA)买到。优选地，锌酸盐在大约15℃到50℃；浸泡持续几秒到5分钟的时间，并可以在分离的暴露区重复进行。锌层(图3中的301)可以仅是薄膜，但应该不间断地覆盖铝表面。其功能是单独地建立后续镍层与铝的可靠粘附性。
【0046】淀积镍层302从而使淀积溶液不与锌层发生电化学反应。因此，优选通过非电镀方法来淀积镍层。通常，溶液在-25℃到+60℃并且淀积持续1-10分钟。优选的非电镀镍层的厚度302为约0.5μm到3μm。作为替代，可以使用碱性电镀镍工艺。两个层301和302的总厚度在650nm到4000nm的范围内。
【0047】图3中实施例的最外层303包括从钯、铑、金和银中选择的贵金属；优选为钯。优选通过非电镀方法淀积贵金属层。层303的厚度优选在10nm和75nm之间；其主要用途是防止镍表面氧化，并以此确保其可靠的可焊接性。作为替代，贵金属层可以由两个贵金属层的堆叠组成，例如镍层上的钯层和钯层上的最外面的金层。
【0048】根据需要，通常基于锡或锡合金的回流焊接金属层可以被淀积；在这种情况下，不需要贵金属层303。
【0049】虽然已经通过参考示例性实施例描述了本发明，但并不希望从限制的意义上解读该说明书。通过参考本说明书，这些示例性实施例的多种变化和组合以及本发明的其他实施例对本领域技术人员来说是显而易见的。例如，本发明适用于使用任何类型的半导体芯片、分立或集成电路的产品，并且半导体芯片的材料可包含用于集成电路制造的硅、硅锗、砷化镓或其它半导体或化合物材料。
【0050】作为另一个示例，从基础金属片刻蚀出引线框架的工艺步骤可跟随在选择性刻蚀特别是暴露的基础金属表面的工艺步骤之后，由此产生大面积轮廓表面以改善对成型化合物的粘附性。依照本发明的镀层序列可以适应这些特殊刻蚀的引线框架基础结构中的任何一种。
【0051】因此希望要求保护的本发明包含所有这些变化或实施例。

Claims (8)

1.一种不带有悬臂引线的半导体器件，其包含：
由铝合金制成的引线框架，所述引线框架具有包括芯片安放垫和多个引线段的结构；
半导体芯片，其附着到所述芯片安放垫；
导电连接，其从所述芯片跨越到所述引线段的铝表面；
聚合封装材料，其覆盖所述芯片、所述连接以及所述铝引线段的部分；
锌层，其位于那些引线段部分的铝之上，所述引线段部分没有被所述封装材料覆盖；
所述锌层上的镍层；以及
所述镍层上的贵金属层。
2.根据权利要求1所述的器件，还包含位于所述引线段部分上的回流金属，所述引线段部分具有镍层。
3.根据权利要求1或2所述的器件，其中所述贵金属是钯；并且所述器件还包括在钯层上的金层。
4.一种加工不带有悬臂引线的半导体器件的方法，其包含以下步骤：
提供铝合金片；
从所述片刻蚀出引线框架结构，所述结构包括芯片安放垫和适用于不带有悬臂引线的器件的多个引线段；
提供具有焊盘的半导体芯片；
在所述芯片安放垫上安放所述芯片；
把所述芯片焊盘互联到各自引线段的铝表面上；
把所述芯片、所述互联以及所述铝引线段的部分封装到聚合材料中，从而使所述引线段不具有悬臂部分；
在没有被聚合材料覆盖的那些引线段部分的铝上形成锌层；
在所述锌层上形成镍层；以及
在所述镍层上形成贵金属层，从而使所述引线段部分适应焊接附着。
5.根据权利要求4所述的方法，其中所述贵金属层包括钯层和最外面的金层。
6.根据权利要求4或5所述的方法，其中形成锌层的步骤包括以下步骤：
通过在封装步骤后将所述器件浸入碱溶液中，清洗没有被聚合材料覆盖的那些铝引线段部分；
通过将所述器件浸入酸溶液中，活化被清洗的铝引线段部分；以及
通过将所述器件浸入锌酸盐镀液中，溶解被活化的引线段部分上的任何氧化铝，并在这些部分上形成锌层。
7.一种加工不带有悬臂引线的半导体器件的方法，其包含以下步骤：
提供铝合金片；
从所述片刻蚀出引线框架条，所述条包括多个单元，每个单元包括芯片安放垫和适用于不带有悬臂引线的器件的多个引线段；
提供具有焊盘的半导体芯片；
在每个各自单元的所述芯片安放垫上安放一个芯片；
把每个芯片的所述焊盘互联到每个单元的各自引线段的铝表面上；
把每个单元的所述芯片、所述互联以及所述铝引线段的部分封装到聚合材料中；
单粒化所述条上的被封装单元，从而使所述引线段不具有悬臂部分并且选择的聚合支撑条继续连接所述单元并保持所述条连贯；
在没有被聚合材料覆盖的那些铝引线段部分上形成锌层，所述铝引线段部分包括由所述单粒化步骤形成的铝段表面；
在所述锌层上形成镍层；以及
在所述镍层上形成贵金属层，从而使所述引线段部分适应焊接附着。
8.根据权利要求7所述的方法，还包含在形成所述贵金属层的步骤后断开所述聚合物支撑条的步骤，从而分离完成的器件。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103178003A (zh) * 2013-03-27 2013-06-26 中国航天科技集团公司第九研究院第七七一研究所 一种基于镍钯金镀层的金线键合互连方法
CN106835084A (zh) * 2017-02-28 2017-06-13 西安微电子技术研究所 一种在半导体裸芯片上实现键合金属化改性的方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7061096B2 (en) * 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
DE102006015447B4 (de) * 2006-03-31 2012-08-16 Infineon Technologies Ag Leistungshalbleiterbauelement mit einem Leistungshalbleiterchip und Verfahren zur Herstellung desselben
JP2008258411A (ja) * 2007-04-05 2008-10-23 Rohm Co Ltd 半導体装置および半導体装置の製造方法
US8106489B1 (en) * 2007-05-25 2012-01-31 Cypress Semiconductor Corporation Integrated circuit package and packaging method
US7932587B2 (en) * 2007-09-07 2011-04-26 Infineon Technologies Ag Singulated semiconductor package
US8076003B2 (en) * 2008-09-26 2011-12-13 Infineon Technologies Ag Coating composition and a method of coating
US20150035166A1 (en) * 2009-01-29 2015-02-05 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure
US9899349B2 (en) 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
US10163766B2 (en) 2016-11-21 2018-12-25 Semiconductor Components Industries, Llc Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks
US10199311B2 (en) 2009-01-29 2019-02-05 Semiconductor Components Industries, Llc Leadless semiconductor packages, leadframes therefor, and methods of making
CN102117753A (zh) * 2010-01-05 2011-07-06 飞思卡尔半导体公司 封装半导体器件的方法
US8836101B2 (en) 2010-09-24 2014-09-16 Infineon Technologies Ag Multi-chip semiconductor packages and assembly thereof
US20160056098A9 (en) * 2012-09-28 2016-02-25 Yan Xun Xue Semiconductor device employing aluminum alloy lead-frame with anodized aluminum
US20150262919A1 (en) * 2014-03-14 2015-09-17 Texas Instruments Incorporated Structure and method of packaged semiconductor devices with qfn leadframes having stress-absorbing protrusions
CN205282448U (zh) 2015-05-28 2016-06-01 意法半导体股份有限公司 表面安装类型半导体器件
JP6840466B2 (ja) * 2016-03-08 2021-03-10 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及び半導体パッケージの製造方法
CN109788643A (zh) * 2017-11-10 2019-05-21 泰连公司 铝基可焊接的触头
JP7051508B2 (ja) * 2018-03-16 2022-04-11 ローム株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097651A (ja) * 1983-11-02 1985-05-31 Hitachi Ltd 半導体装置
JP2858196B2 (ja) * 1993-04-17 1999-02-17 株式会社三井ハイテック 半導体装置用リードフレーム
TW457674B (en) * 1999-03-15 2001-10-01 Texas Instruments Inc Aluminum leadframes for semiconductor devices and method of fabrication
US6747343B2 (en) 2000-03-08 2004-06-08 Texas Instruments Incorporated Aluminum leadframes with two nickel layers
US6387732B1 (en) 1999-06-18 2002-05-14 Micron Technology, Inc. Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby
JP2003023134A (ja) * 2001-07-09 2003-01-24 Hitachi Ltd 半導体装置およびその製造方法
JP3618316B2 (ja) * 2001-11-21 2005-02-09 株式会社三井ハイテック 半導体装置の製造方法
JP3865055B2 (ja) * 2001-12-28 2007-01-10 セイコーエプソン株式会社 半導体装置の製造方法
US20030178707A1 (en) * 2002-03-21 2003-09-25 Abbott Donald C. Preplated stamped small outline no-lead leadframes having etched profiles
US6872599B1 (en) * 2002-12-10 2005-03-29 National Semiconductor Corporation Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)
US7125747B2 (en) 2004-06-23 2006-10-24 Advanced Semiconductor Engineering, Inc. Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe
US7507605B2 (en) * 2004-12-30 2009-03-24 Texas Instruments Incorporated Low cost lead-free preplated leadframe having improved adhesion and solderability

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103178003A (zh) * 2013-03-27 2013-06-26 中国航天科技集团公司第九研究院第七七一研究所 一种基于镍钯金镀层的金线键合互连方法
CN106835084A (zh) * 2017-02-28 2017-06-13 西安微电子技术研究所 一种在半导体裸芯片上实现键合金属化改性的方法

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