CN101388376B - Semi-conductor package substrate construction - Google Patents
Semi-conductor package substrate construction Download PDFInfo
- Publication number
- CN101388376B CN101388376B CN 200710145395 CN200710145395A CN101388376B CN 101388376 B CN101388376 B CN 101388376B CN 200710145395 CN200710145395 CN 200710145395 CN 200710145395 A CN200710145395 A CN 200710145395A CN 101388376 B CN101388376 B CN 101388376B
- Authority
- CN
- China
- Prior art keywords
- electric connection
- connection pad
- circuit board
- package substrate
- conductive pole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The invention discloses a semiconductor packaging base plate structure, which comprises a circuit board which is provided with a plurality of first electric connection pads on at least one surface thereof, a conducting post which is arranged on the surfaces of the first electric connection pads, and an insulating protective layer which is arranged on the surface of the circuit body, and is provided with open holes to expose the conducting post, wherein the conducting post is projected out the surface of the insulating protective layer in order to electrically connect with a semiconductor chip easily, and to guarantee the quality and reliability of the past packaging process.
Description
Technical field
The present invention relates to a kind of conductor package substrate construction, refer to a kind of on the electric connection pad of circuit board surface, formation and the extraneous structure of making the conducting element of electric connection especially.
Background technology
Cover in crystalline substance (Flip Chip) technology existing, on the active surface of the semiconductor chip of integrated circuit (IC), has electronic pads, and organic circuit board also has the electric connection pad of corresponding this electronic pads, be formed with scolding tin structure or other conducting adhesion material between the electric connection pad of the electronic pads of this semiconductor chip and circuit board, this scolding tin structure or conducting adhesion material provide electric connection and the mechanical connection between this semiconductor chip and the circuit board.
As shown in Figure 1, Flip Chip is that a plurality of metal couplings 11 are formed on the electronic pads 121 of semiconductor chip 12, and a plurality ofly be formed on the electric connection pad 141 of a circuit board 14 by the made pre-scolding tin structure 13 of scolder, with the metal coupling 11 of this semiconductor chip 12 to cover the pre-scolding tin structure 13 of crystal type corresponding to circuit board 14, and be enough to make under the reflow temperature condition of these pre-scolding tin structure 13 fusions, to corresponding metal coupling 11, make this semiconductor chip 12 electrically connect this circuit board 14 pre-scolding tin structure 13 reflows.
See also Fig. 2 A to Fig. 2 D, for having the method for making cross-sectional schematic that on circuit board, is pre-formed the scolding tin structure now.
Shown in Fig. 2 A, the circuit board 20 that provides a surface to have electric connection pad 201.
Shown in Fig. 2 B, being formed with one in these circuit board 20 surfaces is insulating protective layer 21 as welding resisting layer, and through the exposure imaging processing procedure to expose this electric connection pad 201.
Shown in Fig. 2 C, then, the electric connection pad 201 in these circuit board 20 surfaces is formed with a following layer 22, forms pre-scolding tin 23 in the mode of electroplating or print again.But, still there are some problems in Flip Chip, for example chip scale encapsulation usefulness covers brilliant substrate (Flip-ChipChip Scale Package, FCCSP), this thickness that covers brilliant substrate is very thin little, therefore be easy to generate plate and stick up, and the circuit board surface of strip has a plurality of base board units, easily cause the surface to form problems such as low and production cycle (Cycle time) of processing procedure complexity, the yield of pre-scolding tin is long; The pre-scolding tin 23 on these electric connection pad 201 surfaces highly is not all in same level height in addition, and the pre-scolding tin 23 ' of part highly is below or above normal pre-scolding tin 23, and between this conducting element 23,23 ' a difference in height e is arranged.
Shown in Fig. 2 D, be the highly irregular problem of the conducting element 23 that solves these circuit board 20 surfaces, then flatten (coining) processing procedure, in the hope of the height of those pre-scolding tin 23 preferable planarization is arranged by fashion of extrusion, but the leveling processing procedure can't be with all once levelings of all conducting elements 23 on these circuit board 20 surfaces, and must progressively flatten the part, though so can solve the problem of local evenness, expend man-hour and cost.
See also Fig. 3, for semiconductor chip 31 to cover the schematic diagram that crystalline substance is electrically connected at this circuit board 32, these circuit board 32 surfaces have electric connection pad 321, and be formed with an insulating protective layer 33 in these circuit board 32 surfaces, and this insulating protective layer 33 is formed with perforate 330 to expose this electric connection pad 321 part surfaces, and these electric connection pad 321 surfaces are formed with following layer 322, but it highly still is lower than this insulating protective layer 33 surfaces; And this semiconductor chip 31 has electronic pads 311, be formed with a metal coupling 34 in these electronic pads 311 surfaces, make the metal coupling 34 of this semiconductor chip 31 corresponding, and carry out back welding process and make this metal coupling 34 be electrically connected at electric connection pad 321 surfaces of this circuit board 32 with the electric connection pad 321 of circuit board 32.
But, the height of this insulating protective layer 33 is not smooth fully, the height of part can be higher or lower than average height, make and produce a difference in height e ' between insulating protective layer 33 surfaces of zones of different, be formed with perforate 330 in insulating protective layer 33, manifesting electric connection pad 321, the metal coupling 34 of this semiconductor chip 31 is connected with this electric connection pad 321, and is easy to generate skew or electrically connects condition of poor; Especially nonisulated protective layer definition (promptly this weld pad is not covered by insulating protective layer for Non SolderMask Defined, NSMD) product is more serious.
Therefore; how a kind of conductor package substrate electric connection structure and method for making are proposed; avoid conducting element height out-of-flatness in the prior art; and the height inequality of this insulating protective layer; cause producing skew between this semiconductor chip and the base plate for packaging and electrically connecting bad defective, become the problem that present industry is demanded urgently overcoming in fact.
Summary of the invention
In view of the defective of above-mentioned prior art, main purpose of the present invention is to provide a kind of conductor package substrate construction, must form smooth conductive pole, influences the reliability of follow-up encapsulation procedure to exempt prewelding tin out-of-flatness.
Another purpose of the present invention is to provide a kind of conductor package substrate construction, is higher than insulating protective layer by forming conductive pole and this conductive pole height, with easily and the projection of die terminals electrically connect.
For reaching above-mentioned and other purpose, the present invention proposes a kind of conductor package substrate construction, comprising: circuit board has a plurality of first electric connection pads at least one surface of this circuit board; Conductive pole is formed at this first electric connection pad surface; And insulating protective layer, be formed at this circuit board surface, and be formed with perforate exposing this conductive pole fully, and this conductive pole protrudes this insulation protection laminar surface.
Comprise that again a conductive layer is formed between this circuit board and first electric connection pad, the material of this conductive layer can be selected from wherein one of copper, tin, nickel, chromium, titanium and copper one group that evanohm is formed, or the material of this conductive layer is conducting polymer, and this conductive layer the best is Copper Foil or electroless-plating copper.
This circuit board surface includes the circuit and second electric connection pad again, between this circuit board and circuit, between this circuit board and first electric connection pad, and has a conductive layer between this circuit board and second electric connection pad.
This first electric connection pad is weld pad (solder pad), and this first electric connection pad surface has this conductive pole, and this second electric connection pad is wire pad (wire bounding pad), and be lower than this insulation protection laminar surface, has a following layer in this conductive pole surface and the second electric connection pad surface, in order to avoiding this conductive pole and second electric connection pad surface to produce oxidative phenomena, and strengthen and quality that other element connects; Or directly be formed with a conducting element in this conductive pole surface.
The material of this insulating protective layer is sensing optical activity dielectric material such as welding resisting layer (soldermask), this sensing optical activity dielectric material is wherein one of liquid state and a dry film, this liquid sensing optical activity dielectric material is to be formed at this circuit board surface with printing or non-mode of printing, wherein this non-mode of printing can be roll extrusion rubbing method (roller coating), ripples is dripped the spraying coating (spray coating) of formula, wherein one of dipping bath coating (dipping coating) or rotary coating (spincoating), and the sensing optical activity dielectric material of this dry film is to be formed at this circuit board surface with the applying method; And this insulating protective layer comprises again and is formed with another perforate to expose this second electric connection pad.
The method for making of aforesaid semiconductor package substrate construction comprises: a circuit board is provided; Be formed with a plurality of first electric connection pads and circuit in this circuit board surface plating; Be formed with conductive pole in this first electric connection pad electroplating surface; And being formed with an insulating protective layer in this circuit board surface and conductive pole surface, this insulating protective layer is formed with perforate exposing this conductive pole fully, and makes this conductive pole protrude from this insulation protection laminar surface.
This circuit board surface comprises again and is formed with the circuit and second electric connection pad; This circuit board surface forms the method for making of first, second electric connection pad and circuit, comprising: at least one surface in this circuit board is formed with a conductive layer; Be formed with one first resistance layer in this conductive layer surface, and this first resistance layer is formed with the conductive layer of opening with exposed portions serve; And the conductive layer surface in this first resistance layer opening is formed with this first, second electric connection pad and circuit.
This first electric connection pad surface forms the method for making of this conductive pole, and comprising: be formed with one second resistance layer in this first resistance layer, first electric connection pad and circuit surface, this second resistance layer is formed with opening to expose this first electric connection pad surface; Be formed with conductive pole in this first electric connection pad electroplating surface; And remove this first, second resistance layer and conductive layer; Wherein this second resistance layer opening appears whole upper surfaces of this first electric connection pad or part upper surface, the conductive pole external diameter is equated or less than this first electric connection pad.
This first electric connection pad is weld pad (solder pad), and this first electric connection pad surface has this conductive pole, and this second electric connection pad is wire pad (wire bounding pad), and be lower than this insulation protection laminar surface, form a following layer in this conductive pole surface and second electric connection pad surface, in order to avoiding this conductive pole and second electric connection pad surface to produce oxidative phenomena, and strengthen and quality that other element connects; Or directly form a conducting element in this conductive pole surface.
The material of this insulating protective layer is sensing optical activity dielectric material such as welding resisting layer (soldermask), this sensing optical activity dielectric material is wherein one of liquid state and a dry film, this liquid sensing optical activity dielectric material is to be formed at this circuit board surface with printing or non-mode of printing, wherein this non-mode of printing can be roll extrusion rubbing method (roller coating), ripples is dripped the spraying coating (spray coating) of formula, wherein one of dipping bath coating (dipping coating) or rotary coating (spincoating), and the sensing optical activity dielectric material of this dry film is to be formed at this circuit board surface with the applying method; And this insulating protective layer comprises again and is formed with another perforate to expose this second electric connection pad.
In sum; conductor package substrate construction of the present invention; be to form a conductive layer earlier in this circuit board surface; form this electric connection pad and conductive pole by this conductive layer to electroplate; after removing this conductive layer, form an insulating protective layer again in this circuit board surface and conductive pole surface; because this conductive pole is higher than this circuit board surface; thereby behind the patterned processing procedure of this insulating protective layer; this conductive pole is exposed fully; and be nonisulated protective layer definition (Non-Solder MaskDefined; NSMD) weld pad; and make this conductive pole protrude from this insulation protection laminar surface; and the projection of easy and die terminals electrically connects, and guarantees the quality and the reliability of follow-up encapsulation procedure.
Description of drawings
Fig. 1 is the generalized section of existing flip chip structure;
Fig. 2 A to Fig. 2 D is prior art is pre-formed the scolding tin structure on this circuit board a method for making cross-sectional schematic;
Fig. 3 is for having semiconductor chip now to cover the schematic diagram that crystalline substance is electrically connected at circuit board;
Fig. 4 A to Fig. 4 I is the cross-sectional schematic of method for making first embodiment of conductor package substrate construction of the present invention;
Fig. 4 I ' is the cross-sectional schematic of another embodiment of Fig. 4 I;
Fig. 5 A to Fig. 5 I is the method for making cross-sectional schematic of method for making second embodiment of conductor package substrate construction of the present invention;
Fig. 5 I ' is the cross-sectional schematic of another embodiment of Fig. 5 I;
Fig. 6 A to Fig. 6 I is the method for making cross-sectional schematic of method for making the 3rd embodiment of conductor package substrate construction of the present invention; And
Fig. 7 A to Fig. 7 I is the method for making cross-sectional schematic of method for making the 4th embodiment of conductor package substrate construction of the present invention.
The main element symbol description
11,34 metal couplings
12,31 semiconductor chips
121,311 electronic padses
13 pre-scolding tin structures
14,20,32,40 circuit boards
141,201,321 electric connection pads
21,33,46 insulating protective layers
22,48 following layers
23,23 ' pre-scolding tin
49 conducting elements
420,440 openings
330,460 perforates
41 conductive layers
42 first resistance layers
43a first electric connection pad
The 43b circuit
43c second electric connection pad
44 second resistance layers
45 conductive poles
E, e ' difference in height
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
First embodiment
Seeing also Fig. 4 A to Fig. 4 I ', is the generalized section that shows the conductor package substrate construction first embodiment method for making of the present invention.
Shown in Fig. 4 A, one circuit board 40 at first is provided, be formed with a conductive layer 41 in the surface of this circuit board 40, the material of this conductive layer 41 can be selected from wherein one of copper, tin, nickel, chromium, titanium and group that copper-evanohm is formed, or the material of this conductive layer 41 is conducting polymer, and this conductive layer the best is Copper Foil or electroless-plating copper.
Shown in Fig. 4 B, be formed with first resistance layer 42 for dry film or liquid photoresistance in these conductive layer 41 surfaces, and this first resistance layer 42 is formed with the conductive layer 41 of opening 420 with exposed portions serve.
Shown in Fig. 4 C, by the current conduction path of this conductive layer 41 as plating, be formed with at least one first electric connection pad 43a and circuit 43b with conductive layer 41 surfaces in this first resistance layer opening 420, wherein this first electric connection pad 43a can be as weld pad (solder pad) in successive process.
Shown in Fig. 4 D, be formed with second resistance layer 44 for dry film or liquid photoresistance in this first resistance layer 42, the first electric connection pad 43a and circuit 43b surface, and this second resistance layer 44 is formed with opening 440 to expose this first electric connection pad 43a, and wherein this second resistance layer opening 440 appears the whole upper surfaces of this first electric connection pad 43a.
Shown in Fig. 4 E, as the current conduction path of electroplating, form a conductive pole 45 with the first electric connection pad 43a electroplating surface in this second resistance layer opening 440 by this conductive layer 4l.
Shown in Fig. 4 F, in modes such as stripping (Strip) and etchings this second resistance layer 44, first resistance layer 42 and the conductive layer 41 that covered thereof are removed, this conductive pole 45 is exposed fully; Because removing the processing procedure of this first resistance layer 42, second resistance layer 44 and conductive layer 41 is to belong to prior art, so no longer give unnecessary details for literary composition in this.
Shown in Fig. 4 G, then, be formed with an insulating protective layer 46 in these circuit board 40 surfaces and conductive pole 45 surfaces; The material of this insulating protective layer 46 is sensing optical activity dielectric material such as welding resisting layer (solder mask); this sensing optical activity dielectric material is wherein one of liquid state and a dry film; this liquid sensing optical activity dielectric material is to be formed at this circuit board 40 surfaces with printing or non-mode of printing; wherein this non-mode of printing can be roll extrusion rubbing method (roller coating); ripples is dripped the spraying coating (spray coating) of formula; wherein one of dipping bath coating (dipping coating) or rotary coating (spin coating), and the sensing optical activity dielectric material of this dry film is to be formed at this circuit board 40 surfaces with the applying method.
Shown in Fig. 4 H; this insulating protective layer 46 carries out exposure imaging to form perforate 460 then; and expose this conductive pole 45 fully; and be non-welding resisting layer definition (Non-Solder MaskDefined; NSMD) weld pad, behind the insulating protective layer 46 that removes these conductive pole 45 surfaces, this conductive pole 45 promptly exceeds this insulating protective layer 46 surfaces; make this conductive pole 45 protrude these insulating protective layer 46 surfaces, wherein the external diameter of this conductive pole 45 is equal to this first electric connection pad 43a.
Shown in Fig. 4 I, be formed with a following layer 48 in these conductive pole 45 surfaces, the material of this following layer 48 is the tin (Sn) of nickel/gold (Ni/Au), the chemical deposition of chemical deposition, the nickel/palladium/gold (Ni/Pd/Au) of chemical deposition, nickel/gold (Ni/Au) of electroplating, the tin of electroplating (Sn), tin/lead (Sn/Pb) of electroplating, have organizational security layer (OSP) to reach directly soaks wherein one of gold (DIG).
Shown in Fig. 4 I ', also can be directly in these conductive pole 45 surfaces to electroplate and printing wherein one is formed with a conducting element 49, for electrically connecting other electronic installation; This conducting element 49 is solder projection (Solder Bump), and wherein the material of this solder projection is wherein one of tin (Sn), Xi-Yin (Sn-Ag), tin-silver-copper (Sn-Ag-Cu), tin-lead (Sn-Pb) and tin-copper (Sn-Cu).
Conductor package substrate construction of the present invention comprises: circuit board 40 has a plurality of first electric connection pad 43a at least one surface of this circuit board 40; Conductive pole 45 is formed at this first electric connection pad 43a surface; And insulating protective layer 46, be formed at this circuit board 40 surfaces, and be formed with perforate 460 exposing this conductive pole 45 fully, and this conductive pole 45 protrudes these insulating protective layer 46 surfaces, wherein the external diameter of this conductive pole 45 is equal to this first electric connection pad 43a.
These circuit board 40 surfaces include circuit 43b again, and comprise that again a conductive layer 41 is formed between this circuit board 40 and the first electric connection pad 43a, the circuit 43b, the material of this conductive layer 41 can be selected from wherein one of copper, tin, nickel, chromium, titanium and copper-evanohm group that alloy is formed, or the material of this conductive layer 41 is a conducting polymer; Have a following layer 48 in these conductive pole 45 surfaces, the material of this following layer 48 is the tin (Sn) of nickel/gold (Ni/Au), the chemical deposition of chemical deposition, the nickel/palladium/gold (Ni/Pd/Au) of chemical deposition, nickel/gold (Ni/Au) of electroplating, the tin of electroplating (Sn), tin/lead (Sn/Pb) of electroplating, have organizational security layer (OSP) to reach directly soaks wherein one of gold (DIG); Or having a conducting element 49 in these conductive pole 45 surfaces, this conducting element 49 is solder projection (Solder Bump); Wherein the material of this solder projection is tin (Sn), Xi-Yin (Sn-Ag), tin-silver-copper (Sn-Ag-Cu), tin-lead (Sn-Pb) or tin-copper (Sn-Cu).
Second embodiment
Seeing also Fig. 5 A to Fig. 5 I ', is the generalized section that shows the conductor package substrate construction second embodiment method for making of the present invention.
Fabrication steps and the structure of present embodiment Fig. 5 A to Fig. 5 I ', Fig. 5 A to Fig. 5 C wherein is that the method for making shown in Fig. 4 A to Fig. 4 C with first embodiment is identical; But it is inequality as those shown after Fig. 5 D, be to be formed with second resistance layer 44 for dry film or liquid photoresistance in this first resistance layer 42, the first electric connection pad 43a and circuit 43b surface, and this second resistance layer 44 is formed with opening 440 to expose this first electric connection pad 43a, and wherein this second resistance layer opening 440 manifests the first electric connection pad 43a part upper surface; Shown in Fig. 5 E to Fig. 5 G, be in this second resistance layer opening 440, electroplate to form this conductive pole 45, can form conductive pole 45 external diameters shown in 5H, Fig. 5 I and Fig. 5 I ' less than the structure of this first electric connection pad 43a.
The 3rd embodiment
Seeing also Fig. 6 A to Fig. 6 I, is the generalized section that shows conductor package substrate construction the 3rd embodiment method for making of the present invention; Have first, second electric connection pad and circuit with different being in of this first and second embodiment in this circuit board surface.
As shown in Figure 6A, at first provide a circuit board 40, be formed with a conductive layer 41 in the surface of this circuit board 40.
Shown in Fig. 6 B, be formed with one first resistance layer 42 in these conductive layer 41 surfaces, and this first resistance layer 42 is formed with the conductive layer 41 of opening 420 with exposed portions serve.
Shown in Fig. 6 C, by the current conduction path of this conductive layer 41 as plating, be formed with at least one first electric connection pad 43a, circuit 43b and the second electric connection pad 43c with conductive layer 41 surfaces in this first resistance layer opening 420, wherein this first electric connection pad 43a can be as weld pad (solder pad) in successive process, and this second electric connection pad 43c then can be used as wire pad (wire bounding pad).
Shown in Fig. 6 D, be formed with one second resistance layer 44 in this first resistance layer 42, conductive layer 41, the first electric connection pad 43a, circuit 43b and the second electric connection pad 43c surface, and this second resistance layer 44 is formed with opening 440 and only exposes this first electric connection pad 43a, and wherein this second resistance layer opening 440 manifests the whole upper surfaces of the first electric connection pad 43a.
Shown in Fig. 6 E, as the current conduction path of electroplating, form a conductive pole 45 with the first electric connection pad 43a electroplating surface in this second resistance layer opening 440 by this conductive layer 41.
Shown in Fig. 6 F, in modes such as stripping (Strip) and etchings this second resistance layer 44, first resistance layer 42 and the conductive layer 41 that covered thereof are removed, this conductive pole 45, circuit 43b and the second electric connection pad 43c are exposed fully.
Shown in Fig. 6 G, then, in these circuit board 40 surfaces, conductive pole 45 and the second electric connection pad 43c surface be formed with an insulating protective layer 46; The material of this insulating protective layer 46 is sensing optical activity dielectric material such as welding resisting layer (solder mask); this sensing optical activity dielectric material is wherein one of liquid state and a dry film; this liquid sensing optical activity dielectric material is to be formed at this circuit board 40 surfaces with printing or non-mode of printing; wherein this non-mode of printing can be roll extrusion rubbing method (roller coating); ripples is dripped the spraying coating (spray coating) of formula; wherein one of dipping bath coating (dipping coating) or rotary coating (spin coating), and the sensing optical activity dielectric material of this dry film is to be formed at this circuit board 40 surfaces with the applying method.
Shown in Fig. 6 H; this insulating protective layer 46 carries out exposure imaging to form perforate 460 then; and expose this conductive pole 45 fully; and expose this second electric connection pad 43c; behind the insulating protective layer 46 that removes these conductive pole 45 surfaces; this conductive pole 45 promptly exceeds this insulating protective layer 46 surfaces; make this conductive pole 45 protrude these insulating protective layer 46 surfaces; and the external diameter of this conductive pole 45 is equal to this first electric connection pad 43a, and this second electric connection pad 43c then is lower than this insulating protective layer 46 surfaces.
Shown in Fig. 6 I, be formed with a following layer 48 in this conductive pole 45 and the second electric connection pad 43c surface, wherein this following layer 48 can chemical deposition form nickel/palladium/gold (Ni/Pd/Au) or nickel/gold (Ni/Au).
Conductor package substrate construction of the present invention comprises: circuit board 40 has a plurality of first electric connection pad 43a and the second electric connection pad 43c at least one surface of this circuit board; Conductive pole 45 is formed at this first electric connection pad 43a surface; And insulating protective layer 46, be formed at this circuit board 40 surfaces, and be formed with perforate 460 exposing this conductive pole 45 fully, and this conductive pole 45 protrudes these insulating protective layer 46 surfaces.
These circuit board 40 surfaces include circuit 43b again, and this first electric connection pad 43a is weld pad (solder pad), and this first electric connection pad 43a surface has this conductive pole 45, and this second electric connection pad 43c is wire pad (wire bounding pad); Comprise that again a conductive layer 41 is formed between this circuit board 40 and first, second electric connection pad 43a, 43c and the circuit 43b; This conductive pole 45 and second electric connection pad 43c surface form a following layer 48, and wherein this following layer 48 can chemical deposition form nickel/palladium/gold (Ni/Pd/Au) or nickel/gold (Ni/Au).
The 4th embodiment
Seeing also Fig. 7 A to Fig. 7 I, is the generalized section that shows conductor package substrate construction the 4th embodiment method for making of the present invention.
Fabrication steps and the structure of present embodiment Fig. 7 A to Fig. 7 I, wherein this Fig. 7 A to Fig. 7 C is identical with Fig. 6 A to Fig. 6 C of the 3rd embodiment, but as those shown's difference after Fig. 7 D, be to be formed with second resistance layer 44 for dry film or liquid photoresistance in this first resistance layer 42, the first electric connection pad 43a and circuit 43b surface, and this second resistance layer 44 is formed with opening 440 to expose this first electric connection pad 43a, and wherein this second resistance layer opening 440 manifests the first electric connection pad 43a part upper surface; Shown in Fig. 7 E to Fig. 7 G, be in this second resistance layer opening 440, electroplate to form this conductive pole 45, can form conductive pole 45 external diameters shown in Fig. 7 H and Fig. 7 I less than the structure of this first electric connection pad 43a.
In sum; conductor package substrate construction of the present invention; be to form a conductive layer earlier in this circuit board surface; form this circuit by this conductive layer to electroplate; first electric connection pad and conductive pole; perhaps and be formed with second electric connection pad; after removing this conductive layer, form an insulating protective layer again in this circuit board surface and conductive pole surface; when this insulating protective layer forms perforate with after exposing this conductive pole fully; this conductive pole promptly is higher than this insulation protection laminar surface; and be nonisulated protective layer definition (Non-Solder Mask Defined; NSMD) weld pad; this conductive pole is higher than the insulation protection laminar surface; and the projection of easy and die terminals electrically connects, and guarantees the quality and the reliability of follow-up encapsulation procedure.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention should be foundation with the scope of claims.
Claims (11)
1. conductor package substrate construction comprises:
Circuit board has a plurality of first electric connection pads at least one surface of this circuit board;
Conductive pole is formed at this first electric connection pad surface;
Insulating protective layer is formed at this circuit board surface, and is formed with perforate exposing this first electric connection pad and conductive pole provided thereon fully, and this conductive pole protrudes this insulation protection laminar surface; And
Solder projection is formed at this conductive pole surface, and coats this conductive pole and first electric connection pad.
2. conductor package substrate construction according to claim 1, wherein, this circuit board surface comprises circuit again.
3. conductor package substrate construction according to claim 1, wherein, the external diameter of this conductive pole equate with this first electric connection pad and less than wherein one.
4. conductor package substrate construction according to claim 1, wherein, this first electric connection pad is a weld pad.
5. conductor package substrate construction according to claim 1, wherein, this circuit board surface comprises a plurality of second electric connection pads again.
6. conductor package substrate construction according to claim 5, wherein, this insulating protective layer comprises again and is formed with another perforate to expose this second electric connection pad.
7. conductor package substrate construction according to claim 5, wherein, this second electric connection pad is a wire pad, and is lower than this insulation protection laminar surface.
8. conductor package substrate construction according to claim 1 comprises that again a following layer is formed at this conductive pole surface.
9. conductor package substrate construction according to claim 5 comprises that again a following layer is formed at this conductive pole and the second electric connection pad surface.
10. conductor package substrate construction according to claim 8, wherein, the material of this following layer be the tin of nickel/gold, the chemical deposition of chemical deposition, the nickel/palladium/gold of chemical deposition, nickel/gold of electroplating, the tin of electroplating, plating tin/lead, have the organizational security layer to reach directly to soak golden wherein one.
11. conductor package substrate construction according to claim 9, wherein, the material of this following layer is wherein one of the nickel/gold of chemical deposition and nickel/palladium/gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710145395 CN101388376B (en) | 2007-09-14 | 2007-09-14 | Semi-conductor package substrate construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710145395 CN101388376B (en) | 2007-09-14 | 2007-09-14 | Semi-conductor package substrate construction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101388376A CN101388376A (en) | 2009-03-18 |
| CN101388376B true CN101388376B (en) | 2011-11-30 |
Family
ID=40477678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710145395 Active CN101388376B (en) | 2007-09-14 | 2007-09-14 | Semi-conductor package substrate construction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101388376B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074535B (en) * | 2009-11-19 | 2013-08-21 | 瑞鼎科技股份有限公司 | Electronic chip and substrate for providing insulating protection among conductive points |
| CN102237328A (en) * | 2010-04-27 | 2011-11-09 | 瑞鼎科技股份有限公司 | Die structure and die bonding method |
| US20110285013A1 (en) * | 2010-05-20 | 2011-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling Solder Bump Profiles by Increasing Heights of Solder Resists |
| CN102789995B (en) * | 2011-05-20 | 2015-07-22 | 稳懋半导体股份有限公司 | Method of manufacture procedures for manufacturing metal protrusion and fusion welded metal |
| CN102956601A (en) * | 2011-08-18 | 2013-03-06 | 颀邦科技股份有限公司 | Base plate structure with elastic lugs and manufacturing method of base plate structure |
| CN104135815B (en) * | 2013-05-03 | 2018-01-02 | 讯芯电子科技（中山）有限公司 | A kind of board structure of circuit for preventing metal pad to be scraped off and manufacture method |
| CN111164752B (en) * | 2018-05-01 | 2024-02-02 | 西部数据技术公司 | Bifurcated memory die module semiconductor device |
| CN108551725B (en) * | 2018-06-29 | 2020-11-10 | 珠海杰赛科技有限公司 | Method for electroplating nickel and gold on printed circuit board circuit and printed circuit board circuit thereof |
| CN114928958A (en) * | 2022-06-24 | 2022-08-19 | 重庆中电天时精密装备技术有限公司 | PCB and PCBA plane precision press-fitting method |
-
2007
- 2007-09-14 CN CN 200710145395 patent/CN101388376B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101388376A (en) | 2009-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101388376B (en) | Semi-conductor package substrate construction | |
| KR100592609B1 (en) | Method for forming bump and method for making semiconductor device | |
| US7350298B2 (en) | Method for fabricating circuit board with conductive structure | |
| US8164003B2 (en) | Circuit board surface structure and fabrication method thereof | |
| US20060219567A1 (en) | Fabrication method of conductive bump structures of circuit board | |
| KR101034161B1 (en) | Semiconductor package substrate | |
| TWI331494B (en) | Circuit board structure | |
| US6931722B2 (en) | Method of fabricating printed circuit board with mixed metallurgy pads | |
| US20060252248A1 (en) | Method for fabricating electrically connecting structure of circuit board | |
| US20080089046A1 (en) | Printed Wiring Board for Mounting Electronic Components and Semiconductor Device Using Same | |
| TWI301740B (en) | Method for fabricating circuit board with electrically connected structure | |
| CN101290917B (en) | Structure of welding mat | |
| US7216424B2 (en) | Method for fabricating electrical connections of circuit board | |
| CN100534263C (en) | Circuit board conductive lug structure and making method | |
| CN1980530A (en) | Method for making circuit-board conductive lug structure | |
| US5780931A (en) | Surface mounting semiconductor device and semiconductor mounting component | |
| CN101287331B (en) | Conductive structure of electrically connected mat of circuit board | |
| CN1980538A (en) | Method for forming circuit-board electric connection end | |
| CN101360388B (en) | Electricity connection terminal construction of circuit board and preparation thereof | |
| CN1326432C (en) | High-density circuit board without weld pad design and manufacturing method thereof | |
| CN100525589C (en) | A manufacturing method of formation of circuit board electricity connection end | |
| JP3741683B2 (en) | Method of manufacturing film carrier tape for mounting electronic component and plating apparatus usable in this method | |
| JP3965148B2 (en) | Printed wiring board for mounting electronic components, method for manufacturing the same, and semiconductor device | |
| US20130081862A1 (en) | Wiring substrate and method of manufacturing the same | |
| JP3854265B2 (en) | Printed wiring board for mounting electronic components, method for manufacturing the same, and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Effective date: 20110825 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20110825 Address after: China Taiwan Taoyuan County Applicant after: Xinxing Electronics Co., Ltd. Address before: Hsinchu City, Taiwan, China Applicant before: Quanmao Precision Science & Technology Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |