CN101377764A - Allocating system of GPIO and data communicating method thereof - Google Patents
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Abstract
The invention discloses a GPIO configuration system and a data communication method thereof. The configuration system comprises a CPU module, an AMBA bus interface module, an information register module and a GPIO module. The CPU module is used for sending GPIO configuration instructions according to external equipment. The AMBA bus interface module comprises an AHB bus and an APB bus, which further comprises an AHB/APB bridge module connected between the AHB bus and the APB bus. The CPU module is connected with the AHB/APB bridge module through the AHB bus; the information register module is connected with the APB bus, and used for storing configuration instructions. The GPIO module is connected with an information register and the APB bus, which is used for generating operating circuits according to the configuration instructions. The GPIO configuration system and the data communication method achieve the multiplex functions of the same GPIO interface; in addition, GPIO can be reached through two channels so that the GPIO is controlled flexibly.
Description
Technical field
The present invention relates to the interface field of embedded system, specifically, relate to configuration-system and the data communications method thereof of a kind of GPIO.
Background technology
Has One's name is legion in the embedded system, the but simple relatively external unit of structure, for these equipment, the CPU that needs that has provides control device for it, what have need provide input signal for CPU, and many such device just want one, promptly as long as the open and close two states, such as: the lamp light on and off.To the control of the circuit of these equipment, use traditional serial port or parallel port all improper, so, in the microcontroller chip, can provide general programmable input/output interface (General-Purpose IO ports is called for short GPIO).
GPIO is meant the output pin that input signal can be provided for external equipment, and/or by the input pin of input signal is provided for CPU.Because the mode of operation of interfaces for external devices may be different, therefore, need be according to the coupling requirement of interfaces for external devices, the mode by software or software and combination of hardware is configured to various type with GPIO.For example, corresponding if the interface of external equipment is a tri-state mode, GPIO need be configured to tri-state mode; If external equipment is open collector (open-drain) pattern, corresponding, just GPIO need be configured to the open collector pattern.
Because the quantity of external equipment is very many and mode of operation may be different, and in the prior art, each GPIO can only link to each other with external equipment with a kind of pattern, will cause the increase of the quantity of required GPIO like this.For instance, if a control system need connect 20 external equipments, and the interface of these 20 external equipments is the open collector pattern, if the GPIO of 10 open collector patterns is only arranged in the above-mentioned control system, so, existing GPIO can not satisfy the demand of external equipment, can only increase new GPIO interface in system, cause the increase of the quantity of GPIO thus.
Therefore, need the urgent technical matters that solves of those skilled in the art to be exactly: how can carry out multiplexing functions and how can realize flexible configuration to GPIO to reusable GPIO.
Summary of the invention
Technical matters to be solved by this invention provides configuration-system and the data communications method thereof of a kind of GPIO, so that a GPIO can link to each other with the external equipment of distinct interface pattern, thus the quantity of the required GPIO of reduction system.
In order to address the above problem, the invention discloses the configuration-system of a kind of GPIO, comprise CPU, AMBA bus interface module, information register module, GPIO module.Wherein, the CPU module is used for sending the order of GPIO block configuration according to external equipment, the AMBA bus interface module comprises ahb bus and APB bus, also comprises the AHB/APB bridge module that is connected between ahb bus and the APB bus, and the CPU module is connected with the AHB/APB bridge module by ahb bus; The information register module is connected on the APB bus, is used for the stored configuration order; The GPIO module is connected with information register, APB bus respectively, is used for generating operating circuit according to configuration order.
Preferably, configuration order is control signal and data-signal, the operating circuit that operating circuit is complementary for the interface modes with external equipment.
Preferably, GPIO comprises GPIO data register and GPIO control register, and GPIO data register, GPIO control register are connected with information register, APB bus respectively.
Preferably, information register is connected by logic gates with the GPIO data register.
Preferably, information register is connected by logic gates with the GPIO control register.
Preferably, the configuration-system of GPIO also comprises a look-at-me module, and the look-at-me module is connected with CPU, is used to receive the look-at-me of external unit.
The invention also discloses a kind of data transmission method, comprise the steps: that the CPU module sends the order of GPIO block configuration according to external equipment, configuration order is sent to the AHB/APB bridge module through the ahb bus of AMBA bus, and the AHB/APB bridge module is sent to the GPIO module with configuration order through the APB bus; Perhaps, the AHB/APB bridge module with configuration order through APB bus, information register module, be sent to the GPIO module, the GPIO module generates the operating circuit that the interface modes with external equipment is complementary according to configuration order.
Preferably, configuration order is control signal and data-signal.
Preferably, GPIO comprises GPIO data register and GPIO control register, and GPIO data register, GPIO control register are connected with information register, APB bus respectively.
Preferably, CPU is according to the configuration order of external equipment generation GPIO, and perhaps CPU becomes the GPIO configuration order according to the look-at-me module
Compared with prior art, the present invention has the following advantages:
Based on the AMBA interface module, the configuration order that CPU is produced is sent to GPIO control register and GPIO data register, and generate the operating circuit that can be complementary with the interfaces for external devices pattern according to the configuration order in GPIO control register and the GPIO data register, thereby, realized multiplexing functions to same GPIO interface, a GPIO can be linked to each other with the external equipment of distinct interface pattern, thus the quantity of the required GPIO of reduction system; And, because the configuration order that CPU sends can arrive control register and the data register of GPIO via two paths, therefore, when transmitting configuration order, can not be subjected to the restriction of register, therefore flexible relatively to the control of GPIO.
Description of drawings
Fig. 1 is typical system chart based on the AMBA bus;
Fig. 2 is the structured flowchart according to the configuration-system of the GPIO of the embodiment of the invention;
Fig. 3 is the annexation synoptic diagram of the described configuration-system of Fig. 2 on the AMBA bus;
Fig. 4 is the detailed annexation synoptic diagram of the described configuration-system of Fig. 3 on the AMBA bus;
Fig. 5 is the structured flowchart of configuration-system that has the GPIO of interrupt processing mechanism;
Fig. 6 is the process flow diagram according to the data communications method embodiment of the configuration-system that the present invention is based on GPIO;
Fig. 7 is the process flow diagram according to another embodiment of data communications method of the configuration-system that the present invention is based on GPIO.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Core concept of the present invention is: based on the AMBA interface module, the configuration order that CPU is produced is sent to GPIO control register and GPIO data register, and generate the operating circuit that can be complementary with the interfaces for external devices pattern according to the configuration order in GPIO control register and the GPIO data register, thereby, can realize multiplexing functions to same GPIO interface.
With reference to Fig. 1, show a kind of typical system chart based on the AMBA bus, comprise ahb bus 101 and APB bus 107, wherein, ahb bus 101 is connected by AHB/APB bridge 106 with APB bus 107, its major function is address, data and the control signal that latchs from the AHB system bus, and the selection signal of two-stage decode with generation APB peripherals is provided, thereby realizes the conversion of AHB agreement to the APB agreement.
Ahb bus 101 is mainly used in the connection between the high-performance module (as CPU, DMA and DSP etc.), generally is connected with modules such as ARM or CPU module 102, DSP IP module 103, ROM/SRAM module 105, moderator module 104; APB bus 107 is mainly used in the connection between the peripheral peripheral hardware of low bandwidth, generally is connected with modules such as timer 108, GPIO module 109, UART module 110.
The interface of AMBA bus separates with interconnect function, and this is significant to the interconnection between the chip upper module, and on certain angle, the AMBA bus has been not only a kind of bus, a kind of especially interconnection system that has interface module.
With reference to Fig. 2, Fig. 2 is the structured flowchart according to the configuration-system of the GPIO of the embodiment of the invention, comprises as lower module: CPU module 201, AMBA interface module 202, information register module 203, GPIO module 204.Here, CPU module 201 produces the configuration order that is complementary with external equipment according to external equipment, through AMBA interface module 202, configuration order is sent to GPIO module 204.
Particularly,, configuration order is sent to GPIO module 204, dual mode is arranged through AMBA interface module 202,
One, the configuration order of coming out from AMBA interface module 202 is sent to information register module 203, then, through this information register module 203 configuration order is pass on to GPIO module 204;
Its two, the configuration order of coming out from AMBA interface module 202 directly is sent to GPIO module 204.
By above-mentioned two paths, realize control to the GPIO mode of operation, thereby when GP configuring IO, can be more flexible.
With reference to Fig. 3, Fig. 3 is the annexation synoptic diagram of the described configuration-system of Fig. 2 on the AMBA bus:
GPIO comprises two registers, control register 304 and data register 305; The AMBA interface module comprises ahb bus 306 and APB bus 307, and ahb bus 306 is connected by AHB/APB bridge 302 with APB bus 307.CPU301 is connected on the ahb bus 306, and requires to generate configuration order according to the Interface Matching of external equipment, and particularly, configuration order can be control signal and data-signal; Then, the control signal of generation and data-signal are sent on the APB bus 307 through AHB/APB bridge 302, at this moment, have dual mode can realize control to GPIO interface mode of operation:
One: information register 303 reads control signal and the data-signal on the APB bus 307, and transmits signals in GPIO control register 304 and the GPIO data register 305; At last, GPIO control register 304 and GPIO data register 305 will generate the operating circuit that can be complementary with external equipment according to the control signal of its reception and data-signal.
Its two: GPIO control register 304 and GPIO data register 305 read control signal and the data-signal on the APB bus 307, and generate the operating circuit that can be complementary with external equipment according to control signal and data-signal.
Specifically, the above-mentioned operating circuit that can be complementary with external equipment is to generate like this:
On the one hand, the control signal that sends by CPU module 301 of control register 304 is controlled GPIO and is in input state or output state;
On the other hand, the data-signal that CPU module 301 sends writes data register 305, and described data-signal is the data that are complementary with the interfaces for external devices pattern, operating circuit by data in the data register 305 and GPIO interacts, thereby generates the GPIO operating circuit that can be complementary with the interfaces for external devices pattern.
For instance, if external equipment is a tri-state mode, then CPU module 301 will produce the configuration order that comprises control signal Ctrl-sig1 and data-signal Data-sig1 according to external equipment, Ctrl-sig1 and Data-sig1 are passed to GPIO through the AMBA bus, GPIO is according to control signal Ctrl-sig1 and data-signal Data-sig1, the operating circuit 1 that generation can be complementary with ternary interface modes.
If external equipment is the open collector pattern, then CPU module 301 will produce the configuration order that comprises control signal Ctrl-sig2 and data-signal Data-sig2 according to external equipment, Ctrl-sig2 and Data-sig2 are passed to GPIO through the AMBA bus, GPIO is according to control signal Ctrl-sig2 and data-signal Data-sig2, the operating circuit 2 that generation can be complementary with open-collector interface modes, thus, realized the multiplexing of tri-state mode and open collector pattern.
By above-mentioned example as can be seen, for same GPIO pin, can realize the multiplexing of different working modes by above-mentioned configuration-system, and, because the configuration order that CPU 301 sends can arrive control register and the data register of GPIO via two paths, therefore, when transmitting configuration order, can not be subjected to the restriction of register, therefore flexible relatively to the control of GPIO.
With reference to Fig. 4, Fig. 4 is the detailed annexation synoptic diagram of the described configuration-system of Fig. 2 on the AMBA bus,
Wherein, GPIO comprises two registers, control register 404 and data register 405, and the AMBA interface module comprises ahb bus 406 and APB bus 407, ahb bus 306 is connected by AHB/APB bridge 402 with APB bus 307.CPU 401 is connected on the ahb bus 406, and requires to generate configuration order according to the Interface Matching of external equipment, and particularly, configuration order can be control signal and data-signal; Then, the control signal of generation and data-signal are sent on the APB bus 407 through AHB/APB bridge 402, at this moment, have dual mode can realize control to GPIO interface mode of operation:
One: information register 403 reads control signal and the data-signal on the APB bus 407, and signal is sent in GPIO control register 404 and the GPIO data register 405 through logic gates 410,411, at last, GPIO control register 404 and GPIO data register 405 will generate the operating circuit that can be complementary with external equipment according to the data-signal of its reception and data-signal.
Its two: control signal on the APB bus and data-signal are sent to GPIO control register 404 and GPIO data register 405 by logic gates 408,409, generate the operating circuit that can be complementary with external equipment according to control signal and data-signal.
Specifically, the above-mentioned operating circuit that can be complementary with external equipment is to generate like this:
On the one hand, the control signal that sends by CPU module 401 of control register 404 is controlled GPIO and is in input state or output state;
On the other hand, the data-signal that CPU module 401 sends writes data register 405, and described data-signal is the data that are complementary with the interfaces for external devices pattern, operating circuit by data in the data register 405 and GPIO interacts, thereby generates the GPIO operating circuit that can be complementary with the interfaces for external devices pattern.
Need to prove at this: the logic gates 408,409,410,411 shown in the figure is or door, but to be exemplary expression will carry out the logical operation of signal through logic gates from information register or from the signal that the APB bus is come out for this, do not represent actual conditions to be or door, can be other gate circuit, such as with combination of door, not gate, Sheffer stroke gate or logic gate or the like, need and will design according to the needed GPIO mode of operation of external equipment.
With reference to Fig. 5, Fig. 5 is the structured flowchart of configuration-system that has the GPIO of interrupt processing mechanism, comprises as lower module: CPU 501, AMBA interface module 502, information register 503, GPIO 504.And look-at-me module 505, here, the look-at-me that look-at-me module 505 receives by the outside input, and look-at-me sent to CPU 501, CPU 501 is in the high-priority interrupt signal according to default priority configuration information gating, produces and send the configuration order that the interfaces for external devices pattern of this look-at-me is complementary, through AMBA interface module 502, configuration order is sent to GPIO 504, thereby has realized processing respectively the different priorities external equipment.
Similarly,, configuration order is sent to GPIO 504, dual mode is arranged through AMBA interface module 502,
One, the configuration order of coming out from AMBA interface module 502 is sent to information register 503, then, through this information register 503 configuration order is pass on to GPIO 504;
Its two, the configuration order of coming out from AMBA interface module 502 directly is sent to GPIO module 504.
Have the configuration-system of the GPIO of priority by present embodiment, realized processing, utilize the good priority configuration information of predefined, can realize processing respectively, make same GPIO realize multiplexing functions a plurality of signal priorities to signal priority; And, because the configuration order that CPU module 501 sends can arrive control register and the data register of GPIO via two paths, therefore, when transmitting configuration order, be not subjected to the restriction of register, make the configuration of GPIO flexible relatively.
With reference to Fig. 6, Fig. 6 is according to the process flow diagram of the data communications method embodiment of the configuration-system that the present invention is based on GPIO, comprises the steps:
Step 601:CPU module sends the order of GPIO block configuration according to external equipment;
Step 602: configuration order is sent to the AHB/APB bridge module through the ahb bus of AMBA bus;
Step 603:AHB/APB bridge module is sent to GPIO control register and GPIO data register with configuration order through the APB bus;
Step 604: according to the configuration order in described GPIO control register and the GPIO data register, the operating circuit that the pattern of generation and interfaces for external devices is complementary.
Wherein, the configuration order in the step 601 is for being fit to data-signal and the control signal of external equipment to the coupling requirement of GPIO.
The collocation method of present embodiment GPIO, the configuration order that CPU is sent, be that control signal and data-signal directly are forwarded to GPIO control register and GPIO data register through the AMBA bus module, then according to the information of GPIO control register and GPIO data register, the operating circuit that generation and external equipment are complementary, thus realization GPIO's is multiplexing.
With reference to Fig. 7, Fig. 7 is according to the process flow diagram of another embodiment of data communications method of the configuration-system that the present invention is based on GPIO, comprises the steps:
Step 701:CPU module sends the order of GPIO block configuration according to external equipment;
Step 702: configuration order is sent to the AHB/APB bridge module through the ahb bus of AMBA bus;
Step 703:AHB/APB bridge module is sent to configuration order to the information register module through the APB bus;
Step 704: the information register module is sent to control register and data register with configuration order;
Step 705: according to the configuration order in GPIO control register and the GPIO data register, the operating circuit that pattern living and interfaces for external devices is complementary.
Equally, the configuration order in step 701 is for being data-signal and the control signal of suitable external equipment to the coupling requirement of GPIO.
The collocation method of present embodiment GPIO, the configuration order that CPU is sent, be that control signal and data-signal are forwarded to information register through the AMBA bus module, described information register is sent to GPIO control register and GPIO data register with the information of receiving, then according to the information of GPIO control register and GPIO data register, the operating circuit that generation and external equipment are complementary, thus realization GPIO's is multiplexing.
The embodiment of the collocation method by Fig. 6 and two GPIO shown in Figure 7 as can be seen, the present invention can adopt two kinds of methods that GPIO is controlled, a kind of method is without information register, and another kind of method is through information register, when GPIO is carried out the control of multiplexing functions, can compare flexibly.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For system embodiment, because it is similar substantially to method embodiment, so description is fairly simple, relevant part gets final product referring to the part explanation of method embodiment.
More than to configuration-system and the data communications method thereof of a kind of GPIO provided by the present invention, be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1, the configuration-system of a kind of GPIO is characterized in that, comprises CPU, AMBA bus interface module, information register module, GPIO module, wherein,
Described CPU module is used for sending the order of GPIO block configuration according to external equipment;
Described AMBA bus interface module comprises ahb bus and APB bus, also comprises the AHB/APB bridge module that is connected between ahb bus and the APB bus, and described CPU module is connected with described AHB/APB bridge module by described ahb bus;
Described information register module is connected on the described APB bus, is used for the stored configuration order;
Described GPIO module is connected with described information register, described APB bus respectively, is used for generating operating circuit according to described configuration order.
2, the configuration-system of GPIO according to claim 1 is characterized in that, described configuration order is control signal and data-signal, the operating circuit that described operating circuit is complementary for the interface modes with described external equipment.
3, the configuration-system of GPIO according to claim 2, it is characterized in that, described GPIO comprises GPIO data register and GPIO control register, and described GPIO data register, described GPIO control register are connected with described information register, described APB bus respectively.
4, GPIO configuration-system according to claim 3 is characterized in that, described information register is connected by logic gates with described GPIO data register.
5, the configuration-system of GPIO according to claim 4 is characterized in that, described information register is connected by logic gates with described GPIO control register.
According to the configuration-system of each described GPIO in the claim 1 to 5, it is characterized in that 6, also comprise a look-at-me module, described look-at-me module is connected with described CPU, is used to receive the look-at-me of external unit.
7, a kind ofly it is characterized in that, comprising based on the described data communications method of claim 1:
Described CPU module sends the order of GPIO block configuration according to external equipment;
Described configuration order is sent to described AHB/APB bridge module through the ahb bus of described AMBA bus;
Described AHB/APB bridge module is sent to described GPIO module with configuration order through described APB bus; Perhaps, described AHB/APB bridge module passes through described configuration order described APB bus, described information register module, is sent to described GPIO module;
Described GPIO module generates the operating circuit that the interface modes with described external equipment is complementary according to described configuration order.
8, data communications method according to claim 7 is characterized in that, described configuration order is control signal and data-signal.
9, data communications method according to claim 8, it is characterized in that, described GPIO comprises GPIO data register and GPIO control register, and described GPIO data register, described GPIO control register are connected with described information register, described APB bus respectively.
10, data communications method according to claim 9 is characterized in that, described CPU generates the GPIO configuration order and is specially:
Described CPU is according to the configuration order of external equipment generation GPIO, and perhaps described CPU becomes the GPIO configuration order according to described look-at-me module.
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| CN2008102222557A CN101377764B (en) | 2008-09-12 | 2008-09-12 | Allocating system of GPIO and data communicating method thereof |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101901202A (en) * | 2010-07-29 | 2010-12-01 | 东莞市泰斗微电子科技有限公司 | Circuit and method for cross clock domain accessing of AHB bus equipment to APB bus equipment |
| CN102880574A (en) * | 2011-07-11 | 2013-01-16 | 航天信息股份有限公司 | Method for simulating low speed parallel interface by using GPIO (general purpose input output) |
| CN104516853A (en) * | 2014-12-22 | 2015-04-15 | 厦门雅迅网络股份有限公司 | System and method for improving GPIO (general purpose input and output) efficiency under linux |
| CN107992439A (en) * | 2017-10-13 | 2018-05-04 | 武汉高德智感科技有限公司 | A kind of expansible data interactive method and system |
| WO2019136983A1 (en) * | 2018-01-12 | 2019-07-18 | 江苏华存电子科技有限公司 | Low-delay instruction scheduler |
| CN110895518A (en) * | 2019-07-01 | 2020-03-20 | 研祥智能科技股份有限公司 | GPIO (general purpose input/output) interface configuration method and system |
| WO2020155545A1 (en) * | 2019-01-28 | 2020-08-06 | 山东华芯半导体有限公司 | Programmable gpio device and time sequence implementation method based on the device |
| CN111880941A (en) * | 2020-07-31 | 2020-11-03 | 深圳市新国都支付技术有限公司 | Method and device for multiplexing GPIO, computer equipment and storage medium |
| CN114048158A (en) * | 2021-10-12 | 2022-02-15 | 北京控制与电子技术研究所 | General purpose GPIO port controller based on user command |
| CN114487793A (en) * | 2022-04-13 | 2022-05-13 | 武汉杰开科技有限公司 | Chip functionality test unit, test method, chip and automatic test system |
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2008
- 2008-09-12 CN CN2008102222557A patent/CN101377764B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101901202A (en) * | 2010-07-29 | 2010-12-01 | 东莞市泰斗微电子科技有限公司 | Circuit and method for cross clock domain accessing of AHB bus equipment to APB bus equipment |
| CN101901202B (en) * | 2010-07-29 | 2012-08-15 | 东莞市泰斗微电子科技有限公司 | Circuit for cross clock domain accessing of AHB bus equipment to APB bus equipment |
| CN102880574A (en) * | 2011-07-11 | 2013-01-16 | 航天信息股份有限公司 | Method for simulating low speed parallel interface by using GPIO (general purpose input output) |
| CN102880574B (en) * | 2011-07-11 | 2015-01-07 | 航天信息股份有限公司 | Method for simulating low speed parallel interface by using GPIO (general purpose input output) |
| CN104516853B (en) * | 2014-12-22 | 2019-05-31 | 厦门雅迅网络股份有限公司 | The system and method for improving GPIO I/O efficiency under linux |
| CN104516853A (en) * | 2014-12-22 | 2015-04-15 | 厦门雅迅网络股份有限公司 | System and method for improving GPIO (general purpose input and output) efficiency under linux |
| CN107992439A (en) * | 2017-10-13 | 2018-05-04 | 武汉高德智感科技有限公司 | A kind of expansible data interactive method and system |
| WO2019136983A1 (en) * | 2018-01-12 | 2019-07-18 | 江苏华存电子科技有限公司 | Low-delay instruction scheduler |
| WO2020155545A1 (en) * | 2019-01-28 | 2020-08-06 | 山东华芯半导体有限公司 | Programmable gpio device and time sequence implementation method based on the device |
| CN110895518A (en) * | 2019-07-01 | 2020-03-20 | 研祥智能科技股份有限公司 | GPIO (general purpose input/output) interface configuration method and system |
| CN111880941A (en) * | 2020-07-31 | 2020-11-03 | 深圳市新国都支付技术有限公司 | Method and device for multiplexing GPIO, computer equipment and storage medium |
| CN114048158A (en) * | 2021-10-12 | 2022-02-15 | 北京控制与电子技术研究所 | General purpose GPIO port controller based on user command |
| CN114487793A (en) * | 2022-04-13 | 2022-05-13 | 武汉杰开科技有限公司 | Chip functionality test unit, test method, chip and automatic test system |
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| CN101377764B (en) | 2011-10-12 |
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