WO2020155545A1

WO2020155545A1 - Programmable gpio device and time sequence implementation method based on the device

Info

Publication number: WO2020155545A1
Application number: PCT/CN2019/093652
Authority: WO
Inventors: 王运哲; 刘大铕; 刘奇浩; 刘尚; 朱苏雁; 孙中琳
Original assignee: 山东华芯半导体有限公司
Priority date: 2019-01-28
Filing date: 2019-06-28
Publication date: 2020-08-06
Also published as: CN109857485B; CN109857485A

Abstract

Provided are a programmable gpio device and a time sequence implementation method based on the device, the programmable gpio device comprises a CMD module for storing instructions from software configuration, a read/write FIFO for storing data read from peripheral equipment or data written to the peripheral equipment on a DATA port, a pipeline control module and an interface connected with the peripheral equipment. The solution can be programmed by a user, carries out pin configuration through the CPU, which has the advantages of being rapid and flexible, intervention of the CPU is not needed in the operation process, and communication with the kernel is carried out only through some CPU marks and terminals.

Description

Programmable GPIO device and time sequence realization method based on the device

Technical field

The invention relates to a programmable gpio device and a time sequence realization method based on the device, and belongs to the technical field of memory.

Background technique

Each GPIO port can be configured as input or output by software, that is, the corresponding pin is controlled through the configuration register to realize interaction with peripherals. Because of the overhead of the CPU executing software code and the delay of data transfer within the chip including the system bus, the software cannot accurately control the transition time of the level on the GPIO pin and the timing relationship between the pins, so GPIO does not support high-speed interface protocols and then Can not realize data interaction with complex peripherals.

With the improvement of technology, high-speed interface protocols have become the mainstream. The present invention aims to extract the common characteristics of the timing of various interface protocols, and use hardware to implement programming of gpio according to timing waveforms to support various interface protocols. This device classifies interface signals into clocks, control signals, and data signals; classifies the timing status as idle, control output, control input, data read in, data write out, condition trigger waiting, and control and data concurrent status, etc.; This design has a set of instructions and uses a three-stage pipeline to ensure the accuracy of the interface timing. Through software programming, the CPU configuration registers, built-in command SRAM, and data FIFO realize different interface applications.

Summary of the invention

The technical problem to be solved by the present invention is to provide a programmable gpio device and a time sequence implementation method based on the device, which can be programmed by the user and configured by the CPU. It has the characteristics of fast and flexible and does not require CPU intervention during operation. Only communicate with the kernel through some CPU signs and terminals.

In order to solve the technical problem, the technical solution adopted by the present invention is: a programmable gpio device, including a CMD module, for storing instructions from software configuration;

Mode register and default level register. The mode register determines the input and output settings of each port of CTL. As the input CTL port, if its input level is inconsistent with the level of the corresponding bit in the default level register, all signals on the interface remain unchanged Until the two are consistent, the subsequent sequence evolution can be continued according to the command entry in the CMD and SRAM;

Read/write FIFO, used to store data read from peripherals or data written to peripherals on DATA port;

Pipeline control module. The pipeline control module includes an instruction fetching state machine, a decoding state machine, and an execution state machine. The three state machines are responsible for extracting instructions from the command SRAM, parsing the extracted instructions, and executing the parsed instructions;

The interface with peripherals includes three types: PCLK, CTL, and DATA. PCLK is output from the controller to the peripherals. Both CTL and DATA are bidirectional ports.

Further, the length of each command entry stored in the CMD module is 32 bits, where bit[31:29] is the data control symbol, bit31 is the data valid control bit, when it is 1, it means that the current DATA interface is valid, and when it is 0, it means only The CTL interface is valid; bit30 is the read and write control bit, which indicates the read and write operations of the DATA interface. When it is 1, the DATA interface is output, and when it is 0, DATA is input. When bit31 is 1, this bit is valid; bit29 indicates whether the DATA cycle is multi-shot , When bit31 is valid and bit29 is 0, it means that only one-beat data is read and written in the current command. When bit29 is 1, it means that multi-beat data transmission is performed, and the number of data transmissions and the actual command cycle number Consistent; bit[20:16] represents the command direction and the number of pclk cycles when the command is output. When it is 0, it means that the value on the CTL line configured as input needs to wait for it to become the corresponding bit in the default level register Execute the next command after the values are the same. At this time, if bit31 is valid, only one-shot data reading and writing operations are performed when bit29 is 0, and multi-shot operations are performed when bit29 is 1, that is, each pclk cycle of the waiting process is performed Read and write operations until the input becomes the default value;

bit[12:0] indicates the output level on the CTL interface or whether to detect the level of the input control line. It is matched with bit[20:16]. When cmd_count=0, it means that only the input control line is looked at and only this bit Control lines that are inconsistent with the default level.

Further, on the interface with peripherals, the level signal of the CTL port in each PCLK cycle is determined by the currently executed CMD SRAM entry and the mode and level register. The level signal of the DATA port is determined by the current executed CMD SRAM entries and mode and level registers, as well as writing data on the FIFO or the level of connected peripherals are jointly determined. The input and output settings of each CTL port are determined by the mode register. As the output CTL port, its output level is determined by The corresponding bit in [12:0] of the corresponding command entry in CMD SRAM is determined; as the input CTL port, its input level needs to be consistent with the level of the corresponding bit in the default level register to indicate that the command is completed, DATA port Whether it is valid and the input and output settings when it is valid are determined by the [31:30] bits of the CMD SRAM entry. When the DATA port is used as an output, data is ejected from the WR FIFO, and when it is used as an input, the data is pushed into the RDFIFO.

Further, the state of the fetching state machine includes idle, first fetching, second fetching, normal fetching, trigger waiting, execution feedback, and the state of the decoding and executing state machine includes idle, control output, control input, Data read in, data write out, condition trigger waiting, control output and data read and write, control input and data write out, the states of the three state machines can jump in pairs with each other.

The next state of the decoding state machine depends on the analysis of the instructions output by the current state of the instruction fetching state machine. The next state of the execution state machine depends on the current state of the decoding state machine. The instruction fetching state machine is controlled by the mode and the default level register. The information and the execution feedback of the instructions determine whether to perform a state jump, so that the interface timing of the execution phase is completely consistent with the description in the instruction queue.

Further, the width of the control signal CTL is 13 bits, and the width of the data signal DATA is configurable, and its width must be consistent with the bit width of the internal FIFO.

The invention also discloses a time sequence realization method based on the above programmable gpio device, which includes the following steps:

S01), CPU configuration mode register and default level register, and code CMD SRAM;

S02), the instruction fetching state machine jumps from the idle state to the state of fetching the first instruction;

S03). After the first instruction is fetched, the instruction fetching state machine jumps to the state of fetching the second instruction, and at the same time, the decoding state machine jumps to the decoding timing state according to the decoding information;

S04). After the second instruction is fetched, the instruction fetching state machine jumps to the normal instruction fetching state. At the same time, the decoding state machine jumps to the second decoding timing state according to the information of the decoded second instruction, and the execution state machine Jump from the idle state to the previous decoding state;

S05). The decoding information obtained from the decoding state determines the PCLK cycle required to execute the previous decoding state that the state machine jumps in step S03, and then the instruction fetching state machine enters the normal instruction fetching state from the waiting state, and the decoding state machine is based on the decoded state. The information of the third instruction jumps to the third decoding timing state, and the execution state machine jumps from the decoding state jumped in step S03 to the previous decoding state;

S06), the decoding information obtained from the decoding state determines the PCLK cycle required to execute the previous decoding state that the state machine jumped in step S04, and then the instruction fetching state machine enters the normal instruction fetching state from the waiting state, and the decoding state machine is based on the decoded The information of the fourth instruction jumps to the fourth decoding timing state, and the execution state machine jumps from the decoding state jumped in step S04 to the previous decoding state;

S07). Because the previous decoding state of the execution state machine jumped in step S06 needs to wait for a certain input signal on the CTL interface to be consistent with the corresponding bit of the mode register, the specific waiting time depends on the peripheral. After the two are consistent, fetch the instruction The state machine enters the idle state, the decoding state machine jumps to the fifth decoding timing state according to the information of the decoded fifth instruction, and the execution state machine jumps from the decoding state jumped in step S06 to the previous decoding state;

S08), the decoding information obtained from the decoding state determines the PCLK cycle required for the previous decoding state that the execution state machine jumps in step S07, after which the decoding state machine enters the idle state, and the execution state machine jumps from the decoding state jumped in step S07 Go to the previous decoding state;

S09) The decoding information obtained from the decoding state determines the PCLK cycle required for the previous decoding state to which the execution state machine jumps in step S08, and then the execution state machine enters the idle state.

Further, in step S03, the decoding timing state that the decoding state machine jumps to is the data writing state, and in step S04, the second decoding timing state that the decoding state machine jumps to is the data reading state, and the execution state machine jumps The previous decoding state to be transferred is the data writing state. In step S05, the third decoding timing state of the decoding state machine jump is the waiting state, and the previous decoding state of the execution state machine jump is the data reading state. In S06, the fourth decoding timing state where the decoding state machine jumps is the control output state, the last decoding state that executes the state machine jump is the waiting state, and in step S07, the fifth decoding timing state where the decoding state machine jumps It is the control input state, the last decoding state that executes the state machine jump is the control output state, and in step S08, the last decode state that executes the state machine jump is the control input state.

The beneficial effects of the present invention: the traditional GPIO can only set the pin as input or output, and set the pin to a fixed level value or a high resistance state, and cannot realize complex timing control of the pin. This design is actually a multi-function peripheral storage interface controller, which can be programmed by the user, and carries out large-scale pin configuration through the CPU, which is fast and flexible. And no CPU intervention is needed during operation, and only some CPU signs and interrupts are used to communicate with the kernel. The flexible interface it enables can be used as a master device in an industrial standard or dedicated interface, and both parallel and serial interfaces can be implemented.

Description of the drawings

Figure 1 is a schematic block diagram of a programmable gpio device;

Figure 2 is a schematic diagram of the pipeline when three state machines are running;

Figure 3 is a schematic diagram of a mode control register;

Figure 4 is a schematic diagram of the default level register;

Figure 5 is a schematic diagram of the CPU configuration settings for CMD_SRAM.

detailed description

The present invention will be further described below in conjunction with the drawings and specific embodiments.

Example 1

This embodiment discloses a programmable gpio device, as shown in FIG. 1, including:

CMD module, used to store instructions from software configuration;

The mode register (represented as Mode Register in Figure 1) and the default level register (represented as Level Register in Figure 1) have a bit width of 13 bits. As shown in Figures 3 and 4, the mode register determines each port of the CTL Input and output settings, as the input CTL port, when the input level is inconsistent with the level of the corresponding bit in the default level register, all the signals on the interface remain unchanged until the two are consistent, and the subsequent commands in CMD SRAM can be continued. Timing evolution

The pipeline control module, as shown in Figure 2, the pipeline control module includes a fetch state machine (Fetch), a decoding state machine (Decode), and an execution state machine (Execute). The three state machines are respectively responsible for extracting instructions from the command SRAM and parsing The extracted instructions and the parsed instructions;

The interface with peripherals includes three types: PCLK, CTL, and DATA. PCLK is output from the controller to the peripherals. Both CTL and DATA are bidirectional ports. The width of the control signal CTL is 13 bits, and the width of the data signal DATA is configurable, and its width must be consistent with the bit width of the internal FIFO.

As shown in Figure 5, the length of each command entry stored by the CMD module is 32 bits, of which bit[31:29] is the data control symbol, bit31 (DATA_VALID) is the data valid control bit, when it is 1, it means that the current DATA interface is valid , When it is 0, it means that only the CTL interface is valid; bit30 (RW) is the read and write control bit, which means the read and write operation of the DATA interface. When it is 1, the DATA interface is output, and when it is 0, DATA is input. When bit31 is 1, this bit is only Valid; bit29 (DATA_LENGTH) indicates whether the DATA cycle is multi-beat. When DATA_VALID is valid and bit29 is 0, it means that only one-beat data is read and written in the current command. When DATA_LENGTH is 1, it means multi-beat data transmission. And the number of data transmission is the same as the cycle number of the actual command, which is the value in [20:16].

bit[20:16](Command cycle counter) represents the command direction and the number of pclk cycles when the command is output. When it is 0, it means that the value on the CTL line configured as input needs to wait for the value to be changed to the default level register After the values of the corresponding bits are consistent, execute the next command. At this time, if DATA_VALID is valid, only one beat of data read and write operations will be performed when DATA_LENGTH is 0 (this operation is performed at the beat when the control line becomes the default value). At 1 o'clock, multi-shot operation is performed, that is, each pclk cycle of the waiting process performs read and write operations until the input becomes the default value.

bit[12:0](Command) indicates the output level on the CTL interface or whether to detect the level of the input control line. It is matched with bit[20:16]. When cmd_count=0, it means that only the input control line is looked at. Look at the control line that is inconsistent with the default level on this bit.

In this embodiment, on the interface with peripherals, the level signal of the CTL port in each PCLK cycle is determined by the currently executed CMD SRAM entry and the mode and level register, and the level signal of the DATA port is determined by the current execution The received CMD SRAM entry, the mode and level register, and the data written on the FIFO or the level of the connected peripheral are jointly determined. The input and output settings of each CTL port are determined by the mode register. As the output CTL port, its output power The level is determined by the corresponding bit in [12:0] of the corresponding command entry in CMD SRAM; as the input CTL port, its input level needs to be consistent with the level of the corresponding bit in the default level register to indicate that the command is completed. Whether the DATA port is valid and the input and output settings when it is valid are determined by the [31:30] bits of the CMD SRAM entry. When the DATA port is used as an output, data is ejected from the WRFIFO, and when it is used as an input, the data is pushed into the RDFIFO.

In this embodiment, the states of the instruction fetching state machine include idle, first fetching, second fetching, normal fetching, trigger waiting, and execution feedback. The states of the decoding state machine and the execution state machine include idle, control output , Control input, data read in, data write out, condition trigger waiting, control output and data read and write, control input and data write out, the states of the three state machines can jump two by two. The next state of the decoding state machine depends on the analysis of the instructions output by the current state of the instruction fetching state machine, and the next state of the execution state machine depends on the current state of the decoding state machine. The instruction fetching state machine decides whether to perform a state jump according to the mode control and default level register information and the execution feedback of the instruction, so that the interface timing of the execution stage is exactly the same as that described in the instruction queue. Since instruction fetching and decoding essentially only require one clock cycle, the advance speed of the pipeline depends on the execution time of each command. The execution time of a command depends on the content of the command, such as the number of cycles of writing data or the waiting time for waiting for input signal changes.

Example analysis in Figure 5: The mode control register indicates that CTL[12] is the output mode, CTL[11] is the input mode, CTL[1] is the input mode, and CTL[0] is the output mode. The default level register indicates that the input CTL[11] is high by default, and CTL[1] is low. In the input mode, every PCLK cycle, it is judged whether CTL[11] is 1 and at the same time CTL[1] is 0. If they are not consistent, wait until the input changes to be consistent before proceeding to the next command.

Example 2

This embodiment discloses a data reading and writing method based on the programmable gpio device of claim 1, which includes the following steps:

S01), CPU configuration mode register and default level register, and code CMD SRAM (assuming 5 instructions are configured);

S03). After the first instruction is fetched, the instruction fetching state machine jumps to the state of fetching the second instruction. At the same time, the decoding state machine jumps to the first decoding timing state according to the decoding information. In this embodiment, the The state is the data write state;

S04). After the second instruction is fetched, the instruction fetching state machine jumps to the normal instruction fetching state. At the same time, the decoding state machine jumps to the second decoding timing state according to the information of the decoded second instruction. This embodiment In the second decoding state, the execution state machine jumps from the idle state to the previous decoding state. In this embodiment, this state is the data writing state;

S05). The decoding information obtained from the decoding state determines the PCLK cycle required for the data writing state that the execution state machine jumps in step S03. In this embodiment, 10 pclk cycles are required, and then the instruction fetching state machine enters the normal state from the waiting state In the instruction fetching state, the decoding state machine jumps to the third decoding timing state (waiting state) according to the information of the decoded third instruction, and the execution state machine jumps from the data writing state to the previous decoding state (data reading in status);

S06). The decoding information obtained from the decoding state determines that it takes 8 pclk cycles to execute the data read-in state of the state machine, and then the instruction fetching state machine enters the normal instruction fetching state from the waiting state, and the decoding state machine is based on the fourth instruction decoded The information jumps to the fourth decoding timing state (control output state), and the execution state machine jumps from the data reading state to the previous decoding state (waiting state);

S07), because the execution state machine wait state needs to wait for a certain input signal on the CTL interface to be consistent with the corresponding bit of the mode register. The specific waiting time depends on the peripheral. After the two are consistent, the instruction fetching state machine enters the idle state and the decoding state The machine jumps to the fifth decoding timing state (control input state) according to the information of the decoded fifth instruction, and the execution state machine jumps from the waiting state to the previous decoding state to control the output state;

S08), the decoding information obtained from the decoding state determines that the control output state of the execution state machine requires 16 pclk cycles, after which the decoding state machine enters the idle state, and the execution state machine jumps from the data writing state to the previous decoding state control input state ；

S09) It is determined from the decoding information obtained from the decoding state that the control input state of the execution state machine requires 4 pclk cycles, and then the execution state machine enters the idle state.

Take the data in CMD SRAM in Figure 5 as an example to analyze the interface timing as follows:

The first instruction, one pclk clock cycle, CTL[12] output is 0, CTL[0] output is 1

The second instruction, three pclk clock cycles, CTL[12] output is 1, CTL[0] output is 0

The third instruction maintains the current state until it is detected that the input CTL[11]=1 and CTL[1]=0 are established at the same time; DATA writes a group of data (from WRFIFO) in this pclk cycle.

The fourth instruction, ten pclk clock cycles, CTL[12] output is 1, CTL[0] output is 0, and at the same time ten groups of data are read in sequence on the DATA interface (into the RDFIFO in sequence).

The fifth instruction maintains the current state until it detects that the input CTL[11] becomes 1; in this pclk cycle, a group of data is read on the DATA port (press into the RD FIFO).

Traditional GPIO can only set the pin as input or output, and set the pin to a fixed level value or high impedance state, which cannot achieve complex timing control of the pin. This device is actually a multi-function peripheral storage interface controller, which can be programmed by the user, and carries out large-scale pin configuration through the CPU, which is fast and flexible. And no CPU intervention is needed during operation, and only some CPU signs and interrupts are used to communicate with the kernel. The flexible interface it enables can be used as a master device in an industrial standard or dedicated interface, and both parallel and serial interfaces can be implemented.

Note: Ports, pins, and pins in this text refer to the same meaning. Command and instruction refer to the same meaning. What has been described above are only the basic principles and preferred embodiments of the present invention. Improvements and replacements made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

A programmable gpio device, which is characterized in that it comprises

CMD module, used to store instructions from software configuration;

Mode register and default level register. The mode register determines the input and output settings of each port of CTL. As the input CTL port, if its input level is inconsistent with the level of the corresponding bit in the default level register, all signals on the interface remain unchanged Until the two are consistent, the subsequent sequence evolution can be continued according to the command entry in the CMD and SRAM;

Read/write FIFO, used to store data read from peripherals or data written to peripherals on DATA port;

Pipeline control module. The pipeline control module includes an instruction fetching state machine, a decoding state machine, and an execution state machine. The three state machines are responsible for extracting instructions from the command SRAM, parsing the extracted instructions, and executing the parsed instructions;

The interface with peripherals includes three types: PCLK, CTL, and DATA. PCLK is a one-way port output by the controller to the peripheral. CTL and DATA are both two-way ports.
The programmable gpio device according to claim 1, wherein the length of each command entry stored in the CMD module is 32 bits, where bit[31:29] is a data control symbol, and bit31 is a data valid control bit, which is 1. When is the current DATA interface is valid, when it is 0, it means that only the CTL interface is valid; bit30 is the read and write control bit, which means the read and write operation of the DATA interface, when it is 1, the DATA interface is output, when it is 0, DATA is input, when bit31 is This bit is valid when 1; bit29 indicates whether the data cycle is multi-beat. When bit31 is valid and bit29 is 0, it means that only one-beat data is read and written in the current command. When bit29 is 1, it means multi-beat data. Transmission, and the number of data transmissions is the same as the number of cycles of the actual command; bit[20:16] indicates the command direction and the number of pclk cycles when the command is output. When it is 0, it indicates the CTL line configured as input You need to wait for the value to be consistent with the value of the corresponding bit in the default level register before executing the next command. At this time, if bit31 is valid, only one-shot data read and write operation is performed when bit29 is 0, and when it is 1, perform Multi-shot operation, that is, each pclk cycle of the waiting process performs read and write operations until the input becomes the default value;

bit[12:0] indicates the output level on the CTL interface or whether to detect the level of the input control line. It is matched with bit[20:16]. When cmd_count=0, it means that only the input control line is looked at and only this bit Control lines that are inconsistent with the default level.
The programmable gpio device according to claim 2, characterized in that: on the interface with the peripheral, the level signal of the CTL port in each PCLK cycle is shared by the currently executed CMD SRAM entry and the mode and level register Determined, the level signal of the DATA port is determined by the currently executed CMD SRAM entry, the mode and level register, and the data written on the FIFO or the level of the connected peripheral. The input and output settings of each CTL port are determined by the mode register It is decided that the output level of the CTL port as the output is determined by the corresponding bit in [12:0] of the corresponding command entry in CMD SRAM; the input level of the CTL port as the input needs to be the same as the corresponding bit in the default level register The command is completed only when the levels are the same. Whether the DATA port is valid and the input and output settings when it is valid are determined by the [31:30] bit of the CMD SRAM entry. When the DATA port is used as an output, the data will be popped from the WRFIFO. The data is pressed into the RD FIFO.
The programmable gpio device according to claim 1, wherein the state of the fetching state machine includes idle, first fetching, second fetching, normal fetching, trigger waiting, execution feedback, and decoding state machine The state of the execution state machine includes idle, control output, control input, data read in, data write out, condition trigger waiting, control output and data read and write, control input and data read and write, one of the internal states of the three state machines You can jump in pairs.
The programmable gpio device according to claim 4, wherein the next state of the decoding state machine depends on the analysis of the instruction output from the current state of the instruction fetching state machine, and the next state of the execution state machine depends on the decoding state machine The current state of the instruction fetching state machine determines whether to perform a state jump according to the mode control and the default level register information and the execution feedback of the instruction, so that the interface timing of the execution stage is completely consistent with the description in the instruction queue.
The programmable gpio device according to claim 1, wherein the width of the control signal CTL is 13 bits, and the width of the data signal DATA is configurable, and its width must be consistent with the bit width of the internal FIFO.
A time sequence implementation method based on the programmable gpio device of claim 3, characterized in that it comprises the following steps: S01), CPU configuration mode register and default level register, and coding CMD SRAM;

S02), the instruction fetching state machine jumps from the idle state to the state of fetching the first instruction;

S03). After the first instruction is fetched, the instruction fetching state machine jumps to the state of fetching the second instruction, and at the same time, the decoding state machine jumps to the decoding timing state according to the decoding information;

S04). After the second instruction is fetched, the instruction fetching state machine jumps to the normal instruction fetching state. At the same time, the decoding state machine jumps to the second decoding timing state according to the information of the decoded second instruction, and the execution state machine Jump from the idle state to the previous decoding state;

S05), the decoding information obtained from the decoding state determines the PCLK cycle required by the previous decoding state that the state state machine jumps in step S03, and then the instruction fetching state machine enters the normal instruction fetching state from the waiting state, and the decoding state machine is based on the decoded state. The information of the third instruction jumps to the third decoding timing state, and the execution state machine jumps from the decoding state jumped in step S03 to the previous decoding state;

S06), the decoding information obtained from the decoding state determines the PCLK cycle required to execute the previous decoding state that the state machine jumped in step S04, and then the instruction fetching state machine enters the normal instruction fetching state from the waiting state, and the decoding state machine is based on the decoded The information of the fourth instruction jumps to the fourth decoding timing state, and the execution state machine jumps from the decoding state jumped in step S04 to the previous decoding state;

S07). Because the previous decoding state of the execution state machine jumped in step S06 needs to wait for a certain input signal on the CTL interface to be consistent with the corresponding bit of the mode register, the specific waiting time depends on the peripheral. After the two are consistent, fetch the instruction The state machine enters the idle state, the decoding state machine jumps to the fifth decoding timing state according to the information of the decoded fifth instruction, and the execution state machine jumps from the decoding state jumped in step S06 to the previous decoding state;

S08), the decoding information obtained from the decoding state determines the PCLK cycle required for the previous decoding state that the execution state machine jumps in step S07, after which the decoding state machine enters the idle state, and the execution state machine jumps from the decoding state jumped in step S07 Go to the previous decoding state;

S09) The decoding information obtained from the decoding state determines the PCLK cycle required by the previous decoding state that the execution state machine jumps to in step S08, and then the execution state machine enters the idle state.
The time sequence implementation method of a programmable gpio device according to claim 7, characterized in that: in step S03, the decoding time sequence state to which the decoding state machine jumps is the data write state, and in step S04, the decoding state machine jumps to The second decoding timing state of the decoding state machine is the data reading state, and the last decoding state that the execution state machine jumps to is the data writing state. In step S05, the third decoding timing state of the decoding state machine jumping is the waiting state. The last decoding state of the execution state machine jump is the data read state. In step S06, the fourth decoding timing state of the decoding state machine jump is the control output state, and the last decoding state of the execution state machine jump is the waiting state. In step S07, the fifth decoding timing state of the decoding state machine jump is the control input state, and the previous decoding state that executed the state machine jump is the control output state. In step S08, the previous decoding state of the state machine jump is executed. The state is the control input state.