CN201590076U - An interface expansion circuit and a mobile terminal with the circuit - Google Patents

Abstract

The utility model discloses an interface extending circuit and mobile terminal with the circuit, comprising a main processor and an interface extending module with GPIO ports, wherein the interface extending module is connected with a parallel interface of the main processor by a parallel bus to receive the interface configuration command and data sent from the main processor and connected with a perimeter circuit by the GPIO ports of the interface extending module. The required interface configuration command and data transmission communication are realized between the main processor and the interface configuration command by the parallel communication way and the reading-writing speed is quick and the interface extending circuit and mobile terminal can be flexibly extended according to the requirement of the perimeter circuit for the number of the GPIC interface. When the interface extending circuit and mobile terminal are used in the mobile terminal system such the telephones, not only the required enough GPIC interface resources are provided for continuously increased perimeter circuits, but also the interface extending circuit and mobile terminal respond the operation in good time, such as quick press-key switch performed by the user, thereby improving the work performance of the mobile terminal.

Description

An interface expansion circuit and a mobile terminal with the circuit

technical field

The utility model belongs to the technical field of interface expansion, in particular relates to a circuit structure capable of expanding the GPIO interface of a chip and a mobile terminal designed by adopting the interface expansion circuit.

Background technique

With the increasing diversification of mobile phone functions, when designing mobile phone system circuits, more and more functional circuits need to be connected to the periphery of the main processor of the mobile phone, and most of the peripheral circuits often need to be connected to the GPIO interface of the main processor to realize Cooperative work with the main processor. For example, a mobile phone with 16 keys needs to occupy 8 GPIO interfaces of the main processor for its keyboard scanning circuit. However, the GPIO interfaces provided by the general mobile phone main processor are often not enough, especially in the design of smart phones. In this way, it is necessary to expand the GPIO interface or the keyboard scanning circuit to meet the connection needs of an increasing number of peripheral circuits. At present, there are two ways to realize GPIO interface expansion: one is to use a dedicated expansion chip, and the other is to use programmable logic devices such as CPLD to achieve.

However, the dedicated GPIO interface expansion chips and programmable logic devices currently on the market are basically based on the I ² C bus interface, that is, the connection and communication between the main processor and the interface expansion chip is realized through the I ² C bus. Due to the limitation of the speed of the I ² C interface, when the mobile phone user presses the key quickly or plays a game, there will be a problem of slow key response. Moreover, the use of dedicated expansion chips is inflexible, and each design needs to select different expansion chips according to the actual functions to be completed by the system, which causes discontinuity in circuit design.

Utility model content

In order to solve the problem of slow response speed of the existing I ² C bus-based interface expansion circuit, the utility model provides an interface expansion circuit based on parallel port communication to improve the response speed of the system circuit.

In order to solve the above-mentioned technical problems, the utility model adopts the following technical solutions to achieve:

An interface expansion circuit, comprising a main processor and an interface expansion module with multiple GPIO ports, the interface expansion module is connected to the parallel interface of the main processor through a parallel bus, receives interface configuration commands and data sent by the main processor, and Connect the peripheral circuit through the GPIO port of the interface expansion module.

Further, the interface expansion module includes a main processor interface unit, a GPIO functional logic unit, a GPIO configuration register, and a GPIO level status register; the main processor interface unit is connected to the parallel interface of the main processor through a parallel bus , write data to the corresponding GPIO configuration register or GPIO level status register according to the received interface configuration command and data; the GPIO function logic unit configures the corresponding GPIO port according to the data in the GPIO configuration register and the GPIO level status register state.

Still further, the master processor interface unit uses a state machine in a level detection mode to create a parallel slave interface.

Preferably, the main processor preferably adopts its I8080 interface as a parallel interface for connecting and communicating with the interface expansion module.

Still further, the keyboard scanning logic unit and the keyboard scanning code register are included in the interface expansion module, the keyboard scanning logic unit is connected to the GPIO port of the interface expansion module for connecting the matrix keyboard circuit, and when a key is detected When pressing down, the key scan code is transmitted to the keyboard scan code register for storage, and an interrupt signal is generated and transmitted to the interrupt interface of the main processor.

Wherein, the keyboard scanning logic unit is connected to the main processor interface unit, transmits the interrupt signal generated to the main processor interface unit, and is connected to the interrupt interface of the main processor through the main processor interface unit.

Furthermore, the keyboard scan logic unit includes a row scan counter module, a debounce clock frequency division module, a debounce logic module, and a keyboard matrix scan module; the debounce clock frequency divider module receives the system clock and performs division After frequency transmission to the de-jitter logic module to generate a de-jitter synchronous clock, and then output to the keyboard matrix scanning module; the row scan counter module receives the system clock, generates a count clock and transmits it to the keyboard matrix scanning module; The keyboard matrix scanning module is connected to the GPIO port on the interface expansion module for connecting to the matrix keyboard circuit, detects the key state, and when it is detected that a key is pressed, generates a key scanning code and saves it to the keyboard scanning code register, and generate an interrupt signal output to the main processor.

Preferably, the de-jitter logic module is composed of a shift register composed of 3 groups of synchronous flip-flops.

Optionally, the interface expansion module can be implemented by using programmable logic devices such as CPLD.

Based on the above-mentioned interface expansion circuit structure, the utility model also provides a mobile terminal adopting the design of the interface expansion circuit, through connecting the main processor and the interface expansion module with a parallel bus to realize interface configuration commands and data Parallel transmission, thus improving the response speed of the system circuit.

Compared with the prior art, the advantages and positive effects of the utility model are: the interface expansion circuit of the utility model adopts a parallel communication mode to realize the transmission and communication of the required interface configuration commands and data between the main processor and the interface expansion module, read The writing speed is fast, and it can be flexibly expanded according to the requirements of the peripheral circuit on the number of GPIO interfaces, thereby improving the versatility of the system circuit design. Applying it to mobile terminal systems such as mobile phones can not only provide sufficient GPIO interface resources required for connection to the increasing number of peripheral circuits, but also respond in a timely manner to operations such as fast switching keys performed by users, thereby improving performance of the mobile terminal.

After reading the detailed description of the embodiments of the utility model in conjunction with the accompanying drawings, other features and advantages of the utility model will become clearer.

Description of drawings

Fig. 1 is the circuit block diagram of a kind of embodiment of the interface expansion circuit proposed by the utility model;

FIG. 2 is a functional block diagram of an embodiment of the internal circuit of the keyboard scanning logic unit in FIG. 1 .

Detailed ways

Specific embodiments of the present utility model are described in detail below in conjunction with the accompanying drawings.

The interface expansion circuit of the utility model abandons the traditional circuit design mode based on the I ² C bus, uses a parallel bus to connect and communicate between the main processor and the interface expansion module, and uses the characteristics of fast data reading and writing speed of the parallel interface to speed up the main processor The interface with the interface expansion module configures the transmission speed of commands and data, so as to meet the flexible expansion of the system GPIO port resources, and realize the rapid response of the system circuit to the fast operation.

The specific building structure and working process of the interface expansion circuit will be described in detail below through a specific embodiment.

Embodiment one, referring to shown in Fig. 1, in the interface extension module of the present embodiment, comprise main processor interface unit, GPIO function logic unit, GPIO configuration register, GPIO level state register and can provide the pin of multi-channel GPIO interface Multiplexing unit and other main components.

The main processor interface unit is used as the communication interface between the main processor of the system and the interface expansion module. Select signal CS, address signal RS, read enable signal RE, write enable signal WE and reset signal Reset, and realize bidirectional data transmission with the main processor through the 16-bit data bus Data_bus in the parallel bus. In this embodiment, the main processor interface unit can use the state machine of the detection level mode to realize the design of the I8080 slave interface, according to the level state of the configuration command received, the configuration data sent by the main processor Write the corresponding register, for example, write the address information corresponding to the GPIO interface to be configured into the GPIO configuration register; write the specific state (such as input/output/interrupt, etc.) to be configured by the interface into the GPIO level status register, etc. wait.

Implementing the I8080 slave interface with a state machine is not only safe and reliable, but also very simple to implement. Of course, in addition to the state machine, the main processor interface unit can also be designed in various other interface implementation forms according to the specific type of the parallel interface provided by the main processor. This embodiment is not limited to the above examples.

The GPIO function logic unit is used to realize the specific configuration function of the GPIO interface, connects the GPIO configuration register, the GPIO level status register and the GPIO pin multiplexing unit, according to the GPIO configuration register and the GPIO level status register. The value is used to configure the state of the required GPIO interface, such as configuring a part of the GPIO interface as an input state or an output state, configuring another part of the interface as an interrupt state, and so on.

In order to enable the interface expansion circuit of this embodiment to realize the matrix keyboard scanning function, this embodiment also designs a keyboard scanning logic unit in the interface expansion module to connect the keyboard scanning code register, the main processor interface unit and the GPIO pin complex Use the unit, as shown in Figure 1. Wherein, the keyboard scanning logic unit scans the level state of the GPIO interface used to connect the matrix keyboard circuit in the GPIO pin multiplexing unit, so as to detect the trigger state of the keyboard. When a key is pressed, the key scan code corresponding to the key is written into the keyboard scan code register, and the interrupt signal Host_irq is transmitted to the interrupt interface of the system main processor through the main processor interface unit to notify the main processor Read the key scan code, and then respond to the operations performed by the user in a timely manner.

The keyboard scan logic unit of this embodiment can be formed by using a row scan counter module, a debounce clock frequency division module, a debounce logic module, and a keyboard matrix scan module, as shown in FIG. 2 . First, the system clock CLK is used to provide the count clock to the row scan counter module, and the generated count clock is provided to the keyboard matrix scan module through the row scan counter module; After the frequency processing, it is output to the de-jitter logic module to generate a de-jitter synchronous clock, which is transmitted to the keyboard matrix scanning module. Among them, the de-jitter logic module can be designed and implemented by a shift register composed of three groups of synchronous flip-flops. The row input level state of the matrix keyboard can be determined by the keyboard matrix scanning module after "bit ORing" the three output phases of the shift register. The column input of the keyboard matrix scanning module is obtained by periodically scanning the matrix keyboard under the action of the debounced synchronous clock. The final key scan code is determined by the row input level state and column scan output state of the matrix keyboard. When the keyboard matrix scanning module determines that a key is pressed, the generated key scan code is saved in the keyboard scan code register, and an interrupt signal Host_irq is generated to notify the main processor to access the keyboard scan code register to read the key scan code therein .

The GPIO pin multiplexing unit of this embodiment can be designed and implemented by a group of logic switches. According to the value of the GPIO configuration register, the corresponding logic switch is turned on to realize the keyboard scanning or GPIO interface function.

The interface expansion module of this embodiment can be implemented by using discrete functional module circuit connections, and can also be implemented by using low-power programmable logic devices, such as CPLD devices, etc., using hardware description language programming to simplify system circuit design. There is no specific limitation on this.

The interface expansion circuit of the utility model adopts the parallel interface of the main processor to expand the GPIO interface and the keyboard scanning function, and the data reading and writing speed is fast, which is suitable for application in the system circuit design of mobile terminals such as mobile phones and palmtop computers, so that users can press keys quickly , the system can respond in a timely manner.

Of course, the above description is only a preferred embodiment of the utility model, and it should be pointed out that for those of ordinary skill in the art, some improvements can also be made without departing from the principle of the utility model and retouching, these improvements and retouching should also be regarded as the protection scope of the present utility model.

Claims (10)

1. A kind of interface expansion circuit, it is characterized in that: comprise main processor and have the interface expansion module of multi-channel GPIO mouth, described interface expansion module connects the parallel interface of main processor by parallel bus, receives the interface that main processor sends Configure commands and data, and connect peripheral circuits through the GPIO port of the interface expansion module. 2. The interface expansion circuit according to claim 1, characterized in that: in the interface expansion module, a main processor interface unit, a GPIO functional logic unit, a GPIO configuration register, and a GPIO level status register are included; The processor interface unit is connected to the parallel interface of the main processor through the parallel bus, and writes data to the corresponding GPIO configuration register or GPIO level status register according to the interface configuration command and data received; Configure the state of the corresponding GPIO port with the data in the GPIO level status register. 3. The interface expansion circuit according to claim 2, characterized in that: the master processor interface unit uses a state machine in a level detection mode to create a parallel slave interface. 4. The interface expansion circuit according to claim 3, characterized in that: the parallel interface of the main processor is an I8080 interface. 5. The interface expansion circuit according to claim 1, characterized in that: a keyboard scanning logic unit and a keyboard scanning code register are included in the interface expansion module, and the keyboard scanning logic unit is connected to the interface expansion module for connecting When the GPIO port of the matrix keyboard circuit detects that a key is pressed, the key scan code is transmitted to the keyboard scan code register for storage, and an interrupt signal is generated and transmitted to the interrupt interface of the main processor. 6. The interface expansion circuit according to claim 5, characterized in that: the keyboard scanning logic unit is connected to the main processor interface unit, and the generated interrupt signal is transmitted to the main processor interface unit, and is connected to the main processor interface unit. Interrupt interface to the host processor. 7. The interface extension circuit according to claim 5, characterized in that: a line scan counter module, a debounce clock frequency division module, a debounce logic module and a keyboard matrix scan module are included in the keyboard scan logic unit; The debounce clock frequency division module receives the system clock, transmits it to the debounce logic module to generate the debounce synchronous clock after frequency division, and then outputs it to the keyboard matrix scanning module; the row scan counter module receives the system clock, Generate the counting clock and transmit it to the keyboard matrix scanning module; the keyboard matrix scanning module is connected to the GPIO port on the interface expansion module for connecting the matrix keyboard circuit, detects the state of the key, and presses the key when it is detected At this time, the key scan code is generated and stored in the keyboard scan code register, and an interrupt signal is generated and output to the main processor. 8 . The interface expansion circuit according to claim 7 , wherein the debounce logic module is composed of a shift register composed of three groups of synchronous flip-flops. 9. The interface expansion circuit according to claim 1, wherein the interface expansion module is a programmable logic device (CPLD). 10. A mobile terminal, characterized in that it includes the interface expansion circuit according to any one of claims 1 to 9.

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