CN114487793A - Chip functionality test unit, test method, chip and automatic test system - Google Patents
Chip functionality test unit, test method, chip and automatic test system Download PDFInfo
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Abstract
The invention provides a chip functionality test unit, a test method, a chip and an automatic test system, wherein the test unit comprises a plurality of peripheral function modules, a GPIO multiplexing function module and a self-test module; and the self-test module is used for controlling all the peripheral functional modules to output interface signals of the GPIO multiplexing functional module through the self-test mode in the functional test stage of the tested chip and carrying out functional test on the GPIO multiplexing functional module based on the output interface signals. The self-test module is added in the tested chip, the main function is to control the output enabling and the output data of all the peripheral function modules when the GPIO multiplexing function module function pattern is developed, so that most of logic of the GPIO multiplexing function module can be covered by one function pattern, the test coverage rate of the GPIO multiplexing function module is improved, and the test efficiency is also improved.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a chip functionality test unit, a test method, a chip, and an automatic test system.
Background
With the development of chip technology, the functions of a chip become more and more complex, the number of functional modules inside the chip also becomes more and more, and the number of interfaces required to be connected to pins of the chip also becomes more and more, so that the number of pins of the chip also increases, and the multiplexing and mapping functions of GPIO (General Purpose Input Output) also become more and more complex. In a common chip, a maximum of 6 to 7 peripheral functional modules are connected to one GPIO multiplexing functional module. The interface signal of each peripheral function module is mapped to 4 GPIO multiplexing function sub-units in the GPIO multiplexing function module at most.
Since the GPIO function is more complicated and the combinational logic is more, the ATPG (Automatic Test Pattern Generation) Test coverage of the chip GPIO is difficult to reach over 90%, which requires analyzing the remaining fault points and adding a function Pattern to cover the remaining fault points in the FT Test stage. However, GPIOs are more interface signals of internal functional modules, and therefore development of functional patterns corresponding to each peripheral functional module is required, resulting in a large number of functional patterns, long test time, and high test cost.
Disclosure of Invention
The invention provides a chip functionality test unit, a test method, a chip and an automatic test system, aiming at the technical problems of long test time and high test cost of GPIO functions in the prior art.
According to a first aspect of the present invention, a chip functionality test unit is provided, which includes a plurality of peripheral functional modules, a GPIO multiplexing functional module, and a self-test module; the self-test module is used for controlling output interface signals from all peripheral functional modules to the GPIO multiplexing functional module through the self-test mode in the functional test stage of the tested chip, and carrying out functional test on the GPIO multiplexing functional module based on the output interface signals so as to improve the test coverage rate.
On the basis of the technical scheme, the invention can be improved as follows.
Optionally, the GPIO multiplexing functional module includes a plurality of GPIO multiplexing functional sub-units; the self-test module is used for controlling output interface signals from all peripheral functional modules to a GPIO multiplexing functional module through a self-test mode in a functional test stage of a chip to be tested, and carrying out functional test on the GPIO multiplexing functional module based on the output interface signals, and comprises the following steps: and setting a function test mode of the tested chip, and controlling the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit through the self-test mode so as to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module.
Optionally, the self-test module includes a global control register, and the controlling, by the self-test mode, the output enable signal and the output data signal of each peripheral function module to the corresponding GPIO multiplexing function sub-unit to test the function of each GPIO multiplexing function sub-unit in the GPIO multiplexing function module includes: and controlling the output enabling signal and the output data signal of each peripheral function module to the corresponding GPIO multiplexing function sub-unit by setting the relevant bit of the global control register so as to test the function of each GPIO multiplexing function sub-unit.
According to a second aspect of the present invention, there is provided a chip functionality testing method, comprising: and a self-test module is added in the tested chip, and in the functional test stage of the tested chip, the self-test mode of the self-test module controls output interface signals from all peripheral functional modules to the GPIO multiplexing functional module so as to perform functional test on the GPIO multiplexing functional module based on the output interface signals and improve the test coverage rate.
Optionally, the GPIO multiplexing functional module includes a plurality of GPIO multiplexing functional sub-units; in a functional test stage of the chip to be tested, the self-test mode of the self-test module controls output interface signals from all peripheral functional modules to a GPIO multiplexing functional module so as to perform a functional test on the GPIO multiplexing functional module based on the output interface signals, and the method comprises the following steps: and setting a function test mode of the tested chip, and controlling the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit through the self-test mode so as to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module.
Optionally, the controlling, by the self-test mode, the output enable signal and the output data signal of each peripheral function module to the corresponding GPIO multiplexing function subunit to test the function of each GPIO multiplexing function subunit in the GPIO multiplexing function module includes: and configuring a global control register in the self-test module, and controlling an output enabling signal and an output data signal of each peripheral function module to a corresponding GPIO multiplexing function subunit by setting a relevant bit of the global control register so as to test the function of each GPIO multiplexing function subunit.
Optionally, the GPIO multiplexing functional module has a plurality of multiplexing functions, and the setting of the relevant bit of the global control register controls the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit, so as to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module, including: in the functional test stage of the tested chip, the GPIO multiplexing functional module is switched to a first multiplexing function through the global control register in a self-test mode; controlling output enabling signals output to the GPIO multiplexing functional subunits by all the peripheral functional modules through output enabling bits of the global control register, and recording a first test result of each GPIO multiplexing functional subunit; controlling output data signals output to the GPIO multiplexing functional subunits by all the peripheral functional modules through output data bits of the global control register, and recording a second test result of each GPIO multiplexing functional subunit; and closing all the output enabling signals sent to the GPIOs by the peripheral functional modules through the output enabling bits of the global register, and recording a third test result of each GPIO multiplexing functional subunit.
Optionally, the method further includes determining a success or failure test result of the first multiplexing function of the GPIO multiplexing functional module according to the first test result, the second test result, and the third test result:
respectively comparing the first test result, the second test result and the third test result with corresponding expected results, and determining that the first multiplexing function test of the GPIO multiplexing function module is successful when the first test result, the second test result and the third test result are consistent with the corresponding expected results; otherwise, determining that the first multiplexing function test of the GPIO multiplexing function module fails.
Optionally, the GPIO multiplexing function module is switched to the remaining multiplexing functions through the global control register, and all the multiplexing functions are tested in a traversal manner.
According to a third aspect of the invention, a chip is provided comprising a chip functionality test unit.
According to a fourth aspect of the present invention, an automatic test system is provided, which includes a machine station and a chip to be tested, wherein the chip to be tested includes a chip functionality test unit;
the machine station is used for writing the developed test case into a tested chip; comparing the test value returned by the tested chip with an expected value, and determining a test result according to the comparison result;
and the tested chip is used for completing the test according to the test case and returning the test value to the machine.
According to the chip functionality test unit, the test method, the chip and the automatic test system, the self-test module is added in the tested chip, the main function is that when the GPIO multiplexing function module function pattern is developed, the output enabling and the output data of all peripheral function modules can be controlled, most of logic of the GPIO multiplexing function module can be covered by one function pattern, the test coverage rate of the GPIO multiplexing function module is improved, and the test efficiency is also improved.
Drawings
FIG. 1 is a schematic diagram of a conventional chip under test;
FIG. 2 is a schematic structural diagram of a chip functionality test unit according to a first embodiment of the present invention;
FIG. 3 is a flow chart illustrating a chip functionality testing method according to a second embodiment of the present invention;
fig. 4 is a flowchart illustrating a chip functionality testing method according to a third embodiment of the invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
For a chip with a GPIO multiplexing function, in the design of a conventional GPIO function module, as shown in fig. 1, external function modules such as UART (Universal Asynchronous Receiver/Transmitter), spi (Serial Peripheral Interface), i2c (Inter-Integrated circuit, two-wire Serial bus), and the output signal and the output enable signal of the GPIO function module are sent to the GPIO multiplexing function module, and then are selected by the GPIO multiplexing function and finally sent to an external pin. However, since the GPIO multiplexing function module has complex logic, the coverage rate in the ATPG (Automatic Test Pattern Generation) Test is less than 90%, and the remaining fault points (uncovered points) need to be analyzed and then covered by developing the function Pattern of each peripheral function module. Therefore, external functional modules such as UART, spi, i2c and the like are required to develop the relevant function pattern to cover the fault point of the GPIO multiplexing functional module, and not only a large amount of human resources are required, but also the number of patterns is large.
Table 1 multiplexing function table of GPIO multiplexing function module
Table 1 shows a multiplexing Function table of GPIO multiplexing functional modules, where each GPIO multiplexing functional module has 7 multiplexing functions (where the specific number is only an example, and the number of the multiplexing functions is more as the number of the peripherals is more), the Function1 tests the input and output functions of the GPIOs themselves, and the fcation 2-Function7 tests the multiplexing functions of the GPIOs. The combinations of peripherals under each Function in this table are only examples, and there may be more than one peripheral per Function in actual use, for example, there may be 3 UARTs. Each GPIO multiplexing functional module comprises a plurality of GPIO multiplexing functional subunits, each peripheral functional module can be mapped to 3-8 GPIO multiplexing functional subunits, and in the prior art, 2-3 patterns are independently arranged on each peripheral, so that the number of the patterns is large, the execution is complex and time-consuming, and the reasons are that the GPIO multiplexing functional module is complex in logic and the ATPG coverage rate is low.
When the GPIO multiplexing functional module is to be functionally tested, it is necessary to test the output interface signals of each GPIO multiplexing functional subunit corresponding to different peripheral functional modules. In the past, the number of GPIO multiplexing functional subunits is small, and the multiplexing function is not so much, so that for the remaining fault points after the ATPG test, the functional patterns are developed by corresponding peripheral modules, for example: the uart realizes the signal inversion of the uart interface by developing a function pattern of the uart interface, and covers corresponding fault points of the GPIO multiplexing function module, but the interface signal of the uart can be mapped to other GPIO multiplexing function subunits, so that one function pattern cannot cover all fault points related to the uart of the GPIO multiplexing function module, and a plurality of function patterns need to be supplemented, thereby directly influencing the chip testing time.
Because the number of GPIO multiplexing functional subunits in a GPIO multiplexing functional module of a previous chip is less, and the multiplexing and mapping functions are simple, the number of FT patterns is relatively less, the testing time is shorter, the number of GPIOs is increased along with the increase of the complexity of the chip, and the multiplexing and mapping functions are more complex. At present, the number of GPIO multiplexing functional subunits is large, the multiplexing function and the mapping function are complex, and during the FT function test, functional patterns need to be developed, but interface signals of GPIOs come from a plurality of peripheral functional modules, so that the number of the developed functional patterns is large, and the test cost is increased greatly.
Therefore, the self-test logic circuit is added in the tested chip, the number of the function patterns is reduced, corresponding function modules are not needed to be added, the time for generating the function patterns and the running time of the function patterns can be effectively reduced, and the test cost is saved.
Example one
A chip functionality test unit, see fig. 2, includes a plurality of peripheral functional modules and GPIO multiplexing functional modules, and also includes a self-test module; the self-test module is used for controlling output interface signals from all peripheral functional modules to the GPIO multiplexing functional module through the self-test mode in the functional test stage of the tested chip, and carrying out functional test on the GPIO multiplexing functional module based on the output interface signals so as to improve the test coverage rate.
It can be understood that, in order to solve the defect of the traditional test of the GPIO multiplexing functional module, the embodiment of the present invention adds a self-test module in the tested chip, so as to control the output interface signal from the peripheral functional module to the GPIO multiplexing functional module through the self-test mode in the functional test stage of the tested chip, thereby improving the test coverage of the GPIO multiplexing functional module, and simultaneously, the development of the functional pattern by each peripheral functional module is not required, so that the labor cost is saved.
As an embodiment, the GPIO multiplexing functional module includes a plurality of GPIO multiplexing functional sub-units, and the self-test module is configured to control, in a functional test phase of a chip under test, output interface signals from all peripheral functional modules to the GPIO multiplexing functional module through a self-test mode, and perform a functional test on the GPIO multiplexing functional module based on the output interface signals, and includes: and setting a function test mode of the tested chip, and controlling the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit through the self-test mode so as to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module.
It can be understood that, in order to reduce the number of GPIO multiplexing functional module development function patterns and save labor cost, the embodiment of the present invention adds the self-test module shown in fig. 2, and the main function of the self-test module is to control the output enable signals and the output data signals of all peripheral functional modules such as uart, spi, i2c, etc. when developing the function patterns of the GPIO multiplexing functional module, so that one function pattern can cover the logic of most GPIO multiplexing functional modules. If the GPIO multiplexing function module is covered by peripheral function module development function patterns such as uart, spi, i2c, 1-3 function patterns need to be developed by each peripheral function module. The self-test module is only used in the FT test stage of the GPIO multiplexing functional module, and does not influence the normal use of the tested chip.
As an embodiment, the self-test module includes a global control register, and the controlling, by the self-test mode, the output enable signal and the output data signal of each peripheral function module to the corresponding GPIO multiplexing function sub-unit to test the function of each GPIO multiplexing function sub-unit in the GPIO multiplexing function module includes: and controlling the output enabling signal and the output data signal of each peripheral function module to the corresponding GPIO multiplexing function sub-unit by setting the relevant bit of the global control register so as to test the function of each GPIO multiplexing function sub-unit.
It can be understood that, for the convenience of the user, each GPIO multiplexing function subunit has a corresponding control register, and if all registers are traversed while developing the function pattern, the test time is long. In order to save the test time of the function pattern, in the self-test mode, the embodiment of the present invention controls the control signals of all GPIO multiplexing functional sub-units through one global control register, such as: all multiplexing functions of the GPIO multiplexing functional module can be switched through one global control register, so that a lot of time can be saved when the multiplexing functions are switched, the function is only used for FT test, and normal functions are not affected.
In the embodiment of the invention, in the FT test of the GPIO multiplexing functional module, the mode of the GPIO multiplexing functional module is adjusted to the self-test mode, then the output enable signals and the output data signals of all the peripheral functional modules are controlled by writing the relevant bits of the relevant global control register, and each functional point of the GPIO multiplexing functional module is tested to cover the fault point of the GPIO multiplexing functional module.
Example two
A method for testing functionality of a chip, the method comprising: and a self-test module is added in the tested chip, and in the functional test stage of the tested chip, the self-test mode of the self-test module controls output interface signals from all peripheral functional modules to the GPIO multiplexing functional module so as to perform functional test on the GPIO multiplexing functional module based on the output interface signals, thereby improving the test coverage rate.
It can be understood that the embodiment of the invention adds the self-test module in the tested chip, so that the output interface signal from the peripheral function module to the GPIO multiplexing function module is controlled through the self-test mode in the FT stage, the test coverage rate of the GPIO multiplexing function module is improved, meanwhile, the development function pattern of each peripheral function module is not required, and the labor cost is saved.
As an embodiment, the GPIO multiplexing functional module includes a plurality of GPIO multiplexing functional sub-units; in a functional test stage of a chip to be tested, controlling output interface signals from all peripheral functional modules to a GPIO multiplexing functional module through a self-test mode of the self-test module so as to perform a functional test on the GPIO multiplexing functional module based on the output interface signals, wherein the functional test comprises the following steps: and setting a function test mode of the tested chip, and controlling the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit through the self-test mode so as to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module.
Wherein, the controlling the output enable signal and the output data signal of each peripheral function module to the corresponding GPIO multiplexing function sub-unit through the self-test mode to test the function of each GPIO multiplexing function sub-unit in the GPIO multiplexing function module includes: and configuring a global control register in the self-test module, and controlling an output enabling signal and an output data signal of each peripheral function module to a corresponding GPIO multiplexing function subunit by setting a relevant bit of the global control register so as to test the function of each GPIO multiplexing function subunit.
It can be understood that, when performing the FT test on the GPIO multiplexing function module, the machine writes the developed FT pattern into the chip to be tested, as shown in fig. 3, and then the chip to be tested returns a test value to the machine, and the machine returns a test result by comparing the test value with an expected value. And finally reading the test result as pass or fail, and if fail is tested, needing debug reasons. The specific FT pattern development flow is shown in fig. 4.
When the GPIO multiplexing functional module is specifically subjected to an FT test, the setting of the relevant bit of the global control register controls the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional subunit to test the function of each GPIO multiplexing functional subunit in the GPIO multiplexing functional module, including: in the functional test stage of the tested chip, the GPIO multiplexing functional module is switched to a first multiplexing function through the global control register in a self-test mode; controlling output enabling signals output to the GPIO multiplexing functional subunits by all the peripheral functional modules through output enabling bits of the global control register, and recording a first test result of each GPIO multiplexing functional subunit; controlling output data signals output to the GPIO multiplexing functional subunits by all peripheral functional modules through output data bits of the global control register, and recording a second test result of each GPIO multiplexing functional subunit; and closing all the output enabling signals sent to the GPIOs by the peripheral functional modules through the output enabling bits of the global register, and recording a third test result of each GPIO multiplexing functional subunit. And then determining the success or failure test result of the first multiplexing function of the GPIO multiplexing functional module according to the first test result, the second test result and the third test result.
Determining a success or failure test result of the corresponding multiplexing function of the GPIO multiplexing functional module according to the first test result, the second test result and the third test result, wherein the method comprises the following steps: respectively comparing the first test result, the second test result and the third test result with corresponding expected results, and determining that the first multiplexing function test of the GPIO multiplexing function module is successful when the first test result, the second test result and the third test result are consistent with the corresponding expected results; otherwise, determining that the first multiplexing function test of the GPIO multiplexing function module fails.
After the first multiplexing function of the GPIO multiplexing functional module is tested, the GPIO multiplexing functional module is switched to the rest multiplexing functions through the global control register, and all the multiplexing functions are tested in a traversing way. It can be understood that each multiplexing function of the GPIO multiplexing functional module is tested, and the success or failure test result of the GPIO multiplexing functional module is determined according to the success or failure test result of each multiplexing function. When each multiplexing function of the GPIO multiplexing functional module is tested successfully, determining that the GPIO multiplexing functional module is tested successfully; otherwise, the GPIO multiplexing functional module fails to test.
Wherein, referring to Table 1, the present invention is to multiplex the functional subunit GIPO1-GPIOnAfter the first multiplexing function1 is tested, the GIPO is tested again1-GPIOnAnd so on until all multiplexing functions of all multiplexing function subunits have been tested.
One pattern in the self-test module self-test can complete (cover) the test (ATGP test) of more than 90% of function1-7 in the GPIO pin table 1, the number of the patterns is greatly reduced, the test efficiency is high, the main solution of the invention is the test efficiency of the part, and the invention is also the main invention point of the invention. In addition, a few residual GPIO pin multiplexing function tests which are not covered can be realized by adding a few patterns in the self-test, and the test coverage rate of the GPIO multiplexing function module is improved.
Specifically, the process of performing the FT test on the GPIO multiplexing functional module may be seen in fig. 4, and mainly includes the following steps:
1) and in the functional test stage, switching the working mode of the GPIO multiplexing functional module to a self-test mode.
2) Switching the GPIO multiplexing functional module to the multiplexing function1 through the global control register in self-test mode.
3) And opening uart and other external function modules through the output enable bit of the global control register, sending all output enable signals to the GPIO multiplexing function module, comparing the test result returned by the GPIO multiplexing function module with an expected result, recording the test result, and carrying out the next test.
4) The output data signals from the uart and other external functional modules to the GPIO multiplexing functional module are controlled through the output data bits of the global control register, so that the output data signals of all the external functional modules are controlled to be inverted (0-1, 1-0). And comparing the test result with the expected result every time the test is turned over, recording the test result, and carrying out the next test.
5) And closing all the peripheral function modules by the output enable bit of the global control register to send the output enable signal of the GPIO multiplexing function module, comparing the test result with an expected result, recording the test result, and carrying out the next test.
6) And switching the GPIO multiplexing functional module to the multiplexing function2, and repeating the steps until all the multiplexing functions of the GPIO multiplexing functional module are tested.
It should be noted that, the above 2) to 5) are to perform a function test on one multiplexing function of the GPIO multiplexing function module, where the embodiment of the present invention performs three function tests on one multiplexing function, including turning on an output enable signal, turning over an output signal, and turning off the output enable signal, and when three test results are consistent with an expected result, the test of the GPIO multiplexing function module is successful; otherwise, the test of the GPIO multiplexing functional module fails. And then, testing all multiplexing functions of the GPIO multiplexing functional module, wherein the GPIO multiplexing functional module is tested successfully only when all multiplexing functions of the GPIO multiplexing functional module are tested successfully, and the GPIO multiplexing functional module is tested failed as long as one multiplexing function fails.
EXAMPLE III
The chip to be tested comprises the chip functionality test unit of the first embodiment, wherein the working principle of the chip functionality test unit can refer to the first embodiment, and the description is not repeated here.
Example four
An automatic test system comprises a machine table and a chip to be tested in the third embodiment, wherein the machine table is used for writing a developed test case into the chip to be tested; comparing the test value returned by the tested chip with an expected value, and determining a test result according to the comparison result; and the tested chip is used for completing the test according to the test case and returning the test value to the machine.
The working principle of the chip to be tested can refer to the third embodiment, and the description is not repeated here.
According to the chip functionality test unit, the test method, the chip and the automatic test system, the self-test module is additionally arranged, so that the output interface signal from each peripheral functional module to the GPIO multiplexing functional module can be conveniently turned over through the self-test mode in the functional test stage, the test coverage rate of the GPIO multiplexing functional module is improved, meanwhile, the peripheral functional modules are not required to develop a function pattern, and the labor cost is saved.
In addition, in the self-test mode, a global control register is used for controlling control signals from all peripheral functional modules to the GPIO multiplexing functional module, so that one-key switching is realized, and the test time is saved.
It should be noted that, in the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to relevant descriptions of other embodiments for parts that are not described in detail in a certain embodiment.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. A chip functionality test unit comprises a plurality of peripheral functional modules and GPIO multiplexing functional modules, and is characterized by further comprising a self-test module;
the self-test module is used for controlling output interface signals from all peripheral functional modules to the GPIO multiplexing functional module through the self-test mode in the functional test stage of the tested chip, and carrying out functional test on the GPIO multiplexing functional module based on the output interface signals so as to improve the test coverage rate.
2. The chip functionality test unit of claim 1, wherein the GPIO multiplexing functional module comprises a plurality of GPIO multiplexing functional sub-units;
the self-test module is used for controlling output interface signals from all peripheral functional modules to a GPIO multiplexing functional module through a self-test mode in a functional test stage of a chip to be tested, and carrying out functional test on the GPIO multiplexing functional module based on the output interface signals, and comprises the following steps:
and setting a function test mode of the tested chip, and controlling the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit through the self-test mode so as to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module.
3. The chip functionality test unit of claim 2, wherein the self-test module comprises a global control register, the controlling the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit through the self-test mode to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module comprises:
and controlling the output enabling signal and the output data signal of each peripheral function module to the corresponding GPIO multiplexing function sub-unit by setting the relevant bit of the global control register so as to test the function of each GPIO multiplexing function sub-unit.
4. A method for testing chip functionality, comprising:
and a self-test module is added in the tested chip, and in the functional test stage of the tested chip, the self-test mode of the self-test module controls output interface signals from all peripheral functional modules to the GPIO multiplexing functional module so as to perform functional test on the GPIO multiplexing functional module based on the output interface signals and improve the test coverage rate.
5. The chip functionality testing method according to claim 4, wherein the GPIO multiplexing functional module comprises a plurality of GPIO multiplexing functional sub-units;
in a functional test stage of the chip to be tested, the self-test mode of the self-test module controls output interface signals from all peripheral functional modules to a GPIO multiplexing functional module so as to perform a functional test on the GPIO multiplexing functional module based on the output interface signals, and the method comprises the following steps:
and setting a function test mode of the tested chip, and controlling the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit through the self-test mode so as to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module.
6. The chip functionality test method according to claim 5, wherein the controlling the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit through the self-test mode to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module comprises:
and configuring a global control register in the self-test module, and controlling an output enabling signal and an output data signal of each peripheral function module to a corresponding GPIO multiplexing function subunit by setting a relevant bit of the global control register so as to test the function of each GPIO multiplexing function subunit.
7. The chip functionality test method according to claim 6, wherein the GPIO multiplexing functional module has a plurality of multiplexing functions, and the controlling the output enable signal and the output data signal of each peripheral functional module to the corresponding GPIO multiplexing functional sub-unit by setting the relevant bit of the global control register so as to test the function of each GPIO multiplexing functional sub-unit in the GPIO multiplexing functional module comprises:
in the functional test stage of the tested chip, the GPIO multiplexing functional module is switched to a first multiplexing function through the global control register in a self-test mode;
controlling output enabling signals output to the GPIO multiplexing functional subunits by all the peripheral functional modules through output enabling bits of the global control register, and recording a first test result of each GPIO multiplexing functional subunit;
controlling output data signals output to the GPIO multiplexing functional subunits by all the peripheral functional modules through output data bits of the global control register, and recording a second test result of each GPIO multiplexing functional subunit; and (c) a second step of,
and closing output enabling signals sent to the GPIOs by all the peripheral functional modules through the output enabling bits of the global register, and recording a third test result of each GPIO multiplexing functional subunit.
8. The chip functionality testing method according to claim 7, further comprising determining a test success or failure result of the first multiplexing function of the GPIO multiplexing functional module according to the first test result, the second test result, and the third test result:
respectively comparing the first test result, the second test result and the third test result with corresponding expected results, and determining that the first multiplexing function test of the GPIO multiplexing function module is successful when the first test result, the second test result and the third test result are consistent with the corresponding expected results; otherwise, determining that the first multiplexing function test of the GPIO multiplexing function module fails.
9. The chip functionality test method according to claim 7, wherein all the multiplexing functions are tested in a traversal manner by switching the GPIO multiplexing function module to the remaining multiplexing functions through the global control register.
10. A chip to be tested, characterized in that it comprises a chip functionality test unit according to any of claims 1-3.
11. An automatic test system, comprising a machine and the chip to be tested of claim 10;
the machine station is used for writing the developed test case into a tested chip; comparing the test value returned by the tested chip with an expected value, and determining a test result according to the comparison result;
and the tested chip is used for completing the test according to the test case and returning the test value to the machine.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116243147A (en) * | 2023-05-09 | 2023-06-09 | 武汉芯必达微电子有限公司 | PAD function matrix-based integrated control chip peripheral self-test method and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101377764A (en) * | 2008-09-12 | 2009-03-04 | 北京中星微电子有限公司 | Allocating system of GPIO and data communicating method thereof |
| CN104407882A (en) * | 2014-10-28 | 2015-03-11 | 大唐移动通信设备有限公司 | Board card device |
| CN112614534A (en) * | 2020-12-17 | 2021-04-06 | 珠海市一微半导体有限公司 | MBIST circuit system |
| CN216209527U (en) * | 2021-09-30 | 2022-04-05 | 合肥移瑞通信技术有限公司 | GPIO interface state testing device |
-
2022
- 2022-04-13 CN CN202210385968.5A patent/CN114487793A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101377764A (en) * | 2008-09-12 | 2009-03-04 | 北京中星微电子有限公司 | Allocating system of GPIO and data communicating method thereof |
| CN104407882A (en) * | 2014-10-28 | 2015-03-11 | 大唐移动通信设备有限公司 | Board card device |
| CN112614534A (en) * | 2020-12-17 | 2021-04-06 | 珠海市一微半导体有限公司 | MBIST circuit system |
| CN216209527U (en) * | 2021-09-30 | 2022-04-05 | 合肥移瑞通信技术有限公司 | GPIO interface state testing device |
Non-Patent Citations (1)
| Title |
|---|
| 邓力等主编: "《ARM嵌入式系统——基于ADS1.2及Proteus仿真》", 31 August 2016 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116243147A (en) * | 2023-05-09 | 2023-06-09 | 武汉芯必达微电子有限公司 | PAD function matrix-based integrated control chip peripheral self-test method and device |
| CN116243147B (en) * | 2023-05-09 | 2023-08-18 | 武汉芯必达微电子有限公司 | PAD function matrix-based integrated control chip peripheral self-test method and device |
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