CN114679415A - Non-blocking banyan network meeting AXI5-Lite protocol standard - Google Patents
Non-blocking banyan network meeting AXI5-Lite protocol standard Download PDFInfo
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Abstract
The non-blocking banyan network meeting AXI5-Lite protocol standard includes several exchange units constituting the exchange network and 5 kinds of non-interference double transmission channels set inside; each input port of the switching network is correspondingly provided with a cache unit group, and the host cache unit group and the slave cache unit group are provided with cache units with different numbers and different types and used for receiving signals from the host and the slave and storing and transmitting information packets; the buffer unit is provided with a plurality of buffer queues, and the number of the buffer queues is the same as that of the receiving ends; a scheduler is arranged in the double transmission channel and used for distributing priority to the information packets to be transmitted in the buffer queue; and setting effective control bits and subsequent data bits for the data information packets in the transmission channels, wherein the transmission bus width of each transmission channel is consistent with the length of the data information packet. The non-blocking banyan network meeting the AXI5-L ite protocol standard ensures non-blocking, high-performance and low-delay transmission of data resources and can reduce the complexity of the network.
Description
Technical Field
The application relates to the field of communication, in particular to a non-blocking banyan network meeting the AXI5-Lite protocol standard.
Background
With the continuous expansion of the communication demand among electronic devices, the requirements of various industries on the rate, delay and accuracy of resource data transmission are continuously improved, the performance of an electronic system is determined to a certain extent by an internet, and a good internet needs to meet the following requirements: on one hand, resources of each part can be mobilized with high performance, low delay and no blocking, and on the other hand, the resources occupied by the internet can be small.
Only when the switching network is matched with a proper communication protocol can each module be efficiently linked, and the advantages of the switching network and the communication protocol are highlighted, so that how to design a good interconnection network through the matching of the switching network and the communication protocol becomes one of the key points for developing the communication technology. The traditional switching network meeting the AXI protocol standard has the problems of high blocking rate, high network transmission delay and the like, although the networks with low blocking rates such as crossbar, close and the like can effectively transmit data, the complexity of the networks is high, and channels with different protocols are realized by using separate switching networks, so that the complexity of the switching network is higher, no blocking can not be realized in effect, and even the situation of data packet loss can occur.
The AXI5-Lite bus has simpler structure, easier understanding of internal logic, easy modification and verification, AXI5-Lite allows variable data width transmission, can realize out-of-order transmission, can simplify communication transmission, and has strong compatibility. The banyan network is a representative network of a multi-stage interconnection network, and has the advantages of simple structure, small number of intermediate nodes, low network complexity and easiness in expansion.
Therefore, a new network structure is needed to combine the AXI5-Lite bus protocol with the banyan network, so that the new network structure can be well applied to various transmission with high requirements, high performance and low delay, and the efficient transmission among the communication modules is ensured.
Disclosure of Invention
To solve the problems in the prior art, the present application provides a non-blocking banyan network that meets the AXI5-Lite protocol standard, including:
a plurality of switching units constituting a switching network, wherein each switching unit includes 5 pairs of dual transmission channels;
a set of host I/O port cache units disposed between the switch network and a host to cache packets from the host to be sent to the switch network, wherein each host I/O port cache unit in the set of host I/O port cache units has a plurality of host cache queues therein,
the slave I/O port cache unit group is arranged between the switching network and the slaves to cache data packets from the slaves to be sent to the switching network, wherein each slave I/O port cache unit in the slave I/O port cache unit group is internally provided with a plurality of slave cache queues.
The dual transmission channel can meet the data back-and-forth transmission between a plurality of hosts and a plurality of slaves, data which cannot be transmitted at once is stored by arranging the host I/O port cache unit group and the slave I/O port cache unit group, so that the problem that a banyan network cannot simultaneously transmit information packets which are simultaneously applied for transmission at each time to cause blockage is solved, a plurality of cache queues are arranged in each cache unit, and each cache queue respectively stores the information packets which go to different destinations from the same input port of the same channel, thereby preventing the occurrence of head-of-line blockage.
In an optional embodiment, the master I/O port cache unit group includes three types of cache units respectively used for a read address packet, a write address packet, and a write data packet, and the slave I/O port cache unit group includes two types of cache units respectively used for a read data packet and a response packet.
The setting mode of the cache units in the host I/O port cache unit group and the slave I/O port cache unit group meets the communication requirements of the host and the slave, solves the problem that the efficiency is slowed down when a plurality of different types of equidirectional transmission information packets are transmitted by one network, and greatly reduces the consumption of hardware.
In an optional embodiment, the master I/O port cache unit group accepts a ready signal directly sent from a slave, and the slave I/O port cache unit group accepts a ready signal directly sent from a master.
The host I/O port cache unit group and the slave I/O port cache unit group can judge whether the slave and the host are in the operating state through the received ready signal, and forbids or allows the information packet to be transmitted into the switching network according to the ready signal.
In an optional embodiment, the number of the plurality of master buffer queues is equal to the number of slaves connected to the switching network, and the number of the plurality of slave buffer queues is equal to the number of masters connected to the switching network.
The number of the buffer queues is the same as that of the host and the slave which are externally connected, so that the transmission efficiency of the information packet is greatly improved, and the blocking phenomenon is avoided.
In a further alternative embodiment, the 5 pairs of dual transfer channels include 5 pairs of dual transfer channels for write data, write address, read data, read address, and response, respectively.
5 pairs of dual transmission channels in the exchange unit correspond to 5 different channels of AXI5-Lite protocol, and the advantages of the AXI protocol are exerted.
In a further optional embodiment, the banyan network further comprises 5 schedulers connected to the switching network, the 5 schedulers assigning priorities to pending packets in the buffer queues for 5 pairs of dual transmission channels, respectively.
The priority is distributed according to the delay of each storage queue head information packet and the remaining storage data space of the storage queue, the smaller the remaining storage space of the appointed queue is, the longer the storage queue head information packet is delayed, the higher the priority is, the information packet stored in the internal part should be transmitted preferentially, and the effect of high performance and low delay is achieved by setting the priority for scheduling in the transmission of the switching network.
In an alternative embodiment, for the channel for writing the address and the channel for reading the address, the data packet includes 7 valid control signal bits and control signals corresponding to the valid control signal bits;
for the channel of the write response, the data packet therein includes 5 bits of valid control signal bits and the control signal corresponding to the 5 bits of valid control signal bits.
In a further alternative embodiment, for a data write channel and a data read channel, the data packet includes 4 bits of valid control signal bits and a control signal corresponding to the 4 bits of valid control signal bits, and the data packet further includes a data signal, and the size of the valid data of the data signal is determined by the corresponding control signal.
In an alternative embodiment, the control signal is arranged to be transmitted together with the data signal in one complete packet. Because each bit in the information packet corresponds to a signal with a fixed function, the information packet is only required to be transmitted to a corresponding receiving terminal interface according to bit separation during output, and the effective control signal bit is used for determining which control information is effective and determining which data signal is effective according to the control signal.
The front end of each data information packet is provided with an effective control signal position, and for 5 pairs of channels, the effective control signal position is different from the sum of the control signal positions, and only a data information packet and a data information packet are written to have the data signal positions, so that the size of the information packet of each channel is different, and through the setting of the effective control signal positions, the receiving end is told which signals can be directly skipped, and the convenience of reading the information packet is guaranteed.
In an alternative embodiment, each of the 5 pairs of dual transfer channels has a transfer bus width that corresponds to the length of the data packet, the length of the packet being longer due to the presence of data signals in the read data packet and the write data packet, and the transfer widths of the read data transfer channel and the write data transfer channel corresponding to each other being wider.
The width of the information packet transmission bus of each channel in the integrated banyan network is consistent with the length of the information packet, parallel transmission of the information packets is guaranteed, and one-time transmission can be completed.
In an optional embodiment, the master I/O port cache unit group receives a valid signal from the master to determine whether the master is to send data, the master I/O port cache unit group gives a ready signal of always set to 1 to the master so that data is directly transmitted to the master cache unit group, the slave I/O port cache unit group receives a valid signal from the slave to determine whether the slave is to send data, and the slave I/O port cache unit group gives a ready signal of always set to 1 to the slave so that data is directly transmitted to the slave cache unit.
In an optional embodiment, when the packet is transmitted from the master to the slave, once the output port of the switching network detects that the packet passes through, the output port of the switching network gives a valid signal to a channel corresponding to the packet of the destination slave;
when a packet is transmitted from a slave to a master, once the output port of the switching network detects that the packet passes through, the output port of the switching network gives a valid signal to the channel corresponding to the packet of the destination master.
In a further embodiment, an output port of the switch network reads the phase or result of the valid control bit to determine whether a packet passes through, and if the phase or result of the valid control bit is 1, it determines that a packet passes through, a valid signal of 1 is given to the receiving end.
The buffer unit group gives a ready signal of which the sending end is always set to be 1, and simultaneously receives a valid signal from the sending end, when the valid signal bit of the transmission channel of the sending end is 1, the buffer unit corresponding to the transmission channel knows that the sending equipment of the channel needs to send data, so that the buffer unit group directly processes the signals received from the sending end without considering the state of the receiving end equipment and assembles the signals into information packets to be stored in an internal corresponding queue, and the sending end can continuously send data under the condition that the receiving end does not respond.
When the cache unit judges that the ready signal of the receiving end is 1, the information packet stored in the internal corresponding queue is accessed to the input port of the network, once the information packet from the sending end in the internal corresponding queue is selected for transmission, and when the information packet passes through the output port of the switching network, the output port of the switching network gives the receiving end a valid signal that the information packet corresponding to the transmission channel is set to be 1, so that the information packet stored in the internal queue of the cache unit can be successfully transmitted to the receiving end. The invention provides a non-blocking banyan network meeting an AXI5-Lite protocol standard, which comprises a plurality of switching units forming a switching network, wherein 5 non-interfering dual transmission channels are arranged inside the switching units; each input port of the switching unit is correspondingly provided with a cache unit group, the cache unit group is provided with cache units with different numbers and different types and used for receiving signals from a host and a slave and storing and transmitting information packets, the cache unit is provided with a plurality of cache queues, and the number of the cache queues is the same as that of the sending end; a scheduler is arranged in the dual transmission channel, the priority is distributed to the information packet to be transmitted in the buffer queue, an effective control bit and a subsequent data bit are arranged on the data information packet in the transmission channel, and each transmission channel has a transmission total line width consistent with the length of the data information packet; the basic unit of the banyan network is reestablished, so that the consumption of hardware is greatly reduced. The invention ensures the non-blocking, high-performance and low-delay transmission of data resources and can reduce the complexity of the network.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain the principles of the invention. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
FIG. 1a shows a block diagram of a banyan base switching unit according to one embodiment of the present invention;
FIG. 1b shows a block diagram of a banyan retrofitted switching unit according to one embodiment of the present invention;
FIG. 2 illustrates a schematic diagram of an example of the operation of a switching network according to one embodiment of the present invention;
FIG. 3 shows a detailed construction diagram of the inside of banyan according to one embodiment of the invention;
FIG. 4 illustrates an exemplary diagram of write data, read data packet components in accordance with one embodiment of the present invention;
figure 5 illustrates an exemplary diagram of AXI5-Lite protocol compatibility according to one embodiment of the invention;
FIG. 6 shows a schematic structural diagram of a computer system 600 of an electronic device according to one embodiment of the invention.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Fig. 1a shows a configuration diagram of a banyan basic switching unit according to an embodiment of the present invention, as shown in fig. 1a, when a packet passes through the switching unit of the basic banyan network, the packet may be from 0 input port to 0 output port, from 0 input port to 1 output port, from 1 input port to 0 output port, or from 1 input port to 1 output port, so that the packet input by different input ports can be successfully transmitted to different output ports.
However, this simple switching unit can only satisfy the transmission requirement of a unidirectional transmission channel, and if the AXI protocol is satisfied with smooth transmission, 5 such common switching units are required to form a banyan network.
Fig. 1b shows a configuration diagram of a banyan modified switch unit according to an embodiment of the present invention, where 5 general switch units are aggregated on one switch unit to satisfy 5 AXI channels with different attributes in different directions. In a specific embodiment, the write data channel is configured to transmit from left to right, the input port is provided with an input port 0 and an input port 1, which are respectively marked as W0 and W1, the output port is correspondingly provided with an output port 0 and an output port 1, which are marked as W '0 and W' 1, the W0 can freely transmit packets to the right to W '0 or W' 1, and the W1 can freely transmit packets to the right to W '0 or W' 1;
the write address channel is set to transmit from left to right, the input port is provided with an input port 0 and an input port 1 which are respectively marked as AW0 and AW1, the output port is correspondingly provided with an output port 0 and an output port 1 which are marked as AW '0 and AW' 1, the AW0 can freely transmit information packets to AW '0 or AW' 1 to the right, and the AW1 can freely transmit the information packets to AW '0 or AW' 1 to the right;
the address reading channel is set to transmit from left to right, the input port is provided with an input port 0 and an input port 1 which are respectively marked as AR0 and AR1, the output port is correspondingly provided with an output port 0 and an output port 1 which are marked as AR '0 and AR' 1, the AR0 can freely transmit information packets to AR '0 or AR' 1 rightwards, and the AR1 can freely transmit information packets to AR '0 or AR' 1 rightwards;
the read data channel is set to transmit from right to left, the input port is provided with an input port 0 and an input port 1 which are respectively marked as R0 and R1, the output port is correspondingly provided with an output port 0 and an output port 1 which are marked as R '0 and R' 1, R0 can freely transmit information packets to R '0 or R' 1 to left, and R1 can freely transmit information packets to R '0 or R' 1 to left;
the write response channel is set to transmit from right to left, the input port is provided with an input port 0 and an input port 1 which are respectively marked as Res0 and Res1, the output port is correspondingly provided with an output port 0 and an output port 1 which are marked as Res '0 and Res' 1, Res0 can freely transmit information packets to Res '0 or Res' 1 to left, and Res1 can freely transmit information packets to Res '0 or Res' 1 to left;
five pairs of dual transmission channels pass through one switching unit, and do not interfere with each other, compared with a banyan switching network formed by common switching units, five switching units are needed, and the switching unit shown in fig. 1b greatly reduces the consumption of hardware.
Fig. 2 is a schematic diagram illustrating an exemplary operation of a switching network according to an embodiment of the present invention, as shown in fig. 1, 4 master devices exchange data with 4 slave devices using an AXI5-Lite protocol based banyan switching network, where the 4 master devices are a master 11, a master 12, a master 13, and a master 14, and the 4 slave devices are a slave 21, a slave 22, a slave 23, and a slave 24.
In a specific embodiment, the master device and the slave device are directly connected to the port corresponding to the transport channel of the switching network when they are receiving ports.
In a specific embodiment, when the master device and the slave device are used as transmitting ends, a master I/O port cache unit group and a slave I/O port cache unit group, which are respectively a master I/O port cache unit group 31, a master I/O port cache unit group 32, a master I/O port cache unit group 33, a master I/O port cache unit group 34, a slave I/O port cache unit group 41, a slave I/O port cache unit group 42, a slave I/O port cache unit group 43, and a slave I/O port cache unit group 44, are provided at the input ports.
In a specific embodiment, since there are 3 AXI channels from the host to the slave, the host I/O port cache unit group includes 3 different cache units for respectively storing the read address, the write address and the write data packet.
In a specific embodiment, since there are two AXI channels from the slave to the host and the transmission is from right to left, the slave I/O port cache unit group includes 2 different cache units, which respectively store the response packet and the read data packet.
In the specific embodiment, the host 11 is connected to the host I/O port cache unit group 31, the host 12 is connected to the I/O port cache unit group 32, the host 13 is connected to the host I/O port cache unit group 33, and the host 14 is connected to the host I/O port cache unit group 34.
In a specific embodiment, the slave 21 is connected to the slave I/O port buffer unit group 41, the slave 22 is connected to the slave I/O port buffer unit group 42, the slave 23 is connected to the slave I/O port buffer unit group 43, and the slave 24 is connected to the slave I/O port buffer unit group 44.
In a specific embodiment, the cache unit group gives a ready signal of which the sending end is always set to be 1, and simultaneously receives a valid signal from the sending end;
in a specific embodiment, the host sends a valid signal to the host I/O port cache unit group, and the host I/O port cache unit group gives the ready signal that the host always sets 1; the slave machine sends a valid signal to the slave machine I/O port cache unit group, and the slave machine I/O port cache unit group gives a ready signal of the slave machine which is always set to be 1; a ready signal from a slave is directly transmitted to the master I/O port cache unit group without passing through the switch unit, and a ready signal from a master is directly transmitted to the slave I/O port cache unit group without passing through the switch unit; when the information packet from the host passes through the output port of the switching network, the output port of the switching network gives a 1-set valid signal to the slave, and when the information packet from the slave passes through the output port of the switching network, the output port of the switching network gives a 1-set valid signal to the host.
The host, the slave and the host I/O port cache unit group and the slave I/O port cache unit group cache the information packet from the sending end in the cache unit group through the sending and receiving of valid and ready signals, so that the sending end can continuously send data under the condition that the receiving end does not respond;
the receiving end gives a ready signal to the buffer unit group, and the switching network output port gives a valid signal to the receiving end, so that the information packet stored in the internal queue of the buffer unit can be successfully transmitted to the receiving end.
In a specific embodiment, each buffer unit has buffer queues with the same number as the master or slave devices, and the buffer queues respectively store the packets destined to different destinations from the same input port of the same channel, so as to prevent the occurrence of head-of-line blocking.
In a specific embodiment, the switching network is provided with a scheduler 7 for identifying the priority values of the storage queues and preferentially transmitting packets with longer delay, thereby meeting the requirements of low delay and high performance of the switching network.
In a specific embodiment, the signal bus 5 is a rready signal bus from the master, and the signal bus 6 is an awready, arrady signal bus from the slave.
Wherein, in particular, rready, break, awready, areready, wready are ready signals for five transmission channels of read data, write response, write address, read address and write data, respectively
In a specific embodiment, the switching unit may form a switching network that satisfies simultaneous transmission of N larger master devices and N slave devices.
Fig. 3 shows a specific configuration diagram inside banyan according to an embodiment of the present invention, 5 different channel protocols of AXI5-Lite can separate transmission information, and read address information, write address information, and write data information of any host can be transmitted from left to right without mutual influence, while reply data information, read data information of any slave can be transmitted from right to left without mutual influence.
In a specific embodiment, the number of the schedulers is 5, the schedulers respectively schedule information transmission of 5 different channels, and each scheduler of different types schedules information packet transmission of each different channel, so that data packet internal blocking occurs and transmission of other types of information packets is not affected, each channel information packet transmission is managed independently, different physical line transmission of a banyan network based on an AXI5-Lite protocol is occupied, and only when the information packets of the same type of channel are blocked, the schedulers are required to schedule, otherwise, the schedulers do not affect each other, so that data is transmitted smoothly by the transmission mode.
FIG. 4 illustrates an exemplary diagram of the components of a write and read data packet in accordance with one embodiment of the present invention, the beginning of the packet being a valid control bit that determines which of the immediately following control signals are valid data, and the interior of the control signals being capable of determining which of the immediately following data signals are valid data, and with the settings of the valid control bit, control signals and data signals, the data at the desired location being extracted from these signals, thereby reducing consumption.
In a specific embodiment, the valid control bits, control signals, and data signals are combined into a packet for parallel transmission from the output port
Fig. 5 shows an example diagram of AXI5-Lite protocol compatibility according to an embodiment of the present invention, where AXI5-Lite is directly compatible with AXI4-Lite, AXI5 and other interface protocols, and for AHB, APB and other protocols, only a simple interface protocol converter is required to be connected to meet the interface connection.
In a specific embodiment, data transmission is performed between two masters and two slaves, the transmission interface protocol of each device is different, and the same switching network based on the AXI5-Lite protocol is used for data transmission.
In a specific embodiment, the system comprises two hosts and two slaves, wherein the AXI4-Lite interface host 501 and the AXI interface slave 502 are directly connected with an AXI5-Lite protocol exchange network for data transmission.
In a specific embodiment, the AHB interface host 500 may directly access a switching network based on the AXI5-Lite protocol after using a protocol adapter 505 for converting the AHB protocol to the AXI5-Lite protocol.
In a specific embodiment, the APB interface slave 503 uses a protocol conversion interface 506 for converting AXI5-Lite protocol to APB protocol to interface with an AXI5-Lite protocol switching network, although each device is a different transmission protocol, it can transmit on the same protocol switching network, and it embodies the forward and backward compatibility of AXI5-Lite protocol.
Referring now to FIG. 6, shown is a block diagram of a computer system 600 suitable for use in implementing the electronic device of an embodiment of the present application. The electronic device shown in fig. 6 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.
As shown in fig. 6, the computer system 600 includes a Central Processing Unit (CPU)601 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM)602 or a program loaded from a storage section 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data necessary for the operation of the system 600 are also stored. The CPU 601, ROM 602, and RAM 603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
The following components are connected to the I/O interface 605: an input portion 606 including a keyboard, a mouse, and the like; an output portion 606 including a display such as a Liquid Crystal Display (LCD) and a speaker; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The driver 610 is also connected to the I/O interface 605 as needed. A removable medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 610 as necessary, so that a computer program read out therefrom is mounted in the storage section 608 as necessary.
In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable storage medium, the computer program containing program code for performing the method illustrated by the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network through the communication section 609, and/or installed from the removable medium 611. The computer program performs the above-described functions defined in the method of the present application when executed by a Central Processing Unit (CPU) 601. It should be noted that the computer readable storage medium described herein can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this application, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In this application, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable storage medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable storage medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The modules described in the embodiments of the present application may be implemented by software or hardware. The units described may also be provided in a processor, and the names of the units do not in some cases constitute a limitation of the unit itself.
Embodiments of the present invention also relate to a computer-readable storage medium having stored thereon a computer program which, when executed by a computer processor, implements the method above. The computer program comprises program code for performing the method illustrated in the flow chart. It should be noted that the computer readable medium of the present application can be a computer readable signal medium or a computer readable medium or any combination of the two.
The invention relates to a non-blocking banyan network meeting an AXI5-Lite protocol standard, which constructs a switching network meeting the AXI5-Lite protocol standard by using the banyan network, integrates network channel circuits in one switching unit, reduces the complexity of the switching network, respectively arranges a scheduler in 5 pairs of channels to realize the low-delay high performance of the switching network, a buffer unit has the capability of outputting and reading signals, avoids transmission blocking, a buffer queue in the buffer unit corresponds to the number of hosts and slaves, further reduces the blocking, arranges effective control signal bits, control signal bits and data signal bits for data information packets in transmission channels, ensures the convenience of reading the information packets, and ensures that the transmission bus width of each transmission channel is consistent with the length of the data information packets, so that the transmission can be completed at one time without excessive consumption. The switching network has a simpler structure and can be applied to the non-blocking transmission among various AMBA bus interface modules which require high performance, low delay and low network complexity.
The foregoing description is only exemplary of the preferred embodiments of the application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention herein disclosed is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the spirit of the invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (10)
1. A non-blocking banyan network that meets the AXI5-Lite protocol standard, comprising:
a plurality of switching units constituting a switching network, wherein each switching unit includes 5 pairs of dual transmission channels;
a set of host I/O port cache units disposed between the switch network and a host to cache packets from the host to be sent to the switch network, wherein each host I/O port cache unit in the set of host I/O port cache units has a plurality of host cache queues therein,
and the slave I/O port cache unit group is arranged between the switching network and the slaves to cache information packets from the slaves to be sent to the switching network, wherein each slave I/O port cache unit in the slave I/O port cache unit group is internally provided with a plurality of slave cache queues.
2. The non-blocking banyan network of claim 1, wherein the set of master I/O port cache units includes three types of cache units for read address packets, write address packets, and write data packets, respectively, and the set of slave I/O port cache units includes two types of cache units for read data packets and response packets, respectively.
3. The non-blocking banyan network of claim 1, wherein the set of master I/O port cache units accepts ready signals sent directly from slaves, and the set of slave I/O port cache units accepts ready signals sent directly from masters.
4. The non-blocking banyan network of claim 1, wherein the number of the plurality of master buffer queues is equal to the number of slaves connected to a switched network, and the number of the plurality of slave buffer queues is equal to the number of masters connected to the switched network.
5. The non-blocking banyan network of claim 2, wherein the 5 pairs of dual transfer channels comprise 5 pairs of dual transfer channels for write data, write address, read data, read address, and response, respectively.
6. The non-blocking banyan network of claim 5, wherein the banyan network further comprises 5 schedulers connected to the switching network, the 5 schedulers assigning priorities to packets pending transmission in the buffer queue for 5 pairs of dual transmission channels, respectively.
7. The non-blocking banyan network of claim 5, wherein for a channel of write addresses, a channel of read addresses, a data packet includes 7 bits of valid control signal bits and a control signal corresponding to the 7 bits of valid control signal bits;
and for the write response channel, the data information packet comprises 5 effective control signal bits and control signals corresponding to the 5 effective control signal bits.
8. The non-blocking banyan network of claim 7, wherein for a channel of write data and a channel of read data, the data packet includes 4 bits of valid control signal bits and control signals corresponding to the 4 bits of valid control signal bits, and the data packet further includes data signals, the data signals having valid data sizes determined by the corresponding control signals.
9. The non-blocking banyan network of claim 8, wherein each transmission channel of the 5 pairs of dual transmission channels has a transmission bus width that is consistent with a length of the data packets.
10. The non-blocking banyan network of any of claims 1-9, wherein the master I/O port cache unit group accepts a valid signal from the master to confirm whether the master is to send data, the master I/O port cache unit group giving a ready signal to master always set 1 so that data is directly transmitted into the master cache unit group, and the slave I/O port cache unit group accepting a valid signal from the slave to confirm whether the slave is to send data, the slave I/O port cache unit group giving a ready signal to slave always set 1 so that data is directly transmitted into the slave cache unit;
when the information packet is transmitted from the host to the slave, once the output port of the switching network detects that the information packet passes through, the output port of the switching network gives a valid signal of a channel corresponding to the information packet to the target slave;
when the information packet is transmitted from the slave to the master, once the output port of the switching network detects that the information packet passes through, the output port of the switching network gives a valid signal of a channel corresponding to the information packet to the target master.
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