CN114679415B - Non-blocking banyan network meeting AXI5-Lite protocol standard - Google Patents
Non-blocking banyan network meeting AXI5-Lite protocol standard Download PDFInfo
- Publication number
- CN114679415B CN114679415B CN202210491177.0A CN202210491177A CN114679415B CN 114679415 B CN114679415 B CN 114679415B CN 202210491177 A CN202210491177 A CN 202210491177A CN 114679415 B CN114679415 B CN 114679415B
- Authority
- CN
- China
- Prior art keywords
- slave
- data
- host
- port
- unit group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 240000003537 Ficus benghalensis Species 0.000 title claims abstract description 35
- 230000005540 biological transmission Effects 0.000 claims abstract description 73
- 230000000903 blocking effect Effects 0.000 claims abstract description 27
- 230000004044 response Effects 0.000 claims description 9
- 230000009977 dual effect Effects 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 18
- 238000004891 communication Methods 0.000 description 13
- 238000004590 computer program Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/325—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the network layer [OSI layer 3], e.g. X.25
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The disclosed non-blocking banyan network meeting AXI5-Lite protocol standard includes multiple switching units forming switching network, and 5 kinds of dual transmission channels without interference are set inside; a buffer unit group is correspondingly arranged at each input port of the switching network, and the buffer units of different numbers and different types are arranged in the buffer unit groups of the host and the slave and are used for receiving signals from the host and the slave, storing and transmitting information packets; the buffer unit is provided with a plurality of buffer queues, and the number of the buffer queues is the same as that of the receiving end; a scheduler is arranged in the dual transmission channel, and a priority is allocated to the information packets to be transmitted in the buffer queue; the data information package in the transmission channels is provided with effective control bits and subsequent data bits, and the transmission bus width of each transmission channel is consistent with the length of the data information package. The non-blocking banyan network meeting the AX I5-LIte protocol standard ensures non-blocking, high-performance and low-delay transmission of data resources and can reduce the complexity of the network.
Description
Technical Field
The application relates to the field of communication, in particular to a non-blocking banyan network meeting an AXI5-Lite protocol standard.
Background
Along with the continuous expansion of the communication demands on electronic devices, the requirements of various industries on the rate, delay and accuracy of resource data transmission are continuously improved, the performance of an electronic system is determined by the internet to a certain extent, and a good internet is required to meet the following requirements: on one hand, the method can enable all partial resources to be mobilized with high performance, low delay and no blocking, and on the other hand, the method can realize that the resources occupied by the Internet are not large.
Only when the switching network is matched with a proper communication protocol, each module can be efficiently linked, and meanwhile, the advantages of the switching network and the communication protocol are highlighted, so that how to design a good interconnection network through the matching of the switching network and the communication protocol becomes one of the important points of developing communication technology. The traditional switching network meeting the AXI protocol standard has the problems of high blocking rate, high network transmission delay and the like, and the network with low blocking rate such as crossbar, clos and the like can effectively transmit data, but has high complexity, and channels with different protocols are realized by using separate switching networks, so that the complexity of the switching network is higher, no blocking can be realized in effect, and even the situation of data packet loss can occur.
The AXI5-Lite bus has simpler structure, easier understanding of internal logic, easy modification and verification, and the AXI5-Lite allows variable data width transmission, can realize out-of-order transmission, can simplify communication transmission, and has strong compatibility. The banyan network is a representative network of the multistage interconnection network, and has the advantages of simple structure, small number of intermediate nodes, low network complexity and easy expansion.
Therefore, a new network structure is needed to combine the AXI5-Lite bus protocol with banyan networks, so that the network structure can be well applied to various transmission with high performance and low delay requirements, and high-efficiency transmission among all communication modules is ensured.
Disclosure of Invention
Aiming at the problems in the prior art, the application provides a non-blocking banyan network meeting the AXI5-Lite protocol standard, which comprises the following steps:
A plurality of switching units constituting a switching network, wherein each switching unit includes 5 pairs of dual transmission channels;
A host I/O port buffer unit group provided between the switching network and a host to buffer data packets from the host to be transmitted to the switching network, wherein each host I/O port buffer unit in the host I/O port buffer unit group has a plurality of host buffer queues inside,
A slave I/O port buffer unit set disposed between the switch network and a slave to buffer a data packet from the slave to be transmitted to the switch network, wherein each of the slave I/O port buffer units in the slave I/O port buffer unit set has a plurality of slave buffer queues therein.
The dual transmission channel can meet the data round trip transmission between a plurality of hosts and a plurality of slaves, and stores data which cannot be transmitted immediately by setting a host I/O port buffer unit group and a slave I/O port buffer unit group, so that the problem that banyan networks cannot simultaneously transmit information packets which are applied to be transmitted at each time to cause blocking is solved, a plurality of buffer queues are arranged in each buffer unit, and each buffer queue respectively stores the information packets which are transmitted to different destinations from the same input port of the same channel, thereby preventing the occurrence of line head blocking.
In an alternative embodiment, the host I/O port cache unit group includes three types of cache units for read address packets, write address packets, and write data packets, respectively, and the slave I/O port cache unit group includes two types of cache units for read data packets and response packets, respectively.
The arrangement mode of the buffer units in the host I/O port buffer unit group and the slave I/O port buffer unit group meets the communication requirements of the host and the slave, solves the problem that the efficiency is slow due to the fact that a plurality of different types of same-direction transmission information packets are transmitted by one network, and simultaneously greatly reduces the consumption of hardware.
In an alternative embodiment, the host I/O port cache unit group receives a ready signal sent directly from a slave, and the slave I/O port cache unit group receives a ready signal sent directly from a host.
The host I/O port buffer unit group and the slave I/O port buffer unit group can judge whether the slave and the host are still in an operation state or not through the received ready signal, and information packets are forbidden or allowed to be transmitted into the switching network according to the ready signal.
In an alternative embodiment, the number of the plurality of host cache queues is equal to the number of slaves connected to the switching network, and the number of the plurality of slave cache queues is equal to the number of hosts connected to the switching network.
The number of the buffer queues is the same as that of the externally connected hosts and slaves, so that the transmission efficiency of the information packet is greatly improved, and the blocking phenomenon is avoided.
In a further alternative embodiment, the 5 pairs of dual transmission channels include 5 pairs of dual transmission channels for writing data, writing address, reading data, reading address, and responding, respectively.
The 5 pairs of dual transmission channels in the switching unit are provided with 5 different channels corresponding to the AXI5-Lite protocol, and the advantages of the AXI protocol are exerted.
In a further alternative embodiment, the banyan networks further comprise 5 schedulers connected to the switching network, the 5 schedulers respectively assigning priorities to the packets to be transmitted in the buffer queue for 5 pairs of dual transmission channels.
The priority is allocated according to the delay of each storage queue head information packet and the storage data space left by the storage queue, the smaller the storage space left by the designated queue, the higher the priority is, the information packets stored in the storage queue head information packet should be transmitted preferentially, and the scheduling is performed by setting the priority, so that the switching network transmission achieves the effects of high performance and low delay.
In an alternative embodiment, for a channel of a write address and a channel of a read address, wherein the data packet includes 7 bits of valid control signal bits and a control signal corresponding to the valid control signal bits;
for the channel of write response, the data packet includes 5 bits of valid control signal bits and a control signal corresponding to the 5 bits of valid control signal bits.
In a further alternative embodiment, for a channel for writing data and a channel for reading data, the data packet includes 4 bits of valid control signal bits and a control signal corresponding to the 4 bits of valid control signal bits, the data packet further includes a data signal, and the size of the valid data of the data signal is determined by the corresponding control signal.
In an alternative embodiment, the control signal is consolidated with the data signal into one complete packet for transmission. Because each bit in the information packet corresponds to a signal with a fixed function, the information packet is only required to be transmitted to a corresponding receiving end interface according to bit separation when being output finally, and the control information is determined to be valid through valid control signal bits, and the data signals are determined to be valid according to the control signals.
The front end of each data information packet is provided with an effective control signal bit, and for 5 pairs of channels, the sum of the effective control signal bit and the control signal bit is different, and only the data information packet is written and read, so that the size of the information packet of each channel is different, and the receiving end is informed of which signals can be skipped directly through the arrangement of the effective control signal bit, thereby ensuring the convenience of information packet reading.
In an alternative embodiment, each transmission channel of the 5 pairs of dual transmission channels has a transmission bus width consistent with the length of the data packet, and the length of the data packet is longer and the transmission widths of the read data transmission channel and the write data transmission channel are correspondingly wider due to the presence of data signals in the read data packet and the write data packet.
After integration, the width of the information packet transmission bus of each channel in the banyan network is consistent with the length of the information packet, so that the parallel transmission of the information packets is ensured, and the one-time transmission can be completed.
In an alternative embodiment, the host I/O port cache unit receives a valid signal from the host to confirm whether the host is to send data, the host I/O port cache unit gives a ready signal that is always set to 1 to the host so that data is directly transferred to the host cache unit, and the slave I/O port cache unit receives a valid signal from the slave to confirm whether the slave is to send data, and the slave I/O port cache unit gives a ready signal that is always set to 1 to the slave so that data is directly transferred to the slave cache unit.
In an alternative embodiment, when the information packet is transmitted from the host to the slave, once the output port of the switching network detects that the information packet passes through, the output port of the switching network gives a valid signal of a channel corresponding to the information packet of the target slave;
when the information packet is transmitted from the slave to the host, once the output port of the switching network detects that the information packet passes through, the output port of the switching network gives a valid signal of a channel corresponding to the information packet of the target host.
In a further embodiment, the output port of the switching network reads the phase or result of the valid control signal bit to determine whether a packet passes, and if the phase or result of the valid control signal bit is 1 to determine that a packet passes, a valid signal of 1 is given to the receiving end.
The buffer unit group gives the ready signal of the sender always set 1, meanwhile, the buffer unit group receives the valid signal from the sender, when the valid signal bit of the transmission channel of the sender is 1, the buffer unit of the corresponding transmission channel knows that the channel sending equipment needs to send data, so that the buffer unit group directly processes and integrates the signal received from the sender into a message packet to be stored in an internal corresponding queue without considering the equipment state of the receiver, and the sender can continuously send data under the condition that the receiver does not respond.
When the ready signal of the receiving end is judged to be 1, the buffer unit accesses the information packet stored in the internal corresponding queue into the network input port, and once the information packet from the sending end in the internal corresponding queue is selected for transmission, the output port of the switching network gives the receiving end a valid signal with the 1 corresponding to the transmission channel of the information packet when the information packet passes through the output port of the switching network, so that the information packet stored in the internal queue of the buffer unit can be successfully transmitted to the receiving end. The invention provides a non-blocking banyan network meeting AXI5-Lite protocol standard, which comprises a plurality of switching units forming a switching network, wherein 5 non-interfering dual transmission channels are arranged in the switching units; each input port of the exchange unit is correspondingly provided with a buffer unit group, and the buffer unit groups are provided with buffer units with different numbers and different types for receiving signals from a host and a slave and storing and transmitting information packets, wherein the buffer units are provided with a plurality of buffer queues, and the number of the buffer queues is the same as that of the sending ends; a scheduler is arranged in the dual transmission channel, priorities are allocated to the to-be-transmitted information packets in the buffer queue, effective control bits and subsequent data bits are arranged on the data information packets in the transmission channel, and each transmission channel has a transmission total line width consistent with the length of the data information packets; the basic unit of banyan network is re-established, so that the consumption of hardware is greatly reduced. The invention ensures non-blocking, high-performance and low-delay transmission of data resources and can reduce the complexity of the network.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain the principles of the invention. Many of the intended advantages of other embodiments and embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
FIG. 1a shows a block diagram of a banyan basic switching unit according to one embodiment of the invention;
FIG. 1b shows a block diagram of a banyan modified exchange unit according to one embodiment of the invention;
FIG. 2 illustrates an exemplary schematic diagram of the operation of a switching network in accordance with one embodiment of the present invention;
FIG. 3 shows a detailed construction diagram of the interior banyan according to one embodiment of the invention;
FIG. 4 illustrates an exemplary diagram of write data, read data packet components in accordance with one embodiment of the present invention;
FIG. 5 shows an example diagram of AXI5-Lite protocol compatibility according to one embodiment of the present invention;
fig. 6 shows a schematic diagram of a computer system 600 of an electronic device according to an embodiment of the invention.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
Fig. 1a shows a diagram of a banyan basic switching unit according to one embodiment of the present invention, as shown in fig. 1a, in which packets may pass through switching units of the basic banyan network from 0 input port to 0 output port, from 0 input port to 1 output port, from 1 input port to 0 output port, from 1 input port to 1 output port, and may satisfy successful transmission of packets input from different input ports to different output ports.
However, the simple switching unit can only meet the transmission requirement of a unidirectional transmission channel, and if the AXI protocol is successfully transmitted, 5 common switching units are required to form a banyan network.
Fig. 1b shows a diagram of a banyan modified switching unit configuration, with 5 normal switching units clustered on one switching unit to satisfy 5 pairs of AXI channels of different direction and different properties, according to one embodiment of the invention. In a specific embodiment, the write data channel is set to transmit in a left-to-right direction, the input port is provided with an input port 0 and an input port 1, marked as W0 and W1 respectively, the output port is correspondingly provided with an output port 0 and an output port 1, marked as W '0 and W'1 respectively, the W0 can freely transmit the information packet to the right to W '0 or W'1, and the W1 can freely transmit the information packet to the right to W '0 or W'1;
the write address channel is set to transmit from left to right, the input port is provided with an input port 0 and an input port 1, which are respectively marked as AW0 and AW1, the output port is correspondingly provided with an output port 0 and an output port 1, which are respectively marked as AW '0 and AW'1, the AW0 can freely transmit information packets to the right to the AW '0 or AW'1, and the AW1 can freely transmit information packets to the right to the AW '0 or AW'1;
the read address channel is arranged to transmit in the left-to-right direction, the input port is provided with an input port 0 and an input port 1 which are respectively marked as AR0 and AR1, the output port is correspondingly provided with an output port 0 and an output port 1 which are respectively marked as AR '0 and AR'1, the AR0 can freely transmit the information packet to the right to the AR '0 or AR'1, and the AR1 can freely transmit the information packet to the right to the AR '0 or AR'1;
The read data channel is arranged to transmit in the right-to-left direction, the input port is provided with an input port 0 and an input port 1 which are respectively marked as R0 and R1, the output port is correspondingly provided with an output port 0 and an output port 1 which are marked as R '0 and R'1, the R0 can freely transmit the information packet to the left to the R '0 or the R'1, and the R1 can freely transmit the information packet to the left to the R '0 or the R'1;
The write response channel is set to transmit from right to left, the input port is provided with an input port 0 and an input port 1, which are respectively marked as Res0 and Res1, the output port is correspondingly provided with an output port 0 and an output port 1, which are marked as Res '0 and Res'1, res0 can freely transmit information packets to the left to Res '0 or Res'1, and Res1 can freely transmit information packets to the left to Res '0 or Res'1;
five pairs of dual transmission channels are mutually noninterfere via one switching unit, and compared with banyan switching network composed of common switching units, five switching units are needed, and the switching units shown in fig. 1b greatly reduce the consumption of hardware.
Fig. 2 shows a schematic diagram of an example of the operation of a switching network according to an embodiment of the present invention, where 4 host devices and 4 slave devices exchange data with one AXI5-Lite protocol banyan-based switching network, and the 4 host devices are host 11, host 12, host 13 and host 14, and the 4 slave devices are slave 21, slave 22, slave 23 and slave 24, respectively, as shown in fig. 1.
In a specific embodiment, the master device is directly connected to a port corresponding to a transport channel of the switching network when the slave device is the receiving end.
In a specific embodiment, when the host device and the slave device are used as the sending ends, a host I/O port cache unit group and a slave I/O port cache unit group are provided at the input port, which are respectively a host I/O port cache unit group 31, a host I/O port cache unit group 32, a host I/O port cache unit group 33, a host I/O port cache unit group 34, a slave I/O port cache unit group 41, a slave I/O port cache unit group 42, a slave I/O port cache unit group 43, and a slave I/O port cache unit group 44.
In a specific embodiment, since there are 3 AXI channels from the host to the slave, the host I/O port cache unit group includes 3 different cache units for storing read address, write address, and write data packets, respectively.
In a specific embodiment, since there are two AXI channels from the slave to the host and the transmission is from right to left, the slave I/O port buffer unit group includes 2 different buffer units, and stores the response packet and the read data packet respectively.
In a specific embodiment, host 11 is coupled to host I/O port cache block 31, host 12 is coupled to I/O port cache block 32, host 13 is coupled to host I/O port cache block 33, and host 14 is coupled to host I/O port cache block 34.
In a specific embodiment, the slave 21 is connected to a slave I/O port cache unit group 41, the slave 22 is connected to a slave I/O port cache unit group 42, the slave 23 is connected to a slave I/O port cache unit group 43, and the slave 24 is connected to a slave I/O port cache unit group 44.
In a specific embodiment, the cache unit group gives a ready signal that is always set to 1 to the transmitting end, and the cache unit group receives a valid signal from the transmitting end;
In a specific embodiment, the host sends a valid signal to the host I/O port cache unit group, which gives the host a ready signal that is always set to 1; the slave sends valid signals to the slave I/O port cache unit group, and the slave I/O port cache unit group gives ready signals of the slave always set 1; the ready signal from the slave is sent directly to the set of host I/O port cache units without via the switch unit, and the ready signal from the master is sent directly to the set of slave I/O port cache units without via the switch unit; when the information packet from the host passes through the switch network outlet, the switch network outlet gives the slave a 1-set vaild signal, and when the information packet from the slave passes through the switch network outlet, the switch network outlet gives the host a 1-set valid signal.
The host, the slave and the host I/O port cache unit group and the slave I/O port cache unit group are transmitted and received through valid and ready signals, and information packets from the transmitting end are cached in the cache unit group, so that the transmitting end can continuously transmit data under the condition that the receiving end does not respond;
the receiving end gives a ready signal to the buffer unit group, and the switching network output port gives a valid signal to the receiving end, so that the information packet stored in the internal queue of the buffer unit can be successfully transmitted to the receiving end.
In a specific embodiment, each buffer unit has the same number of buffer queues as the host or slave device, and packets of the same channel and the same input port and going to different destinations are stored respectively, so that the occurrence of line head blocking is prevented.
In a specific embodiment, the switching network is provided with a scheduler 7 for identifying the storage queue priority value and for preferentially transmitting the packets with longer delay, so as to meet the requirements of low delay and high performance of the switching network.
In a specific embodiment, signal bus 5 is a rready, bready signal bus from a host and signal bus 6 is a awready, arready, wready signal bus from a slave.
Wherein rready, bready, awready, arready, wready is specifically a ready signal prepared for five transmission channels of read data, write response, write address, read address and write data
In a particular embodiment, the switching units may form a switching network that satisfies the simultaneous transmissions of the larger N master devices and N slave devices.
FIG. 3 is a diagram showing a specific architecture within banyan according to one embodiment of the present invention, in which the 5 different channel protocols of AXI5-Lite may separate transmissions of information, the transmissions of read address information, write data information from left to right of any host may be mutually exclusive, and the transmissions of response data information and read data information from right to left of any slave may be mutually exclusive.
In a specific embodiment, the number of schedulers is 5, and the schedulers schedule information transmissions of 5 different channels respectively, and each different kind of scheduler schedules information packet transmissions of each different channel, so that the inside of a write data information packet is blocked, the transmission of other kinds of information packets is not influenced, the information packet transmissions of each channel are independently managed, and the transmission of different physical lines of banyan networks based on the AXI5-Lite protocol is occupied, and the schedulers are required to schedule only when the information packets of the same channel are blocked, otherwise, the transmission modes are not influenced mutually, so that data are smoothly transmitted.
Fig. 4 shows an exemplary diagram of the write data and read data packet components according to one embodiment of the invention, the beginning of the packet being the valid control signal bits, which determine which of the following control signals are valid data, which control signals can in turn determine which of the following data signals are valid data, by means of the arrangement of the valid control signal bits, the control signals and the data signals, the data of the desired location is extracted from these signals, thus reducing the consumption.
In a specific embodiment, the valid control signal bits, control signals, and data signals are integrated into one packet for parallel transmission from the output port
Fig. 5 shows an example diagram of AXI5-Lite protocol compatibility, where AXI5-Lite can directly compatible with AXI4-Lite, AXI5, etc. interface protocols, and connection of interfaces can be satisfied by only connecting a simple interface protocol converter to an AHB, APB, etc. protocol according to an embodiment of the present invention.
In a specific embodiment, data transmission is performed between two hosts and two slaves, the transmission interface protocol of each device is different, and the same exchange network based on the AXI5-Lite protocol is used for data transmission.
In a specific embodiment, two hosts and two slaves are included, and an AXI4-Lite interface host 501 and an AXI interface slave 502 are directly connected to an AXI5-Lite protocol exchange network for data transmission.
In a specific embodiment, the AHB interface host 500 may directly access the AXI5-Lite protocol-based switching network after using a protocol conversion interface 505 for converting the AHB protocol to the AXI5-Lite protocol.
In a specific embodiment, the APB interface slave 503 uses a protocol conversion interface 506 for converting the AXI5-Lite protocol to the APB protocol to connect to the AXI5-Lite protocol exchange network, and although each device is a different transmission protocol, it can transmit on the exchange network of the same protocol, which reflects the forward-backward compatibility of the AXI5-Lite protocol.
Referring now to FIG. 6, there is illustrated a schematic diagram of a computer system 600 suitable for use in implementing an electronic device of an embodiment of the present application. The electronic device shown in fig. 6 is only an example and should not be construed as limiting the functionality and scope of use of the embodiments of the application.
As shown in fig. 6, the computer system 600 includes a Central Processing Unit (CPU) 601, which can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage section 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the system 600 are also stored. The CPU 601, ROM 602, and RAM 603 are connected to each other through a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
The following components are connected to the I/O interface 605: an input portion 606 including a keyboard, mouse, etc.; an output portion 606 including a display such as a Liquid Crystal Display (LCD) and a speaker; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The drive 610 is also connected to the I/O interface 605 as needed. Removable media 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed as needed on drive 610 so that a computer program read therefrom is installed as needed into storage section 608.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable storage medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network through the communication portion 609, and/or installed from the removable medium 611. The above-described functions defined in the method of the present application are performed when the computer program is executed by a Central Processing Unit (CPU) 601. The computer readable storage medium according to the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable storage medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable storage medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The modules involved in the embodiments of the present application may be implemented in software or in hardware. The units described may also be provided in a processor, and the names of these units do not in some case constitute a limitation of the unit itself.
Embodiments of the present application also relate to a computer readable storage medium having stored thereon a computer program which, when executed by a computer processor, implements the method as described above. The computer program contains program code for performing the method shown in the flow chart. The computer readable medium of the present application may be a computer readable signal medium or a computer readable medium, or any combination of the two.
The invention discloses a non-blocking banyan network meeting AXI5-Lite protocol standard, which uses banyan network to construct a switching network meeting AXI5-Lite protocol standard, sets network channel lines in a switching unit, reduces complexity of the switching network, sets a scheduler in 5 pairs of channels respectively, realizes low delay and high performance of the switching network, has capability of outputting and reading signals, avoids transmission blocking, and has buffer queues in the buffer units corresponding to the number of hosts and slaves, so that blocking is further reduced, data information packets in the transmission channels are provided with effective control signal bits and data signal bits, convenience of information packet reading is ensured, and transmission bus width of each transmission channel is consistent with the length of the data information packet, so that transmission can be completed once and is not excessively consumed. The switching network structure of the invention is simpler, and can be applied to non-blocking transmission among various AMBA bus interface modules with high performance, low delay and low network complexity.
The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the application referred to in the present application is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept described above. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.
Claims (8)
1. A non-blocking banyan network that meets AXI5-Lite protocol standards, comprising:
A plurality of switching units forming a switching network, wherein each switching unit is provided with 5 common switching units in an integrated manner to meet 5 pairs of AXI channels with different attributes in different directions, and each transmission channel in the 5 pairs of AXI channels with different attributes in different directions has a transmission bus width consistent with the length of a data information packet;
A host I/O port buffer unit group provided between the switching network and a host to buffer a packet from the host to be transmitted to the switching network, wherein each host I/O port buffer unit in the host I/O port buffer unit group has a plurality of host buffer queues inside,
A slave I/O port buffer unit group provided between the switching network and a slave to buffer a packet from the slave to be transmitted to the switching network, wherein each of the slave I/O port buffer units in the slave I/O port buffer unit group has a plurality of slave buffer queues inside, wherein the master I/O port buffer unit group receives a valid signal from the master to confirm whether the master is to transmit data, the master I/O port buffer unit group gives a ready signal always set to 1 to the master so that the data is directly transmitted into the master buffer unit group, and the slave I/O port buffer unit group receives a valid signal from the slave to confirm whether the slave is to transmit data, and the slave I/O port buffer unit group gives a ready signal always set to 1 to the slave so that the data is directly transmitted into the slave buffer unit;
when an information packet is transmitted from a host to a slave, once an output port of a switching network detects that the information packet passes, the output port of the switching network gives a valid signal of a channel corresponding to the information packet to the target slave;
when the information packet is transmitted from the slave to the host, once the output port of the switching network detects that the information packet passes, the output port of the switching network gives the valid signal of the channel corresponding to the information packet to the target host.
2. The non-blocking banyan network of claim 1, wherein the master I/O port cache unit group includes three types of cache units for read address packets, write address packets, and write data packets, respectively, and the slave I/O port cache unit group includes two types of cache units for read data packets and response packets, respectively.
3. The non-blocking banyan network of claim 1, wherein the master I/O port cache unit group receives a ready signal sent directly from a slave and the slave I/O port cache unit group receives a ready signal sent directly from a master.
4. The non-blocking banyan network of claim 1, wherein the number of the plurality of master cache queues is equal to the number of slaves connected to the switching network, and the number of the plurality of slave cache queues is equal to the number of masters connected to the switching network.
5. The non-blocking banyan network of claim 2, wherein the 5 pairs of different-direction different-attribute AXI channels include 5 pairs of AXI channels for write data, write address, read data, read address, and response, respectively.
6. The non-blocking banyan network according to claim 5, wherein the banyan network further comprises 5 schedulers connected to the switching network, the 5 schedulers assigning priorities to packets to be transmitted in the cache queue for 5 pairs of AXI channels of different direction and different properties, respectively.
7. The non-blocking banyan network according to claim 5, wherein for a channel of a write address, a channel of a read address, a data packet includes 7 bits of valid control signal bits and a control signal corresponding to the 7 bits of valid control signal bits;
for the channel of the write response, the data information packet comprises 5 bits of valid control signal bits and a control signal corresponding to the 5 bits of valid control signal bits.
8. The non-blocking banyan network according to claim 7, wherein for a channel to write data and a channel to read data, the data packet includes 4 valid control signal bits and a control signal corresponding to the 4 valid control signal bits, the data packet further includes a data signal, and the size of the valid data of the data signal is determined by the corresponding control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210491177.0A CN114679415B (en) | 2022-05-07 | 2022-05-07 | Non-blocking banyan network meeting AXI5-Lite protocol standard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210491177.0A CN114679415B (en) | 2022-05-07 | 2022-05-07 | Non-blocking banyan network meeting AXI5-Lite protocol standard |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114679415A CN114679415A (en) | 2022-06-28 |
| CN114679415B true CN114679415B (en) | 2024-05-28 |
Family
ID=82079354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210491177.0A Active CN114679415B (en) | 2022-05-07 | 2022-05-07 | Non-blocking banyan network meeting AXI5-Lite protocol standard |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114679415B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115242729B (en) * | 2022-09-22 | 2022-11-25 | 沐曦集成电路(上海)有限公司 | Cache query system based on multiple priorities |
| CN117880364B (en) * | 2024-03-12 | 2024-06-11 | 苏州仰思坪半导体有限公司 | Data transmission method, system and related device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101938405A (en) * | 2009-07-01 | 2011-01-05 | 中兴通讯股份有限公司 | Multi-protocol label switching-based data transmitting/receiving method, device and system |
| CN105005546A (en) * | 2015-06-23 | 2015-10-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Asynchronous AXI bus structure with built-in cross point queue |
| CN107070795A (en) * | 2016-01-14 | 2017-08-18 | 赛灵思公司 | Channel selecting in multichannel exchange network |
| US10601635B1 (en) * | 2004-04-16 | 2020-03-24 | EMC IP Holding Company LLC | Apparatus, system, and method for wireless management of a distributed computer system |
| CN112073336A (en) * | 2020-08-21 | 2020-12-11 | 西安电子科技大学 | High-performance data exchange system and method based on AXI4Stream interface protocol |
| CN114090250A (en) * | 2021-11-22 | 2022-02-25 | 厦门大学 | EDA hardware acceleration method and system based on Banyan network and multi-FPGA structure |
| CN114153775A (en) * | 2021-12-10 | 2022-03-08 | 中国兵器工业集团第二一四研究所苏州研发中心 | FlexRay controller based on AXI bus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010055299A1 (en) * | 1996-08-16 | 2001-12-27 | Keith C. Kelly | Method and apparatus for establishing communications between packet-switched and circuit-switched networks |
| US10326448B2 (en) * | 2013-11-15 | 2019-06-18 | Scientific Concepts International Corporation | Code partitioning for the array of devices |
-
2022
- 2022-05-07 CN CN202210491177.0A patent/CN114679415B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10601635B1 (en) * | 2004-04-16 | 2020-03-24 | EMC IP Holding Company LLC | Apparatus, system, and method for wireless management of a distributed computer system |
| CN101938405A (en) * | 2009-07-01 | 2011-01-05 | 中兴通讯股份有限公司 | Multi-protocol label switching-based data transmitting/receiving method, device and system |
| CN105005546A (en) * | 2015-06-23 | 2015-10-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Asynchronous AXI bus structure with built-in cross point queue |
| CN107070795A (en) * | 2016-01-14 | 2017-08-18 | 赛灵思公司 | Channel selecting in multichannel exchange network |
| CN112073336A (en) * | 2020-08-21 | 2020-12-11 | 西安电子科技大学 | High-performance data exchange system and method based on AXI4Stream interface protocol |
| CN114090250A (en) * | 2021-11-22 | 2022-02-25 | 厦门大学 | EDA hardware acceleration method and system based on Banyan network and multi-FPGA structure |
| CN114153775A (en) * | 2021-12-10 | 2022-03-08 | 中国兵器工业集团第二一四研究所苏州研发中心 | FlexRay controller based on AXI bus |
Non-Patent Citations (1)
| Title |
|---|
| 多维交换网络中的一种流量控制机制;刘同;许都;苏清博;江果;;微计算机信息;第24卷(第06期);第113-115页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114679415A (en) | 2022-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114679415B (en) | Non-blocking banyan network meeting AXI5-Lite protocol standard | |
| US8718065B2 (en) | Transmission using multiple physical interface | |
| KR100666515B1 (en) | Store and forward switch device, system and method | |
| US7924708B2 (en) | Method and apparatus for flow control initialization | |
| US8234435B2 (en) | Relay device | |
| US6877048B2 (en) | Dynamic memory allocation between inbound and outbound buffers in a protocol handler | |
| US7352765B2 (en) | Packet switching fabric having a segmented ring with token based resource control protocol and output queuing control | |
| US9854072B1 (en) | Script-controlled egress packet modifier | |
| JP5552196B2 (en) | RELAY DEVICE, RELAY DEVICE CONTROL METHOD, AND COMPUTER PROGRAM | |
| JPH09223089A (en) | Method and device for making packet data difusable to plural bus targets | |
| CN108702325A (en) | Enhance the communication of network service | |
| US20150135196A1 (en) | Method For Enabling A Communication Between Processes, Processing System, Integrated Chip And Module For Such A Chip | |
| JPS611146A (en) | Information communication equipment | |
| JP4255833B2 (en) | Tagging and arbitration mechanisms at the input / output nodes of computer systems | |
| US20120263181A1 (en) | System and method for split ring first in first out buffer memory with priority | |
| US7209489B1 (en) | Arrangement in a channel adapter for servicing work notifications based on link layer virtual lane processing | |
| EP1193914A2 (en) | Data transmission and reception | |
| JP4391819B2 (en) | I / O node of computer system | |
| US7643502B2 (en) | Method and apparatus to perform frame coalescing | |
| CN115955441A (en) | Management scheduling method and device based on TSN queue | |
| RU175049U9 (en) | COMMUNICATION INTERFACE DEVICE SpaceWire | |
| JP7456603B2 (en) | switch device | |
| JP2007325178A (en) | Packet processing system, packet processing method and program | |
| US6857033B1 (en) | I/O node for a computer system including an integrated graphics engine and an integrated I/O hub | |
| JP6206497B2 (en) | Data transfer apparatus and data transfer method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |