CN101375379B - 具有应力器的半导体器件及其形成方法 - Google Patents

具有应力器的半导体器件及其形成方法 Download PDF

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Publication number
CN101375379B
CN101375379B CN2006800472576A CN200680047257A CN101375379B CN 101375379 B CN101375379 B CN 101375379B CN 2006800472576 A CN2006800472576 A CN 2006800472576A CN 200680047257 A CN200680047257 A CN 200680047257A CN 101375379 B CN101375379 B CN 101375379B
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China
Prior art keywords
stressor
compressive
tensile
integrated circuit
stressors
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Expired - Fee Related
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CN2006800472576A
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English (en)
Chinese (zh)
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CN101375379A (zh
Inventor
梅于尔·D·施罗夫
保罗·A·格吕多斯基
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
CN2006800472576A 2005-12-14 2006-11-08 具有应力器的半导体器件及其形成方法 Expired - Fee Related CN101375379B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/300,091 2005-12-14
US11/300,091 US7511360B2 (en) 2005-12-14 2005-12-14 Semiconductor device having stressors and method for forming
PCT/US2006/060638 WO2007097814A2 (en) 2005-12-14 2006-11-08 Semiconductor device having stressors and method for forming

Publications (2)

Publication Number Publication Date
CN101375379A CN101375379A (zh) 2009-02-25
CN101375379B true CN101375379B (zh) 2010-09-01

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US (1) US7511360B2 (https=)
JP (1) JP5323493B2 (https=)
CN (1) CN101375379B (https=)
WO (1) WO2007097814A2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7420202B2 (en) * 2005-11-08 2008-09-02 Freescale Semiconductor, Inc. Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device
JP4764160B2 (ja) * 2005-12-21 2011-08-31 株式会社東芝 半導体装置
JP4760414B2 (ja) * 2006-02-06 2011-08-31 ソニー株式会社 半導体装置の製造方法
JP4899085B2 (ja) * 2006-03-03 2012-03-21 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US8569858B2 (en) * 2006-12-20 2013-10-29 Freescale Semiconductor, Inc. Semiconductor device including an active region and two layers having different stress characteristics
US7843011B2 (en) * 2007-01-31 2010-11-30 Freescale Semiconductor, Inc. Electronic device including insulating layers having different strains
US7799678B2 (en) 2008-01-30 2010-09-21 Freescale Semiconductor, Inc. Method for forming a through silicon via layout
JP2009188330A (ja) * 2008-02-08 2009-08-20 Fujitsu Microelectronics Ltd 半導体装置およびその製造方法
US8122394B2 (en) * 2008-09-17 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Performance-aware logic operations for generating masks
US9564506B2 (en) 2015-01-06 2017-02-07 International Business Machines Corporation Low end parasitic capacitance FinFET

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5591494A (en) * 1993-09-24 1997-01-07 Applied Materials, Inc. Deposition of silicon nitrides by plasma-enhanced chemical vapor deposition
US5707486A (en) * 1990-07-31 1998-01-13 Applied Materials, Inc. Plasma reactor using UHF/VHF and RF triode source, and process
CN1449585A (zh) * 2000-11-22 2003-10-15 株式会社日立制作所 半导体器件及其制造方法
CN1499634A (zh) * 2002-11-04 2004-05-26 台湾积体电路制造股份有限公司 Cmos元件及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4173672B2 (ja) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP2004023047A (ja) * 2002-06-20 2004-01-22 Renesas Technology Corp 半導体装置
US6674146B1 (en) * 2002-08-08 2004-01-06 Intel Corporation Composite dielectric layers
US6870179B2 (en) * 2003-03-31 2005-03-22 Intel Corporation Increasing stress-enhanced drive current in a MOS transistor
JP2005322730A (ja) * 2004-05-07 2005-11-17 Renesas Technology Corp 半導体装置及びその製造方法
US7514752B2 (en) * 2005-08-26 2009-04-07 Toshiba America Electronic Components, Inc. Reduction of short-circuiting between contacts at or near a tensile-compressive boundary
US7297584B2 (en) * 2005-10-07 2007-11-20 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having a dual stress liner

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5707486A (en) * 1990-07-31 1998-01-13 Applied Materials, Inc. Plasma reactor using UHF/VHF and RF triode source, and process
US5591494A (en) * 1993-09-24 1997-01-07 Applied Materials, Inc. Deposition of silicon nitrides by plasma-enhanced chemical vapor deposition
CN1449585A (zh) * 2000-11-22 2003-10-15 株式会社日立制作所 半导体器件及其制造方法
CN1499634A (zh) * 2002-11-04 2004-05-26 台湾积体电路制造股份有限公司 Cmos元件及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
US 5591494 A,全文.

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Publication number Publication date
US20070132031A1 (en) 2007-06-14
CN101375379A (zh) 2009-02-25
WO2007097814A2 (en) 2007-08-30
JP5323493B2 (ja) 2013-10-23
US7511360B2 (en) 2009-03-31
JP2009520363A (ja) 2009-05-21
WO2007097814A3 (en) 2008-10-09

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