CN101364593A - Staggered offset stacking encapsulation construction having multistage omnibus bar in conductive wire support - Google Patents

Staggered offset stacking encapsulation construction having multistage omnibus bar in conductive wire support Download PDF

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Publication number
CN101364593A
CN101364593A CNA2007101432981A CN200710143298A CN101364593A CN 101364593 A CN101364593 A CN 101364593A CN A2007101432981 A CNA2007101432981 A CN A2007101432981A CN 200710143298 A CN200710143298 A CN 200710143298A CN 101364593 A CN101364593 A CN 101364593A
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chip
chips
weld pads
stacked structure
lead frame
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CNA2007101432981A
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CN101364593B (en
Inventor
陈煜仁
沈更新
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

The invention provides an encapsulated structure which is provided with a multisection type bus bar and stacked in a staggered manner in a lead frame. The encapsulated structure comprises the lead frame which is composed of a plurality of oppositely arranged inner pin groups, a plurality of outer pin groups and a chip support plate, wherein, the chip support plate is disposed among the plurality of oppositely arranged inner pin groups, therefore, a height difference is produced between the plurality of oppositely arranged inner pin group and the chip support plate; a stack-type chip device is formed by stacking a plurality of chips, and disposed on the chip support plate; the plurality of chips are electrically connected with the plurality of oppositely arranged inner pin groups; and the encapsulating body is used for wrapping the stack-type chip device and the lead frame, wherein the lead frame includes at least a bus bar which is disposed between the plurality of oppositely arranged inner pin groups and the chip support plate, and formed in the manner of multiple sections.

Description

The staggered offset stacking encapsulation construction that has multi-section bus bar in the lead frame
Technical field
The present invention relates to a kind of multi-chip interleaving offset stacking encapsulation construction, particularly relevant for a kind of multi-chip stacking encapsulating structure with staggered offset (zigzag) stacking construction.
Background technology
In recent years, semi-conductive back-end process is all carrying out three-dimensional space (Three Dimension; Encapsulation 3D) reaches big relatively semiconductor integrated level (Integrated) or capacity of internal memory etc. in the hope of utilizing minimum area.In order to reach this purpose, the mode that present stage has been developed use chip-stacked (chip stacked) is reached three-dimensional space (ThreeDimension; Encapsulation 3D).
In the prior art, the stack manner of chip is that a plurality of chips are stacked on the substrate mutually, uses the processing procedure (wire bonding process) of routing that a plurality of chips are connected with substrate then.Figure 1A is the existing the generalized section identical or stack chip packaging structure of close chip size that has.Shown in Figure 1A, existing stack chip packaging structure comprises a circuit substrate (package substrate) 110, chip 120a, chip 120b, a sept (spacer) 130, many leads 140 and a packing colloid (encapsulant) 150.Have a plurality of weld pads 112 on the circuit substrate 110, and also have a plurality of weld pad 122a and 122b respectively on chip 120a and the 120b, wherein weld pad 122a and 122b are arranged on chip 120a and the 120b with kenel (peripheral type) on every side.Chip 120a is disposed on the circuit substrate 110, and chip 120b is disposed at the top of chip 120a via sept 130.The two ends of lead 140 are to be connected to weld pad 112 and 122a via the routing processing procedure, so that chip 120a is electrically connected at circuit substrate 110.And the two ends of other parts lead 140 also are connected to weld pad 112 and 122b via the routing processing procedure, so that chip 120b is electrically connected at circuit substrate 110.Be disposed on the circuit substrate 110 as for 150 of packing colloids, and coat these leads 140, chip 120a and 120b.
Because weld pad 122a and 122b are arranged on chip 120a and the 120b with kenel on every side, therefore the direct carries chips 120b of chip 120a, so prior art must be between chip 120a and 120b configuration space thing 130, make between chip 120a and the 120b at a distance of a suitable distance, in order to the carrying out of follow-up routing processing procedure.Yet the use of sept 130 but causes the thickness of existing stack chip packaging structure 100 to reduce further easily.
In addition, prior art proposes another kind of stack chip packaging structure with different chip sizes, and its generalized section is shown in Figure 1B.Please refer to Figure 1B, existing stack chip packaging structure 10 comprises a circuit substrate 110, chip 120c, chip 120d, many leads 140 and a packing colloid 150.Have a plurality of weld pads 112 on the circuit substrate 110.The size of chip 120c is the size greater than chip 120d, and also has a plurality of weld pad 122c and 122d respectively on chip 120c and the 120d, and wherein weld pad 122c and 122d are arranged on chip 120c and the 120d with kenel (peripheral type) on every side.Chip 120c is disposed on the circuit substrate 110, and chip 120d is disposed at the top of chip 120c.The two ends of part lead 140 are to be connected to weld pad 112 and 122c via routing processing procedure (wire bondingprocess), so that chip 120c is electrically connected at circuit substrate 110.And the two ends of other parts lead 140 also are connected to weld pad 112 and 122d via the routing processing procedure, so that chip 120d is electrically connected at circuit substrate 110.Be disposed on the circuit substrate 110 as for 150 of packing colloids, and coat these leads 140, chip 120c and 120d.
Because chip 120d is less than chip 120c, therefore when chip 120d was disposed on the chip 120c, chip 120d can not cover the weld pad 122c of chip 120c.But when prior art piles up stack chip packaging structure 10 with the chip of a plurality of different size sizes in above-mentioned mode, because the chip size on upper strata must be more little more, so stack chip packaging structure 10 has the restriction of piling up quantity of chip.
In above-mentioned two kinds of stack manners, Figure 1A uses the mode of sept 130, the shortcoming that causes the thickness of stack chip packaging structure 100 to reduce further easily; And Figure 1B because the chip size on upper strata must be more little more, so can produce the problem that chip can be restricted when design or use.No. the 6252305th, United States Patent (USP), No. the 6359340th, United States Patent (USP) and United States Patent (USP) then provide the structure of another kind of multi-chip stacking encapsulation for No. 6461897, shown in Fig. 1 C, this stacked structure can use measure-alike chip, and does not need to use sept 130 to form connection.Yet, these chips are in the process of piling up, to pile up alternately and must use weld pad configuration more than 2 kinds at least in order to form, for example the weld pad on certain first chip is to be configured on first chip, one side, and the weld pad on another second chip then is to be configured on the two adjacent sides; In addition, this structure also must connect (wire bonding) at the routing of the enterprising row metal lead of both direction.Therefore, in the structure of Fig. 1 C, except the time that might increase the routing processing procedure, in the process of carrying out sealing, might cause the inhomogeneous of mould stream and cause defective, and the plain conductor that may cause a certain direction is subjected to horizontal mould stream and impacts strength, causes the plain conductor contact and produces the problem of chip failure.
In addition, United States Patent (USP) US6900528 number, US publication US20030137042A1, US20050029645A1 and US20060267173A1 then provide the structure of another kind of multi-chip stacking encapsulation, shown in Fig. 1 D.Fig. 1 D discloses a kind of encapsulating structure that piles up alternately, clearly, it utilizes the height of chip chamber to replace sept, make the density of encapsulation to increase, but still there is the trouble on the processing procedure in this kind encapsulating structure, after must finishing the connection of two chips earlier exactly, carry out after primary plain conductor connects, just can carry out the connection of two other chip after, carry out secondary plain conductor again and connect, so when number of chips the more the time, processing procedure is with regard to relative complex and difficulty.
Summary of the invention
Because the shortcoming and the problem of the chip-stacked mode described in the background of invention the present invention seeks to, a kind of mode of using the multi-chip interleaving offset stacked is provided, the akin chip staggered offset of a plurality of sizes is stacked into a kind of tridimensional encapsulating structure.
Main purpose of the present invention provides a kind of multi-chip interleaving offset stacked encapsulation, makes it have higher encapsulation integration and thin thickness.
Another main purpose of the present invention provides a kind of structure that disposes multi-section bus bar in lead frame and carries out the encapsulation of multi-chip interleaving offset stacked, makes it in the sealing process, has the mould stream effect than balance.
Dispose a busbar in the encapsulating structure that also has a main purpose to provide a kind of multi-chip interleaving offset stacked of the present invention, make it have preferable circuit design elasticity and better reliability degree.
A main purpose more of the present invention provides a kind of encapsulating structure of multi-chip interleaving offset stacked, and it can be reshuffled layer by one the pad on the chip is reconfigured on the side of chip, makes it can simplify the processing procedure of encapsulation.
A main purpose more of the present invention provides a kind of encapsulating structure of multi-chip interleaving offset stacked, and it can be finished a plurality of chips that staggered offset piles up and with after substrate is connected, carry out the routing processing procedure again, so also can further simplify the processing procedure of encapsulation.
In view of the above, the invention provides a kind of multi-chip migration stack package structure that disposes busbar in lead frame, comprise: the lead frame that the interior pin group by a plurality of relative arrangements, a plurality of outer pin group and a chip bearing are formed, its chips bearing is to be disposed between the interior pin group of a plurality of relative arrangements, and forms a difference in height with the interior pin group of a plurality of relative arrangements; One multi-chip interleaving offset stacked structure, be to be fixed on the chip bearing, multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active surface of each first chip on a side near configuration and exposing also dispose near another side on the active surface of a plurality of weld pads and each second chip and expose a plurality of weld pads with respect to a plurality of exposure weld pads of first chip, wherein a plurality of first chips of multi-chip interleaving offset stacked structure and a plurality of second chip are by the interior pin group electric connection of the relative arrangement with a plurality of one-tenth of most strip metal leads; One packaging body coats multi-chip interleaving offset stacked structure and lead frame, a plurality of outer pins are to stretch out in packaging body to reach lead frame outward; Wherein comprising at least one busbar in the lead frame, is to be disposed between the interior pin group of a plurality of relative arrangements and the chip bearing and busbar is to form in a multisection type mode.
The present invention then provides a kind of multi-chip migration stack package structure that disposes busbar in lead frame again, comprise: the lead frame of being formed by the interior pin group and a chip bearing of a plurality of outer pin groups, a plurality of relative arrangements, its chips bearing is to be disposed between the interior pin group of a plurality of relative arrangements, and forms a difference in height with the interior pin group of a plurality of relative arrangements; One multi-chip interleaving offset stacked structure is to be fixed on the chip bearing, multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active surface of each first chip on a side near configuration and exposing also dispose near another side on the active surface of a plurality of weld pads and each second chip and expose a plurality of weld pads with respect to this a plurality of exposure weld pads of first chip, wherein a plurality of first chips of multi-chip interleaving offset stacked structure and a plurality of second chip are by the interior pin group electric connection of the relative arrangement with these a plurality of one-tenth of most strip metal leads; And a packaging body, coating multi-chip interleaving offset stacked structure and lead frame, a plurality of outer pins are to stretch out in outside the packaging body; Wherein comprise at least one busbar in the lead frame, be disposed between the interior pin of a plurality of relative arrangements and the chip bearing and with etc. in pin form a copline, and busbar is formed with a plurality of metal segments.
The present invention further provides a kind of conducting wire frame structure with multi-section bus bar, comprise the interior pin of a plurality of relative arrangements and one be disposed between the pin and interior pin to form the chip bearing of a difference in height and at least one busbar be to be disposed between the interior pin of a plurality of relative arrangements and the chip bearing and busbar is formed with a plurality of metal segments.
Description of drawings
Figure 1A to Fig. 1 D is to be the schematic diagram of prior art;
Fig. 2 A and 2C figure are to be the top view of chip structure of the present invention;
Fig. 2 B and Fig. 2 D are to be the cutaway view of chip structure of the present invention;
Fig. 2 E is to be the cutaway view of multi-chip interleaving offset stacked structure of the present invention;
Fig. 3 A to Fig. 3 C is a schematic diagram of reshuffling layer manufacture process of the present invention;
Fig. 4 A and Fig. 4 B are cutaway views of reshuffling the wire bonds district in the floor of the present invention;
Fig. 5 is the cutaway view with the multi-chip interleaving offset stacked structure of reshuffling layer of the present invention;
Fig. 6 is the cutaway view of another embodiment of multi-chip interleaving offset stacked structure of the present invention;
Fig. 7 A to Fig. 7 D is the cutaway view with the multi-chip interleaving offset stacked structure of reshuffling layer of the present invention;
Fig. 8 is the cutaway view of multi-chip interleaving offset stacked construction packages of the present invention;
Fig. 9 is the cutaway view of another embodiment of multi-chip interleaving offset stacked construction packages of the present invention;
Figure 10 is the cutaway view of another embodiment of multi-chip interleaving offset stacked construction packages of the present invention;
Figure 11 is the cutaway view of another embodiment of multi-chip interleaving offset stacked construction packages of the present invention; And
Figure 12 is the cutaway view of another embodiment of multi-chip interleaving offset stacked construction packages of the present invention.
[primary clustering symbol description]
10,100,400: stack chip packaging structure
110,410: circuit substrate
112,122a, 122b, 122c, 122d: weld pad
120a, 120b, 120c, 120d: chip
130: sept
140,242,420,420a, 420b: lead
150,430: packing colloid
200: chip
210: the chip active surface
220: chip back
230: adhesion coating
240: weld pad
250: the wire bonds district
260: the wire welding area edge
30: multi-chip interleaving offset stacked structure
310: the chip body
312a: first weld pad
312b: second weld pad
320: the wire bonds district
330: the first protective layers
332: the first openings
340: reconfiguration line layer
344: the three weld pads
350: the second protective layers
352: the second openings
300: chip structure
400: reshuffle layer
50: multi-chip interleaving offset stacked structure
500 (a, b, c, d): chip structure
600: lead frame
610: interior pin group
6101～6105: interior pin
6102～6106: interior pin
620: the chip bearing
630: busbar
630n (n=1,2,3 ... .): metal segments
6301～63010: metal segments
640n (n=a, b, c ... .): plain conductor
Embodiment
The present invention is a kind of mode of using the chip staggered offset to pile up in this direction of inquiring into, and the chip stack that a plurality of sizes are close or different builds up a kind of tridimensional encapsulating structure.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that skill person had the knack of of chip-stacked mode.On the other hand, the detailed step of back-end process such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, its with after claim be as the criterion.
In the semiconductor packing process in modern times, all be that a wafer (wafer) of having finished FEOL (FrontEnd Process) is carried out thinning processing (Thinning Process) earlier, for example the thickness with chip is ground between 2～20mi l; Then, coating (coating) or wire mark (printing) one deck macromolecule (polymer) material are in the back side of chip again, and this macromolecular material can be a kind of resin (resin), particularly a kind of B-Stage resin.Via a baking or irradiation processing procedure, make macromolecular material present a kind of semi-curing glue again with viscosity; Follow again, an adhesive tape that can remove (tape) is attached on the macromolecular material of semi-solid preparation shape; Then, the cutting (sawing process) of carrying out wafer is to form many chip (die); At last, just many chip can be connected with substrate and chip is formed the stacked chips structure.
Shown in Fig. 2 A and Fig. 2 B, be floor map and the generalized section of finishing the chip 200 of aforementioned processing procedure.Shown in Fig. 2 A, chip 200 has the back side 220 of an active surface 210 and a relative active surface, and has formed an adhesion coating 230 on the chip back 220; To emphasize that at this adhesion coating 230 of the present invention is not defined as aforesaid semi-curing glue,, be enforcement aspect of the present invention, for example: glued membrane (die attachedfilm) so long as can form the sticky material that engages with lead frame or chip.Secondly, in an embodiment of the present invention, a plurality of weld pads 240 are disposed on the side of active surface 210 of chip 200.Moreover shown in figure 2C and Fig. 2 D, with chip 200 different parts, a plurality of weld pads 240 on the active surface 210 of another chip 20 are configured on another side, and promptly chip 20 is to be configured on the relative side with a plurality of separately weld pads 240 on the chip 200.Secondly, definition one edge line 260 is stressed that as the alignment line in wire bonds district 250 edge line 260 is actually and does not exist on the chip 200 on each chip, and it is only as a reference line.
Utilize above-mentioned chip 20 and 200 can form a kind of multi-chip interleaving offset stacked structure.Fig. 2 E is depicted as a kind of generalized section of multi-chip interleaving offset stacked structure, the structure 30 of multi-chip interleaving offset stacked is to determine the overlapping area that the mutual staggered offset of each chip piles up according to the number of chips of piling up, for example, when undermost two chip 20a and 200a engage with adhesion coating 230, chip 200a covers chip 20a alternately greater than area over half, the area that chip 20b covers chip 200a alternately then covers the area of chip 20a greater than chip 200a, and the chip on the upper strata of healing covers lower floor's area of chip more alternately.Simultaneously, each chip is that alignment line forms with the edge line 260 in wire bonds district, therefore can form similar stair-stepping multi-chip interleaving offset stacked structure, and the feasible weld pad that is configured on the chip is not all covered by the chip on upper strata or covers.Illustrate with a specific embodiment, the size of chip 20a, 20b, 20c, 20d or chip 200a, 200b, 200c, 200d is about 10mm * 13mm * 75 μ m, the thickness of each adhesion coating 230 is about 60 μ m, and the substrate thickness that then carries multi-chip interleaving offset stacked structure is about 200 μ m to 250 μ m.According to above-mentioned, the maximum that the structure 30 of multi-chip interleaving offset stacked is finished after piling up is piled up spreading width (overhang): with 6 layers of chip is that example is about 1mm; With 8 layers of chip is that example then can be less than 1.5mm.Be stressed that once more, quantity and size thereof for the chip of the structure of above-mentioned formation multi-chip interleaving offset stacked, the present invention is not limited, as long as the structure of formed multi-chip interleaving offset stacked that can be according to the previous description, be enforcement aspect of the present invention, for example the staggered offset stacked structure of 2 layers of chip or the staggered offset stacked structure of 4 layers of chip.
Next another embodiment of chip pad design of the present invention to be described, be to use a position change, as shown in Figure 3A with chip structure of reconfiguration line layer with chip pad.One chip body 310 at first is provided, and cooks up wire bonds district 320 at the single side of adjacent chips body 310.Pad zone on the active surface of chip body 310 is divided into the first weld pad 312a and the second weld pad 312b, and wherein the first weld pad 312a is positioned at wire bonds district 320, the second weld pad 312b and then is positioned at outside the wire bonds district 320.
Then with reference to figure 3B, form first protective layer 330 on the active surface of chip body 310, wherein first protective layer 330 has a plurality of first openings 332, to expose the first weld pad 312a and the second weld pad 312b.Form reconfiguration line layer 340 then on first protective layer 330, it comprises many leads 342 and a plurality of the 3rd weld pads 344.In this embodiment, the 3rd weld pad 344 is positioned at wire bonds district 320, and lead 342 can electrically connect from the second weld pad 312b and extend to the 3rd weld pad 344, or is electrically connected to the first weld pad 312a from the second weld pad 312b.Secondly, the 3rd weld pad 344 and the first weld pad 312a are arranged in two row, and the single side along chip body 310 is arranged, but the 3rd weld pad 344 and the first weld pad 312a can also with single-row, multiple row or other mode be arranged in the wire bonds district 320.In addition, the material of reconfiguration line layer 340 can be gold, copper, nickel, titanizing tungsten, titanium or other electric conducting material.
With reference to figure 3C; after forming reconfiguration line layer 340; second protective layer 350 is covered on the reconfiguration line layer 340 to form the structure of chip 300, and wherein second protective layer 350 has a plurality of second openings 352, to expose the first weld pad 312a and the 3rd weld pad 344.Be stressed that, the first weld pad 312a and the second weld pad 312b kenel on every side are arranged on the active surface of chip body 310, yet the first weld pad 312a and the second weld pad 312b can also be arranged on the chip body 310 via face array kenel (areaarray type) or other kenel.
With reference to figure 4A and Fig. 4 B, be the generalized section that is illustrated along hatching A-A ' and B-B ' respectively among Fig. 3 C.Chip 300 mainly comprises chip body 310 and reshuffles layer 400, wherein reshuffles layer 400 and comprises first protective layer 330, reconfiguration line layer 340 and second protective layer 350.First protective layer 330 has a plurality of first openings 332, to expose these the first weld pad 312a and the second weld pad 312b.Reconfiguration line layer 340 is disposed on first protective layer 330; second protective layer 350 is covered on the reconfiguration line layer 340; wherein second protective layer 350 has a plurality of second openings 352, to expose the 3rd weld pad 344 of these first weld pad 312a and reconfiguration line layer 340.Clearly; the first weld pad 312a and the 3rd weld pad 344 are positioned at the wire bonds district, and therefore the zone beyond the wire bonds district on second protective layer 350 provides the platform of a carrying, to carry another chip structure; therefore, can form a kind of structure of multi-chip interleaving offset stacked.According to above-mentioned, the structure of multi-chip interleaving offset stacked can comprise the chip that has reconfiguration line layer or one-sided weld pad directly is set, also can only comprise chip with reconfiguration line layer or the structure that only has the formed multi-chip interleaving offset stacked of the chip that one-sided weld pad directly is set, for example extremely shown in Figure 4 with reference to the Fig. 2 in same applicant's the U.S. Pat 7170160, repeat no more in this.
Please refer to shown in Figure 5ly, is the structure 50 of a kind of multi-chip interleaving offset stacked of the present invention.Multi-chip interleaving offset stacked structure 50 is to be piled up by a plurality of chips 500 to form, for example pile up by 4 chip staggered offsets, wherein have on each chip and reshuffle layer 400, so the weld pad 312b on the chip can be disposed on the wire bonds district of chip, and form multi-chip interleaving offset stacked structure 50.Because the stack manner of multi-chip interleaving offset stacked structure 50 is identical with above-mentioned multi-chip interleaving offset stacked structure 30, does not repeat them here.In addition, be to connect between a plurality of chips 500 of formation multi-chip interleaving offset stacked structure 50 with the formed adhesion coating 230 of a macromolecular material.
Multi-chip interleaving offset stacked structure of the present invention is except above-mentioned structure, it is multi-chip interleaving offset stacked structure 30 and 50, also can and have the chip 500 of reshuffling layer 400 with chip 20 piles up alternately to form another kind of multi-chip interleaving offset stacked structure 70, as shown in Figure 6, it is piled up by 6 chip staggered offsets and forms.Because it is identical with the stack manner that forms multi-chip interleaving offset stacked structure 30 and 50 to form the stack manner of multi-chip interleaving offset stacked structure 70, does not repeat them here.Yet be stressed that, present embodiment do not limit chip 20 and chip 500 which layer on the upper strata which layer in lower floor, the present invention is not limited, it is enforcement aspect of the present invention so long as form multi-chip interleaving offset stacked structure of the present invention with chip 20 or chip 200 and chip 500.Simultaneously, will will emphasize once more also that for the quantity of the chip of the structure of above-mentioned formation multi-chip interleaving offset stacked, the present invention is not limited, for example shown in Fig. 2 E, it is piled up by 8 chip staggered offsets and forms; Shown in Figure 5, it is piled up by 4 chip staggered offsets and forms; Shown in Figure 6, it is piled up by 6 chip staggered offsets and forms; Certainly also can be by other the mode of forming, so as long as the structure of formed multi-chip interleaving offset stacked that can be according to the previous description is enforcement aspect of the present invention.
Then, the present invention more proposes a kind of stack type chip packaging structure according to above-mentioned multi-chip interleaving offset stacked structure 30,50 and 70, and is described in detail as follows.Simultaneously, in following declarative procedure, will be embodiment, yet be stressed that multi-chip interleaving offset stacked structure 30 and 70 also is suitable for the disclosed content of present embodiment with multi-chip interleaving offset stacked structure 50.
Then, will the floor map of multi-chip interleaving offset stacked formula encapsulating structure of the present invention be described.Shown in Fig. 7 A, the multi-chip interleaving offset stacking encapsulation construction is to comprise lead frame 600 and multi-chip interleaving offset stacked structure 50.Lead frame 600 comprises interior pin group 610, a plurality of outer pin groups (not being shown on the figure) and the chip bearing 620 that a plurality of one-tenth are arranged relatively, and its chips bearing 620 is to be disposed between the interior pin group 610 of a plurality of relative arrangements.Can be to form a difference in height or form a copline between the interior pin group 610 of a plurality of relative arrangements and the chip bearing 620.In the present embodiment, multi-chip interleaving offset stacked structure 50 is to be configured on the chip bearing 620, and via plain conductor 640 multi-chip interleaving offset stacked structure 50 is connected with the interior pin group 610 of lead frame 600.
Continue with reference to figure 7A, in the lead frame 600 of multi-chip interleaving offset stacking encapsulation construction, comprise that further at least one busbar 630 (bus bar) is disposed between the interior pin group 610 of chip bearing 620 and a plurality of relative arrangements, wherein busbar 630 can adopt at least one strip configuration, and the busbar 630 of each strip configuration is that (n is an integer, n=1 with a plurality of metal segments 630n, 2,3,4 ... .) form, shown in Fig. 7 A and Fig. 7 B.It also is with a plurality of metal segments 630n (n=1,2,3,4 that busbar 630 also can adopt the busbar 630 of ring-type configuration and the configuration of each ring-type ... .) form, shown in Fig. 7 C and Fig. 7 D.In addition, as previously mentioned, the weld pad in the wire bonds district of chip can be that single-row arrangement or multiple row are arranged, and the present invention does not limit.According to above-mentioned, busbar 630 comprises a plurality of metal segments 630n (n=1 independent of each other, 2,3 ... .), make lead frame 600 increase many metal segments 630n (n=1,2,3 ... .) with electric connection, so more elasticity and application on the circuit design can be provided as power supply contact, ground contact or signal contact.
Illustrate that then the present invention uses busbar 630 to reach the process that the plain conductor wire jumper connects, refer again to Fig. 7 A, present embodiment is with a plurality of metal segments 630n (n=1,2,3, ... .) as transit point, be used for reaching weld pad a (a ') is connected with interior pin 6101 (6102) to interior pin 6105 (6106) wire jumpers to weld pad d (d '), and can not produce the situation that plain conductor is crossed over mutually.For example, with a plain conductor 640 the weld pad a on the multi-chip interleaving offset stacked structure 50 is connected to the metal segments 6301 of busbar 630 earlier, and this metal segments 6301 can be used as a ground connection tie point.Pin 6101 in then plain conductor 640 is directly connected to weld pad b.In like manner, electrically connect weld pad c after metal segments 6303, electrically connect metal segments 6303 and interior pin 6105 by another plain conductor 640 again with plain conductor 640; Therefore, finish when being connected when weld pad c and interior pin 6105, can avoid with connect weld pad c and the plain conductor 640 of interior pin 6105 be connected with another weld pad d and in the situation of plain conductor 640 generation leaps of pin 6103.And at the weld pad a ' of another side to weld pad d ' and the wire jumper connection procedure of interior pin 6102,6104 to interior pin 6106, also be to use the metal segments 6302 that forms busbar 630 to metal segments 6304 to form connection as transit point, and this connection procedure as hereinbefore, therefore finishing weld pad a ' after being connected to weld pad d ' and interior pin 6102 to interior pin 6106, can not produce plain conductor 640 situations of leaps mutually yet.
And in another embodiment, when having a plurality of weld pads must carry out the wire jumper connection on the multi-chip interleaving offset stacked structure 50, can use the structure of many busbars 630 to reach, shown in Fig. 7 B.Fig. 7 B shows the schematic diagram that the structural weld pad of multi-chip interleaving offset stacked is connected with interior pin.Clearly, present embodiment can utilize a plurality of metal segments 630n (n=1,2,3 that form busbar 630, ... .) reach as transit point weld pad (a/a '～f/f ') is connected with interior pin 610 wire jumpers, and can not produce the situations that plain conductor 640 is crossed over mutually.For example, earlier with a strip metal lead 640 the weld pad a on the multi-chip interleaving offset stacked structure 50 or a ' are connected to metal segments 6301 or 6302 on the busbar 630 earlier, this metal segments 6301 or 6302 then can be used as a ground connection tie point; With a strip metal lead 640 weld pad b on the multi-chip interleaving offset stacked structure 50 or b ' are directly connected to earlier on the metal segments 6307 or 6308 of busbar 630 then, then are connected with interior pin 6103 or 6104 with the metal segments 6307 or 6308 of another strip metal lead 640 again busbar 630.Therefore, finish when being connected, can avoid crossing over another and being connected the plain conductor 640 that weld pad c or c ' reach interior pin 6101 or 6102 connecting weld pad b or b ' and the plain conductor 640 of interior pin 6103 (6104) when weld pad b or b ' and interior pin 6103 or 6104.Then, carry out weld pad d or d ' are connected with the wire jumper of interior pin 6107 or 6108, with a strip metal lead 640 weld pad d on the multi-chip interleaving offset stacked structure 50 or d ' are connected to earlier on the metal segments 6303 or 6304 of busbar 630 earlier, and then be connected with metal segments 6309 or 63010 with the metal segments 6303 or 6304 of another strip metal lead 640 with busbar 630, at last, with another strip metal lead 640 metal segments on the busbar 630 6309 or 63010 is connected with interior pin 6107 or 6108 again.Therefore, finish when being connected when weld pad d or d ' and interior pin 6107 or 6108, can avoid must crossing over another and being connected the plain conductor 640 that weld pad f or f ' reach interior pin 6105 or 6106 connecting weld pad d or d ' and the plain conductor 640 of interior pin 6107 or 6108; Then weld pad e or e ' are connected to earlier on the metal segments 6305 or 6306 of busbar 630 again, and then with another strip metal lead 640 metal segments 6305 or 6306 of busbar 630 is finished with interior pin 6109 or 61010 and to be connected, so, also can avoid effectively crossing over the plain conductor 640 that another is connected weld pad f or f ' and interior pin 6105 or 6106 with the plain conductor 640 of interior pin 6109 or 61010 with connecting weld pad e or e '.Fig. 7 C and Fig. 7 D are the design of various kenels of the metal segments 630 of embodiments of the invention, because of other parts and Fig. 7 A and Fig. 7 category-B seemingly, repeat no more in this.
Therefore, the structure that is used as a plurality of transit points by the 630 formed busbars 630 of a plurality of metal segments in the lead frame 600 of the present invention, when necessary wire jumper connects carrying out circuit to connect, can avoid the staggered leap of plain conductor, and cause unnecessary short circuit, so can improve the reliability of packaged chip.Simultaneously, have a plurality of metal segments 630n (n=1,2,3 ... .) busbar 630 formed lead frames 600, elasticity more in the time of also can making circuit design.
In addition, to emphasize once more, multi-chip interleaving offset stacked structure 50 of the present invention is to be fixed on the lead frame 600, a plurality of chips in the multi-chip interleaving offset stacked structure 50 wherein, its can be same size and identical function chip (for example: memory chip), or the chip size in a plurality of chips and function (for example: the chip of the superiors is that other chip of chip for driving then is a memory chip) inequality, repeat no more in this.
In addition, in the processing procedure of reality of the present invention, the mode that forms the multi-chip interleaving stacked structure has two kinds, and the first is finished a plurality of chips earlier the back (for example Fig. 2 E, Fig. 5 or Fig. 6) that is staggeredly stacked alternately earlier, is connected with lead frame again; Yet, also can be earlier with undermost chip (20a shown in Fig. 2 E) and lead frame 600 affixed after, more in regular turn with staggered alternately up the piling up of chip on upper strata.No matter use aforementioned which kind of method to form multi-chip interleaving stacked structure (comprising 30,50 or 70), it can be connected multi-chip interleaving stacked structure (comprising 30,50 or 70) with plain conductor 640 after finishing the piling up of chip again with the interior pin group 610 of lead frame 600.Clearly, the encapsulating structure that formation multi-chip interleaving of the present invention piles up be earlier a plurality of chips and lead frame company are finished connect after, just carry out the routing processing procedure, so can the effective simplification encapsulation procedure.Still to emphasize again, (comprise 30,50 or 70) in the structure that each multi-chip interleaving in the present invention piles up, be configured in weld pad on the chip and all do not covered or cover by the chip on upper strata, therefore just can a plurality of chips be connected with lead frame finish after, carry out the routing processing procedure again.Because connecting chip 500 with plain conductor 640 is a prior art with lead frame 600, and be exposed in detail in the 95133670th, 95133663 and 95133664 cases that the applicant applied for, so do not repeat them here.
Then please refer to Fig. 8, is the present invention 7A and Fig. 7 C generalized section along the multi-chip migration stack package structure of AA line segment section.Between lead frame 600 and the multi-chip interleaving offset stacked structure 50 is to be connected by most strip metal leads 640, wherein lead frame 600 is the interior pin groups 610 by a plurality of relative arrangements, a plurality of outer pin groups (not being shown on the figure) and a chip bearing 620 are formed, and chip bearing 620 is to be disposed between the interior pin group 610 of a plurality of relative arrangements, and form a difference in height with the interior pin group 610 of a plurality of relative arrangements, and one strip or ring-type busbar 630 be disposed between pin group 610 and the chip bearing 620, and busbar 630 comprises a plurality of metal segments 630n (n=1,2,3, ... .), busbar 630 in the present embodiment is the configurations with 620 one-tenth one coplines of chip bearing.Plain conductor 640n (n=a, b, c,) be the end of plain conductor 640a to be connected in first weld pad or the 3rd weld pad (for example first weld pad 312a or the 3rd weld pad 344 among earlier figures 3A, Fig. 3 B, Fig. 3 C) of chip 500d with the routing processing procedure, the other end of plain conductor 640a then is connected in first weld pad or the 3rd weld pad of chip structure 500b.The end of plain conductor 640d is connected on first weld pad or the 3rd weld pad of chip 500c, and then the other end of plain conductor 640d is connected on first weld pad or the 3rd weld pad of chip 500a; Then repeat the process of plain conductor 640a and 640d again.Follow again, chip 500d is finished electric connection with the interior pin group 610 of a plurality of relative arrangements of lead frame 600 with plain conductor 640c, 640f, 640g, 640h.Thus, successively finish connection via plain conductor 640a, 640c, 640d and 640f etc. after, just chip 500d, 500c, 500b and 500a can be electrically connected at lead frame 600, wherein the material of these plain conductors 640 can be used gold.
Simultaneously, owing to dispose busbar 630 on the lead frame 600 of present embodiment, it can be used as the electric connection that comprises power supply contact, ground contact or signal contact.For example, as a plurality of metal segments 630n (n=1 with formation busbar 630,2,3, ... .) during the transit point that connects as circuit, so the end of plain conductor 640b can be connected on the weld pad of chip 500b, and the other end of plain conductor 640b be connected to busbar metal segments on, and then by plain conductor 640g with the metal segments of busbar be connected to some on the pin.
Via above-mentioned explanation, in an embodiment of the present invention, selectively an end of plain conductor is connected in the weld pad of chip, and the other end of plain conductor is connected on the busbar 630 or optionally is connected on one or more metal segments.Owing to disposed one or more metal segments on the busbar 630, can be so that the utilization of the weld pad on the multi-chip stacking structure has more elasticity, for example, can utilize the structure of this busbar 630, certain several metal segments is set at ground contact, the metal segments 6301 among Fig. 7 A and Fig. 7 C for example, certain several metal segments then is set at power supply contact, certain several metal segments also can be set at signal contact even, for example the metal segments 6303 and 6305 among Fig. 7 C.Therefore, the configuration of these metal segments then forms the function of similar electrical transit point.So when the weld pad on the multi-chip stacking structure needs wire jumper or cross-line just can finish the connection of circuit, just do not need laterally to stride across other plain conductor, and can finish via the switching of metal segments.So, increase, also so not only can increase the elasticity in circuit design or the application, also can effectively improve the production capacity and the reliability of encapsulation procedure with regard to not producing the radian that makes the plain conductor that to cross in order to cross over other plain conductor.Clearly, in the structure 50 that the multi-chip interleaving of present embodiment piles up, it is configured in weld pad on the chip and is not all covered by the chip on upper strata or cover, therefore can a plurality of chips and lead frame company finish connect after, carry out the routing processing procedure again.
Then please refer to Fig. 9, Figure 10 and Figure 11, is the present invention 7A and Fig. 7 C generalized section along another embodiment of the multi-chip migration stacked structure of AA line segment section.The configuration mode of the busbar 630 of the lead frame 600 of Fig. 9, Figure 10 and Figure 11 can be the strip configuration of Fig. 7 A, also can be the ring-type configuration among Fig. 7 C.Same, also dispose a plurality of metal segments on the busbar 630 in the present embodiment.Clearly, the difference of Fig. 9, Figure 10 and Figure 11 and Fig. 8 is in only inequality in the structure of lead frame 600, for example the height of the busbar 630 of the lead frame among Fig. 9 600 and interior pin 610 coplines and form a difference in height with chip bearing 620; 620 of the busbar 630 of the lead frame 600 among Figure 10 and interior pin 610 and chip bearings form a difference in height; And the interior pin 610 of the lead frame 600 among Figure 11 forms copline and forms a difference in height with busbar 630 with chip bearing 620.In addition, Fig. 9, Figure 10 and Figure 11 use connection procedure and Fig. 8 of most strip metal leads 640 identical between lead frame 600 and multi-chip interleaving offset stacked structure 50, do not repeat them here.
Then again, please refer to shown in Figure 12ly, is Fig. 7 B of the present invention and Fig. 7 D generalized section of an embodiment again along the multi-chip migration stacked structure of AA line segment section.As shown in figure 12, lead frame 600 in the present embodiment is the interior pin groups 610 by a plurality of relative arrangements, a plurality of outer pin groups (not being shown on the figure) and a chip bearing 620 are formed, and chip bearing 620 is to be disposed between the interior pin group 610 of a plurality of relative arrangements, and form the structure of a difference in height with the interior pin group 610 of a plurality of relative arrangements, and at least one be configured in busbar 630 between pin group 610 and the chip bearing 620, wherein can form a copline between busbar 630 and the chip bearing 620, and busbar 630 also is by a plurality of metal segments 630n (n=1,2,3 ... .) form.Same, when multi-chip interleaving offset stacked structure with after lead frame 600 engages, the routing that carries out plain conductor 640 connects, because it is lead frame 600 is same as the previously described embodiments with the process that plain conductor is connected with multi-chip interleaving offset stacked structure, and the routing processing procedure is not a feature of the present invention, just repeats no more in this.Still to emphasize at this,, yet in the application of implementing, can look the design of circuit and complicated case and use most bar busbars though the busbar 630 of Figure 12 is at least one strip structure or the schematic diagram of at least one circulus; And identical to the application between most bar busbars 630 with the embodiment of Fig. 7 B, Fig. 7 D, also repeat no more in this.In addition, Figure 12 also only is an embodiment, and it is in the structure of lead frame 600, also can be identical with the structure of lead frame 600 among Fig. 8 to Figure 11, so its detailed connection procedure also repeats no more.Clearly, the encapsulating structure that formation multi-chip interleaving of the present invention piles up be earlier a plurality of chips and lead frame company are finished connect after, just carry out the routing processing procedure, so can the effective simplification encapsulation procedure.Still to emphasize again, in the structure 50 that multi-chip interleaving in the present embodiment piles up, be configured in weld pad on the chip and all do not covered or cover by the chip on upper strata, therefore can a plurality of chips and lead frame company finish connect after, carry out the routing processing procedure again.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement widely in other embodiments.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the following claim.

Claims (11)

1. have the stack type chip packaging structure of multi-section bus bar in the lead frame, it is characterized in that comprising:
One lead frame is made up of the interior pin of a plurality of relative arrangements, a plurality of outer pin and a chip bearing, and wherein this chip bearing is to be disposed between the interior pin of these a plurality of relative arrangements, and forms a difference in height with the interior pin of these a plurality of relative arrangements;
One multi-chip interleaving offset stacked structure, be to be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active surface of each this first chip on a side near near configuration and expose exposing on the active surface of a plurality of weld pads and each this second chip and also dispose another sides of weld pads and expose these weld pads with respect to these of these first chips, wherein a plurality of first chips of this multi-chip interleaving offset stacked structure this and this a plurality of second chips are by the interior pin group electric connection of the relative arrangement with these a plurality of one-tenth of most strip metal leads;
One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these outer pins are to stretch out in outside this packaging body; And
At least one busbar be to be disposed between the interior pin of these a plurality of relative arrangements and this chip bearing and with this chip bearing to form a copline, and this busbar is formed with a plurality of metal segments.
2. have the stack type chip packaging structure of multi-section bus bar in the lead frame, it is characterized in that comprising:
One lead frame is made up of the interior pin and a chip bearing of a plurality of outer pins, a plurality of relative arrangements, and wherein this chip bearing is to be disposed between these interior pins of arranging relatively, and the interior pin of relative arrangement with these forms a difference in height;
One multi-chip interleaving offset stacked structure, be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active surface of each this first chip on a side near configuration and exposing also dispose near another side on the active surface of a plurality of weld pads and each this second chip and expose these weld pads with respect to this a plurality of exposure weld pads of this first chip, wherein these first chips of this multi-chip interleaving offset stacked structure and these second chips become the interior pin group electric connection of relative arrangement by most strip metal leads and these;
One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these outer pins are to stretch out in outside this packaging body; And
At least one busbar, be disposed between these interior pins of relatively arranging and this chip bearing and with these in pin form a copline, and this busbar is formed with a plurality of metal segments.
3. have the stack type chip packaging structure of multi-section bus bar in the lead frame, it is characterized in that comprising:
One lead frame is made up of the interior pin and a chip bearing of a plurality of outer pins, a plurality of relative arrangements, and wherein this chip bearing is to be disposed between these interior pins of arranging relatively, and the interior pin of relative arrangement with these forms a difference in height;
One multi-chip interleaving offset stacked structure, one multi-chip interleaving offset stacked structure, be to be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active surface of each this first chip on a side near near configuration and expose exposing on the active surface of a plurality of weld pads and each this second chip and also dispose another sides of weld pads and expose these weld pads with respect to these of this first chip, wherein these first chips of this multi-chip interleaving offset stacked structure and these second chips become the interior pin group electric connection of relative arrangement by most strip metal leads and these;
One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these outer pins are to stretch out in outside this packaging body; And
At least one busbar be to be disposed between these interior pins of relatively arranging and this chip bearing and interior pin and this chip bearing of relative arrangement with these form a difference in height, and this busbar is formed with a plurality of metal segments.
4. have the stack type chip packaging structure of multi-section bus bar in the lead frame, it is characterized in that comprising:
One lead frame, an interior pin and a chip bearing by a plurality of outer pins, a plurality of relative arrangements are formed, wherein this chip bearing is to be disposed between these interior pins of arranging relatively, and the interior pin of relative arrangement with these forms a copline;
One multi-chip interleaving offset stacked structure, one multi-chip interleaving offset stacked structure, be to be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active surface of each this first chip on a side near near configuration and expose exposing on the active surface of a plurality of weld pads and each this second chip and also dispose another sides of weld pads and expose a plurality of weld pads with respect to these of these first chips, wherein these first chips of this multi-chip interleaving offset stacked structure and these second chips are by the interior pin group electric connection of the relative arrangement with this a plurality of one-tenth of most strip metal leads;
One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these a plurality of outer pins are to stretch out in outside this packaging body; And
At least one busbar be to be disposed between these interior pins of relatively arranging and this chip bearing and to form a difference in height with interior pin and this chip bearing of these a plurality of relative arrangements, and this busbar is formed with a plurality of metal segments.
5. as claim 1,2,3 or 4 described encapsulating structures, it is characterized in that each this chip in this multi-chip interleaving offset stacked structure comprises:
One chip body, has a wire bonds zone, this wire bonds zone is single side or the adjacent dual-side that is adjacent to this chip body, and wherein this chip body has and a plurality ofly is positioned at one first weld pad in this wire bonds zone and is positioned at extra-regional a plurality of second weld pads of this wire bonds;
One first protective layer is disposed on this chip body, and wherein this first protective layer has a plurality of first openings, to expose these first weld pads and these second weld pads;
One reconfiguration line layer is disposed on this first protective layer, and wherein this reconfiguration line layer extends in this wire bonds zone from these second weld pads, and this reconfiguration line layer has a plurality of the 3rd weld pads that are positioned at this wire bonds zone; And
One second protective layer is covered on this reconfiguration line layer, and wherein this second protective layer has a plurality of second openings, to expose these first weld pads and these the 3rd weld pads.
6. have the stack type chip packaging structure of multi-section bus bar in the lead frame, it is characterized in that comprising:
One lead frame is made up of the interior pin of a plurality of relative arrangements, a plurality of outer pin and a chip bearing, and wherein this chip bearing is to be disposed between the interior pin of these a plurality of relative arrangements, and forms a difference in height with the interior pin of these a plurality of relative arrangements;
One multi-chip interleaving offset stacked structure, be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by two first chips and two second chips are staggered alternately and with a side-play amount pile up form and an active surface of each this first chip on a side near near configuration and expose exposing on the active surface of a plurality of weld pads and each this second chip and also dispose another sides of weld pads and expose a plurality of weld pads with respect to these of these first chips;
Most strip metal leads are the relative interior pin group electric connections of arranging with these one-tenth of weld pad with a plurality of exposures on these two first chips and this two second chips;
One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these outer pins are to stretch out in outside this packaging body; And
At least one busbar be to be disposed between the interior pin of these a plurality of relative arrangements and this chip bearing and with this chip bearing to form a copline, and this busbar is formed with a plurality of metal segments.
7. have the stack type chip packaging structure of multi-section bus bar in the lead frame, it is characterized in that comprising:
One lead frame is made up of the interior pin and a chip bearing of a plurality of outer pins, a plurality of relative arrangements, and wherein this chip bearing is to be disposed between these interior pins of arranging relatively, and the interior pin of relative arrangement with these forms a difference in height;
One multi-chip interleaving offset stacked structure, be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by two first chips and two second chips are staggered alternately and with a side-play amount pile up form and an active surface of each this first chip on a side near near configuration and expose exposing on the active surface of a plurality of weld pads and each this second chip and also dispose another sides of weld pads and expose a plurality of weld pads with respect to these of this first chip;
Most strip metal leads are to become the relative interior pin group who arranges to electrically connect a plurality of weld pads that exposed on these two first chips and this two second chips and these;
One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these outer pins are to stretch out in outside this packaging body; And
At least one busbar, be disposed between these interior pins of relatively arranging and this chip bearing and with these in pin form a copline, and this busbar is formed with a plurality of metal segments.
8. have the stack type chip packaging structure of multi-section bus bar in the lead frame, it is characterized in that comprising:
One lead frame is made up of the interior pin and a chip bearing of a plurality of outer pins, a plurality of relative arrangements, and wherein this chip bearing is to be disposed between these interior pins of arranging relatively, and the interior pin of relative arrangement with these forms a difference in height;
One multi-chip interleaving offset stacked structure, be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by two first chips and two second chips are staggered alternately and with a side-play amount pile up form and an active surface of each this first chip on a side near near configuration and expose exposing on the active surface of a plurality of weld pads and each this second chip and also dispose another sides of weld pads and expose a plurality of weld pads with respect to these of these first chips;
Most strip metal leads are to become the relative interior pin group who arranges to electrically connect a plurality of weld pads that exposed on these two first chips and this two second chips and these;
One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these outer pins are to stretch out in outside this packaging body; And
At least one busbar is to be disposed between these interior pins and this chip bearing of relatively arranging, and interior pin and this chip bearing of the relative arrangement with these of this busbar form a difference in height, and this busbar is formed with a plurality of metal segments.
9. have the stack type chip packaging structure of multi-section bus bar in the lead frame, it is characterized in that comprising:
One lead frame is made up of the interior pin and a chip bearing of a plurality of outer pins, a plurality of relative arrangements, and wherein this chip bearing is to be disposed between these interior pins of arranging relatively, and the interior pin of relative arrangement with these forms a copline;
One multi-chip interleaving offset stacked structure, be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by two first chips and two second chips are staggered alternately and with a side-play amount pile up form and an active surface of each this first chip on a side near near configuration and expose exposing on the active surface of a plurality of weld pads and each this second chip and also dispose another sides of weld pads and expose a plurality of weld pads with respect to these of this first chip;
Most strip metal leads are to become the relative interior pin group who arranges to electrically connect a plurality of weld pads that exposed on these two first chips and this two second chips and these;
One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these outer pins are to stretch out in outside this packaging body; And
At least one busbar be to be disposed between these interior pins of arranging relatively and this chip bearing and with this chip bearing to form a difference in height, and this busbar is formed with a plurality of metal segments.
10. as claim 6,7,8 or 9 described encapsulating structures, it is characterized in that each this chip in this multi-chip interleaving offset stacked structure comprises:
One chip body, has a wire bonds zone, this wire bonds zone is single side or the adjacent dual-side that is adjacent to this chip body, and wherein this chip body has a plurality of first weld pads that are positioned at this wire bonds zone and is positioned at extra-regional a plurality of second weld pads of this wire bonds;
One first protective layer is disposed on this chip body, and wherein this first protective layer has a plurality of first openings, to expose these first weld pads and these second weld pads;
One reconfiguration line layer is disposed on this first protective layer, and wherein this reconfiguration line layer extends in this wire bonds zone from these second weld pads, and this reconfiguration line layer has a plurality of the 3rd weld pads that are positioned at this wire bonds zone; And
One second protective layer is covered on this reconfiguration line layer, and wherein this second protective layer has a plurality of second openings, to expose these first weld pads and these the 3rd weld pads.
11. conducting wire frame structure with multi-section bus bar, the interior pin, one that comprises a plurality of relative arrangements is disposed at the chip bearing between pin in this and at least one and is disposed in these busbar between the pins and this chip bearing and forms, and it is characterized in that:
This busbar is formed with a plurality of metal segments.
CN2007101432981A 2007-08-09 2007-08-09 Staggered offset stacking encapsulation construction having multistage omnibus bar in conductive wire support Active CN101364593B (en)

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CN103098206A (en) * 2010-03-18 2013-05-08 莫塞德技术公司 Multi-chip package with offset die stacking and method of making same
CN103238213A (en) * 2012-04-18 2013-08-07 晟碟半导体（上海）有限公司 Tilt bare chip stack body
CN104362101A (en) * 2010-01-08 2015-02-18 瑞萨电子株式会社 Method of manufacturing semiconductor device
US9524254B2 (en) 2008-07-02 2016-12-20 Micron Technology, Inc. Multi-serial interface stacked-die memory architecture
US9852813B2 (en) 2008-09-11 2017-12-26 Micron Technology, Inc. Methods, apparatus, and systems to repair memory

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US9524254B2 (en) 2008-07-02 2016-12-20 Micron Technology, Inc. Multi-serial interface stacked-die memory architecture
US9852813B2 (en) 2008-09-11 2017-12-26 Micron Technology, Inc. Methods, apparatus, and systems to repair memory
US10332614B2 (en) 2008-09-11 2019-06-25 Micron Technology, Inc. Methods, apparatus, and systems to repair memory
CN104362101A (en) * 2010-01-08 2015-02-18 瑞萨电子株式会社 Method of manufacturing semiconductor device
CN104362101B (en) * 2010-01-08 2017-04-12 瑞萨电子株式会社 Method of manufacturing semiconductor device
CN103098206A (en) * 2010-03-18 2013-05-08 莫塞德技术公司 Multi-chip package with offset die stacking and method of making same
US9177863B2 (en) 2010-03-18 2015-11-03 Conversant Intellectual Property Management Inc. Multi-chip package with offset die stacking and method of making same
CN102822966A (en) * 2010-03-30 2012-12-12 美光科技公司 Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same
US9484326B2 (en) 2010-03-30 2016-11-01 Micron Technology, Inc. Apparatuses having stacked devices and methods of connecting dice stacks
CN103238213A (en) * 2012-04-18 2013-08-07 晟碟半导体（上海）有限公司 Tilt bare chip stack body
CN103238213B (en) * 2012-04-18 2016-03-16 晟碟半导体（上海）有限公司 Tilt bare chip stack body

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