CN101364585B - Chip packaging construction and manufacturing method therefor - Google Patents

Chip packaging construction and manufacturing method therefor Download PDF

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Publication number
CN101364585B
CN101364585B CN2008101988978A CN200810198897A CN101364585B CN 101364585 B CN101364585 B CN 101364585B CN 2008101988978 A CN2008101988978 A CN 2008101988978A CN 200810198897 A CN200810198897 A CN 200810198897A CN 101364585 B CN101364585 B CN 101364585B
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China
Prior art keywords
chip
support
conductive arm
groups
encapsulating housing
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Expired - Fee Related
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CN2008101988978A
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Chinese (zh)
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CN101364585A (en
Inventor
黄仕冲
林贞秀
周孟松
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Lite On Opto Technology Changzhou Co Ltd
Original Assignee
Silitek Electronic Guangzhou Co Ltd
Lite On Technology Corp
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Application filed by Silitek Electronic Guangzhou Co Ltd, Lite On Technology Corp filed Critical Silitek Electronic Guangzhou Co Ltd
Priority to CN2008101988978A priority Critical patent/CN101364585B/en
Publication of CN101364585A publication Critical patent/CN101364585A/en
Priority to US12/457,563 priority patent/US8319245B2/en
Priority to US12/585,715 priority patent/US8089140B2/en
Application granted granted Critical
Publication of CN101364585B publication Critical patent/CN101364585B/en
Priority to US13/651,516 priority patent/US20130037845A1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21K—NON-ELECTRIC LIGHT SOURCES USING LUMINESCENCE; LIGHT SOURCES USING ELECTROCHEMILUMINESCENCE; LIGHT SOURCES USING CHARGES OF COMBUSTIBLE MATERIAL; LIGHT SOURCES USING SEMICONDUCTOR DEVICES AS LIGHT-GENERATING ELEMENTS; LIGHT SOURCES NOT OTHERWISE PROVIDED FOR
    • F21K9/00—Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2103/00—Elongate light sources, e.g. fluorescent tubes
    • F21Y2103/10—Elongate light sources, e.g. fluorescent tubes comprising a linear array of point-like light-generating elements
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2115/00—Light-generating elements of semiconductor light sources
    • F21Y2115/10—Light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

An encapsulated structure of a chip comprises at least a bracket, and at least an encapsulated shell and the chip which are mounted on the bracket; the chip is arranged in the encapsulated shell and electrically connected with the bracket; the encapsulated chip structure adopts the punching method to integrally shape the bracket and the encapsulated shell set; the chip is directly mounted on the bracket, thereby simplifying the production procedure and preventing the characteristics of the chip, such as the optical performance, the extension quality, the luminous efficiency, etc. from being affected due to the heating of the chip; the bracket which is made of metal can not only serve as a lead frame for the chip to realize electric connection between the chip and the external power source, but also function as a radiating frame for the chip, so as to increase the work efficiency of the chip through rapid heat dissipation; since a radiating layer is no longer needed to be installed, the thickness of the encapsulated structure is reduced, thereby not only lowering the material cost for the radiating layer, but also reducing the production cost by simplifying the production procedure; and as the thickness is reduced, the encapsulated chip structure is more suitable for being used on pliable module products.

Description

A kind of chip-packaging structure and manufacture method thereof
Technical field
The present invention relates to a kind of chip-packaging structure and manufacture method thereof.
Background technology
In recent years, the field that light-emitting diode (LED) is employed is quite extensive, as stop lamp of the light source on the LCD screen, projecting lamp, traffic etc. and automobile or the like, day by day replaces traditional filament bulb.Yet, existing chip, though have the characteristic that volume is little, energy consumption is low, with regard to single chips, energy of light source is less, all is restricted in the application of numerous areas.In order to increase the overall brightness of light emitting source, then need to increase the number or the density of chip.
For number or the density that increases chip, traditional manufacturing method of chip is that the chip finished product after the moulding is installed on respectively on the printed circuit board (PCB), realizes electric connection between each chip by the circuit on the printed circuit board (PCB).Adopt this manufacture method, need seriatim the mode of chip by wave soldering or reflow to be installed on the printed circuit board (PCB), thus, process time, the increase according to the chip number of required installation increased, and then the process-cycle of increase chip, and, chip is very compact components and parts, installation accuracy requires very high, need respectively with printed circuit board (PCB) on circuit electrically connect, this manufacture method of installing has respectively improved the difficulty of processing greatly, needs accurately to aim at corresponding circuit, like this, also will further increase the process-cycle.In addition, because traditional manufacture method need pass through reflow or wave soldering technology, influence the characteristics such as himself optical characteristics, extension quality, luminous efficiency, life-span of chip easily because of being heated.
In addition, because the product face of light-emitting diode (LED) is very extensive, except being applied to, also have some to need crooked or around the light source of song, as decorative lamp, built-in light, hand steered ladder, ladder lamp or path indicator etc. as the flat light sources such as light fixture, billboard.Yet the general at present mode by independent installation is installed on the LED monomer on the printed circuit board (PCB) respectively, has increased the moulding difficulty and the manufacturing process of having mercy on property led module greatly.
Therefore, providing chip-packaging structure and the manufacture method thereof that a kind of manufacturing process is simple, cost is low, the high and thick degree of precision is thin is necessity to address the above problem real.
Summary of the invention
The object of the present invention is to provide a kind of chip-packaging structure, it comprises: at least one support and at least one chip, described support comprises the three groups of conductive arms at interval that are parallel to each other: first conductive arm, second conductive arm and the 3rd conductive arm, be respectively equipped with the electric connection point on three groups of conductive arms, wherein, electric connection point on first conductive arm and the 3rd conductive arm can electrically connect with external power source, second conductive arm is at least one, electric connection point on it can electrically connect with the electric connection point on first conductive arm and the 3rd conductive arm, and described chip electrically connects point and electrically connects with conductive arm by each; Wherein, this chip-packaging structure also includes a plurality of encapsulating housings, and described encapsulating housing coats this support, and described chip is arranged at respectively in the described encapsulating housing, and the internal perisporium of described encapsulating housing is formed with reflection region.
Encapsulating structure of the present invention also can further comprise following additional technical feature:
In a preferred embodiment of the invention, described chip is a plurality of, and each chip is cascaded mutually.
In another preferred embodiment of the present invention, support is a plurality of, and described a plurality of supports link to each other in line in twos, forms groups of holders.
In another preferred embodiment of the present invention, groups of holders is a plurality of, and these described a plurality of groups of holders are arranged parallel to each other.
In the present invention, support is made by having mercy on property electric conducting material, as materials such as iron, copper, aluminium or platinum.Support is provided with a plurality of linking to each other in twos or the encapsulating housing of space, and described chip is arranged at respectively in this encapsulating housing.
Described a plurality of encapsulating housing, and have a linking arm between the adjacent in twos encapsulating housing, thus a plurality of encapsulating housings are linked together.
Be formed with reflection region in the encapsulating housing, described reflection region is made up of high reflecting material.
The present invention also provides a kind of manufacture method of chip-packaging structure, and it may further comprise the steps:
At least one support of step 1) moulding or groups of holders, in groups of holders, described support is connected in line in twos, and each support comprises the three groups of conductive arms at interval that are parallel to each other, and each conductive arm is provided with the electric connection point; Step 2) installing chip on described support, described chip electrically connects with conductive arm by electrically connecting point;
Wherein, in step 2) encapsulating housing that is formed with a reflection region internal perisporium before coats this support or groups of holders, and in step 2) inject colloid in the cavity of described encapsulating housing by the hole for injecting glue of encapsulating housing afterwards, make colloid be full of cavity, thereby the formed chip encapsulating structure, described Xin Pian Let puts in described encapsulating housing.
Compared with prior art, chip-packaging structure of the present invention and manufacture method thereof have the following advantages:
(1) by one-body molded array support or groups of holders, substituted traditional printed circuit board (PCB), bearing substrate and transmitting medium as chip, many core assemblies of moulding simultaneously chip package, need not to adopt the mode of wave soldering or reflow that chip one by one is installed on printed circuit board (PCB) or the heating panel, simplified production process, improve the automaticity of producing, significantly improve production efficiency, also reduced the integral thickness of chip-packaging structure simultaneously.
(2) because support can adopt deformable material to make, has certain pliability, and the integral thickness of encapsulating structure is thinner, the chip module of both plastic having mercy on property of tool then, also can be applicable to have the decoration of the object of certain curvature, and manufacture method is identical with rectilinear Chip Packaging module, has simplified manufacturing process, and makes that the application of Chip Packaging module of the present invention is more extensive.
(3) owing to reduced the operation of wave soldering or reflow, avoided chip because of being heated to the influence of characteristics such as its optical characteristics, extension quality, luminous efficiency, the working life that has prolonged chip.
(4) support adopts metal to make, directly contact with chip, both can be used as the lead frame of chip, realize the electric connection of chip and external power source, simultaneously, also can be used as the heat radiation rack of chip, improve the operating efficiency of chip by quick heat radiating, heat dissipating layer can be installed again, then reduce the thickness of encapsulating structure, also reduce production cost.
(5) structure of support is quite simple, be easy to moulding, form by some conductive arms, the number of conductive arm can be according to the number setting of chip, wherein two conductive arms and positive and negative conducting end electrically connect, being loaded into each chip of connecting mutually on the support can be by directly (electrically connects by lead) or is electrically connected with positive and negative conducting end indirectly (by the support electric connection), realize the conducting of electric current, utilized the electric conductivity of support dexterously, and, short circuit phenomenon has been avoided in space between each conductive arm.
For making the present invention easier to understand, further set forth the different specific embodiment of the present invention below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 is the stereogram of chip-packaging structure of the present invention;
Fig. 2 is the stereogram of the embodiment one of the support of chip-packaging structure of the present invention;
Fig. 3 is the support of chip-packaging structure of the present invention and the assembly drawing one of chip;
Fig. 4 is the stereogram of the embodiment two of the support of chip-packaging structure of the present invention;
Fig. 5 is the circuit diagram of chip-packaging structure of the present invention;
Fig. 6 is the stereogram of the embodiment three of the support of chip-packaging structure of the present invention;
Fig. 7 is the assembly drawing two of chip-packaging structure of the present invention;
Fig. 8 is the stereogram of another embodiment of chip-packaging structure of the present invention; And
Fig. 9 is the enlarged drawing at C position among Fig. 7.
Embodiment
With reference to shown in Figure 1, the invention provides a kind of chip-packaging structure, it comprises: at least one support 10, a plurality of encapsulating housing 20 and a plurality of chip 30 that is provided with opening, described a plurality of encapsulating housing 20 is loaded on the support 10, described chip 30 is arranged at respectively in the encapsulating housing 20, and electrically connects with described support 10.
With reference to shown in Figure 1, in the present embodiment, described a plurality of encapsulating housing 20 is one-body molded, be connected through linking arm 21 between the adjacent in twos encapsulating housing 20, form encapsulating housing group 200, linking arm 21 can be extended by arbitrary limit arm 201 of encapsulating housing 20, in the present embodiment, the linking arm 21 of the encapsulating housing 20 of any adjacent connection is extended in the same way by its two relative edges arm 201 respectively, in same encapsulating housing, if adjacent encapsulating housing is 20a on a certain support 10,20b and 20c, the limit arm of two encapsulating housing 20a and 20b are respectively the first limit arm 201a and the second limit arm 201b, and the first limit arm 201a and the second limit arm 201b are oppositely arranged for staggered.The first limit arm 201a of encapsulating housing 20a extends along the T direction, be connected to encapsulating housing 20b, and the second limit arm 201b of encapsulating housing 20b also extends along the T direction, is connected to next encapsulating housing 20c, and the like, thereby a plurality of encapsulating housings 20 are connected together.
The shape, number and the position that are appreciated that described limit arm all can be unrestricted, as long as the adjacent encapsulating housing on the same support can be connected.Following several connected mode can be arranged: (1) the described first limit arm 201a and the second limit arm 201b also can be provided with and the same side, and two adjacent encapsulating housings are interconnected in line; (2) described limit arm 201 also can be extended in the same way by the both sides of arbitrary encapsulating housing, like this, two adjacent encapsulating housings can be connected by the two limit arms that are symmetrically distributed, make that the connection of a plurality of encapsulating housings is more firm, the mutual tractive of encapsulating housing in twos, and improved the rigidity of encapsulating housing group, avoided rupturing.Described encapsulating housing group 200 can adopt the mode of one ejection formation to make, and is appreciated that its connected mode that also can adopt other combines a plurality of encapsulating housings 20.
In addition, in order to protect chip 30 and circuit structure, reduce light loss; so be filled with colloid in the cavity 204 (as shown in Figure 9) of encapsulating housing 20, the moulding encapsulated layer, described encapsulated layer covers chip 30 at least; better; described encapsulated layer fills up whole cavity 204, and the upper surface of its cavity 204 upper surface open and encapsulating housing 20 flushes, the higher colloid of the preferred optics light transmittance of colloid; as be mixed with the colloid of fluorescent material; to improve light scattering effect, wherein, colloid is preferably resin.
With reference to shown in Figure 2, in the embodiment one of support of the present invention, described support 10 is strip, it is made by electric conducting material, and preferred metal materials has good heat radiating conductivity, comprise two conducting end 101 and three groups of conductive arms 102, described conducting end 101 is arranged at the two ends of conductive arm 102.Wherein, each conducting end 101 comprises positive conducting end and negative conducting end, and by positive and negative conducting end and external power source electric property coupling, positive conducting end is 101a, and negative conducting end is 101b; Described conductive arm 102 is respectively the first conductive arm 102a, the second conductive arm 102b and the 3rd conductive arm 102c, and each conductive arm is parallel to each other and separates at interval and electrically, is respectively equipped with on it to electrically connect point (not indicating).Wherein, the two ends of the described first conductive arm 102a are connected as a single entity with positive conducting end 101a respectively, the two ends of the 3rd conductive arm 102c are connected as a single entity with negative conducting end 101c respectively, and the electric connection point on the first conductive arm 102a and the 3rd conductive arm 102c can electrically connect with external power source; The second conductive arm 102b is two, be respectively 102b1 and 102b2, be arranged at respectively between the first conductive arm 102a and the 3rd conductive arm 102c, electric connection point on the second conductive arm 102b can electrically connect with the electric connection point on the first conductive arm 102a and the 3rd conductive arm 102c, described a plurality of chip 30 electrically connects point and electrically connects with conductive arm 102 by each, and is cascaded mutually.
In the present invention, the described second conductive arm 102b can be at least one, and when the second conductive arm 102b was one, the chip 30 that is loaded on the second conductive arm 102b electrically connected with the first conductive arm 102a and the 3rd conductive arm 102c by electrically connecting point; As the second conductive arm 102b when being a plurality of, then can load a plurality of chips 30, described a plurality of chips 30 electrically connect point and electrically connect with conductive arm 102 by each, and are cascaded mutually.The number of described chip 30 can be provided with as required, and is same, and the quantity of the second conductive arm 102b also can be according to the number setting of chip 30, as long as can be at interval and the two positive elecrtonegativities of electrically separating arbitrary chip.As on same support 10, if 3 chips 30, then 2 second conductive arm 102b of relative set are set; If 4 chips 30, then 3 second conductive arm 102b of relative set are set; If n chip 30 be set, the individual second conductive arm 102b of relative set n-1 then.
In conjunction with shown in Figure 3, on the described same support 10 3 chips 30 are set, be respectively the first chip 30a, the second chip 30b and the 3rd chip 30c, and adopt series system to electrically connect the first chip 30a, the second chip 30b and the 3rd chip 30c.Specifically, the first chip 30a is arranged at the side of the second conductive arm 102b1, and the second chip 30b also is arranged at the side of the second conductive arm 102b2, and the 3rd chip 30c is arranged at the side of the first conductive arm 102a.In the present embodiment, the negative conducting end 101c electric property coupling that the elecrtonegativity end of the first chip 30a links to each other with the 3rd conductive arm 102c by lead, and its electropositive end is by the lead and the second conductive arm 102b1 electric property coupling; The elecrtonegativity end of the second chip 30b is by the lead and the second conductive arm 102b1 electric property coupling, and its electropositive end is by the lead and the second conductive arm 102b2 electric property coupling; The elecrtonegativity end of the 3rd chip 30c is by the lead and the second conductive arm 102b2 electric property coupling, and the negative conducting end 101a electric property coupling that its electropositive end links to each other with the 3rd conductive arm 102a by lead.Under "on" position, electric current is imported by positive conducting end 101a, in regular turn by the 3rd chip 30c, the second chip 30b and the first chip 30a, is derived by negative conducting end 101c.
In the present invention, the position of described positive and negative conducting end and shape can be unrestricted, and it can be arranged at arbitrary side of conductive arm, can be one-body molded with conductive arm, and by any two ends extension of conductive arm, also can be by electric conductor and conductive arm electric property coupling.
With reference to shown in Figure 4, in the embodiment two of support of the present invention, when support 10 was plural groups, described support was connected in line in twos, formed the first groups of holders 10a, and the groups of holders number among the described first groups of holders 10a can be provided with as required.
See also Fig. 5, the circuit framework schematic diagram that Fig. 5 is connected in parallel to each other for m pack support 10.As shown in Figure 5, suppose that the 10 groups of numbers of support among the one first groups of holders 10a are the m group, when then wherein the first chip 30a on a support 10, the second chip 30b and the 3rd chip 30c connected mutually, two stands 10 was parallel with one another arbitrarily.Positive and negative conducting end after positive and negative conducting end after connecting mutually with the chip on the above-mentioned support 10 is again connected mutually with the chip on another support 10 respectively is parallel with one another; At last, by one or more groups positive and negative conducting end and external power source electric property coupling.In like manner, during with above-mentioned same way as m pack support 10 in parallel, the circuit of each core assembly sheet promptly can be shown in Figure 5.Further explanation, the electrically connect mode of the parallel connection shown in Fig. 5 promptly is same as first conductive arm 102a shown in above-mentioned Fig. 3 and the 3rd conductive arm 102c, and the positive and negative electrical end shown in Fig. 5 also is same as positive conducting end 101a shown in above-mentioned Fig. 3 and negative conducting end 101c respectively.
With reference to Fig. 6 and shown in Figure 7, in the embodiment three of support of the present invention, in order to improve the working (machining) efficiency of chip-packaging structure, also can the one-body molded second groups of holders 10b, form by the many groups of first groups of holders 10a that are arranged parallel to each other among the described second groups of holders 10b, process the more needs of multicore sheet 30 simultaneously to satisfy.
With reference to shown in Figure 8, in another embodiment of the present invention, but also space of a plurality of encapsulating housing 20 can take shape on the support 10 independently of each other by the mode of ejection formation respectively.In the present invention, described support 10 can adopt having mercy on property electric conducting material to make, as copper, platinum, aluminium, iron etc., plastic having mercy on property encapsulating structure.In having mercy on property encapsulating structure, do not connect between each encapsulating housing 20, crooked with the bending of support, can be applicable to have the decoration of the object of certain curvature, its manufacture method is identical with rectilinear LED encapsulation module, has simplified manufacturing process.
With reference to shown in Figure 9, encapsulating housing 20 is made for insulating material, as plastics, pottery, boron nitride (BN), aluminium nitride (AlN), carbonization sial (SiCAl) etc.The bottom of encapsulating housing 20 offers opening 202, and chip 30 is installed on the support 10 by described opening 202.The internal perisporium of encapsulating housing 20 is formed with the reflection region 203 of annular, preferred taper, described reflection region 203 can be formed by high reflecting material, as fluorescent material, pottery, paint, plastics or reflective metal (silver, aluminium) etc., with the brightness that improves the outside scattering of chip 30 issued lights and improve the LED light emitting source.Form a cavity 204 in the encapsulating housing 20, chip 30 is arranged in the cavity 204 of encapsulating housing 20, and by electric lead 40 and described each conductive arm 102 electric property coupling.In the present invention, electric property coupling between chip 30 and the support 10 relation is unrestricted, also can adopt inverse bonding chip technology (Flip-chip) by conducting terminal with chip 30 and support 10 electric property couplings.
In the present invention, can also omit encapsulating housing 20, then chip 30 directly is packaged on the described support 10.Chip 30 preferred led chips are appreciated that chip-packaging structure of the present invention is also applicable to the encapsulation of other electronic components.
The present invention also provides a kind of manufacture method of chip-packaging structure, and it may further comprise the steps:
At least one support of step 1) moulding or groups of holders, in groups of holders, described support is connected in line in twos, and each support comprises the three groups of conductive arms at interval that are parallel to each other, and each conductive arm is provided with the electric connection point;
Step 2) installing chip on described support, described chip electrically connects the formed chip encapsulating structure by electrically connecting point with conductive arm.
Below describe manufacture method of the present invention in detail.
In step 1), at first, choose metallic plate; Then, metallic plate is put into molding press punch forming described at least one support 10 (as shown in Figure 2) or groups of holders 10a, 10b.In order to improve the working (machining) efficiency of chip-packaging structure, to make more core assembly chip packages simultaneously, with reference to shown in Figure 4, in groups of holders 10a, described support 10 is connected in line in twos; With reference to shown in Figure 6, in groups of holders 10b, include a plurality of groups of holders 10a that are arranged parallel to each other, in same groups of holders 10a, described support 10 is connected in line in twos.
In step 2) in, by welding or gluing mode installing chip on described support 10, make described chip electrically connect with each conductive arm by electrically connecting point, wherein two groups of conductive arms can electrically connect with external power source.
In a preferred embodiment of the invention, also can further comprise step 3): support or groups of holders are placed on the mould of injection molding machine, ejection formation encapsulating housing 20 on described support or groups of holders makes described chip 30 be contained among the described encapsulating housing 20.
With reference to shown in Figure 8, moulding encapsulating housing group 200, described encapsulating housing is injection molded by plastic material, dig a cavity 204 at the middle part of each encapsulating housing 20, the internal perisporium of cavity 204 is shaped to smooth taper surface, a plurality of chips 30 are inserted respectively in the cavity 204 of each encapsulating housing 20, be fixed on the support 10, and pass through electric lead 40 each chip 30 and support 10 electric property couplings; Then, inject colloid by the hole for injecting glue (not indicating) of encapsulating housing 20 in cavity 204, as resin, colloid riddles in the cavity 204, with chip 30 encapsulation, thus moulding chip-packaging structure of the present invention.
Wherein, the moulding order of the installation of described chip and encapsulating housing is replaceable, also can first moulding encapsulating housing, again with Chip Packaging in encapsulating housing, and be electrically connected with support.
In another preferred embodiment of the present invention, described step 2) and between the step 3) can further include step 21), be formed with reflection region 203 on the internal perisporium of encapsulating housing 20, reflection region 203 can form as silver, aluminium etc. by electroplating reflective metal.
In another preferred embodiment of the present invention, in order to obtain the some groups of chip-packaging structures that are parallel to each other, also can further comprise step 4): the number of chip 30 is cut described groups of holders 10b as required, the promptly plastic finished product that includes at least one core assembly chip package.
The above person of thought, it only is preferred embodiment of the present invention, when not limiting scope of the invention process with this, promptly the content of putting down in writing according to claim of the present invention and description of the invention has generally been done simple equivalent and is changed and modify, and all still belongs within the claim of the present invention institute covering scope.

Claims (7)

1. chip-packaging structure, it comprises: at least one support and at least one chip, it is characterized in that: described support comprises the three groups of conductive arms at interval that are parallel to each other: first conductive arm, second conductive arm and the 3rd conductive arm, be respectively equipped with the electric connection point on three groups of conductive arms, wherein, electric connection point on first conductive arm and the 3rd conductive arm can electrically connect with external power source, the electric connection point of at least one second conductive arm can electrically connect with the electric connection point on first conductive arm and the 3rd conductive arm, and described chip electrically connects point and electrically connects with conductive arm by each; Wherein, this chip-packaging structure also includes a plurality of encapsulating housings, and described encapsulating housing coats this support, and described chip is arranged at respectively in the described encapsulating housing, and the internal perisporium of described encapsulating housing is formed with reflection region.
2. chip-packaging structure according to claim 1 is characterized in that: described chip is a plurality of, and each chip is cascaded mutually.
3. chip-packaging structure according to claim 1 is characterized in that: described support is a plurality of, and described a plurality of supports link to each other in line in twos, forms groups of holders.
4. chip-packaging structure according to claim 3 is characterized in that: described groups of holders is a plurality of, and described a plurality of groups of holders are arranged parallel to each other.
5. chip-packaging structure according to claim 1 is characterized in that: described support is made by having mercy on property electric conducting material.
6. chip-packaging structure according to claim 1 is characterized in that: described a plurality of encapsulating housings link to each other or the space in twos.
7. the manufacture method of a chip-packaging structure is characterized in that may further comprise the steps:
At least one support of step 1) moulding or groups of holders, in groups of holders, described support is connected in line in twos, and each support comprises the three groups of conductive arms at interval that are parallel to each other, and each conductive arm is provided with the electric connection point;
Step 2) installing chip on described support, described chip electrically connects with conductive arm by electrically connecting point; Wherein, in step 2) encapsulating housing that is formed with a reflection region internal perisporium before coats this support or groups of holders, and in step 2) in the cavity of encapsulating housing, inject colloid by the hole for injecting glue of encapsulating housing afterwards, colloid is riddled in the cavity, thereby the formed chip encapsulating structure, described chip is arranged in the described encapsulating housing.
CN2008101988978A 2008-09-25 2008-09-25 Chip packaging construction and manufacturing method therefor Expired - Fee Related CN101364585B (en)

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CN2008101988978A CN101364585B (en) 2008-09-25 2008-09-25 Chip packaging construction and manufacturing method therefor
US12/457,563 US8319245B2 (en) 2008-09-25 2009-06-16 Lead frame, and light emitting diode module having the same
US12/585,715 US8089140B2 (en) 2008-09-25 2009-09-23 Lead frame assembly, lead frame and insulating housing combination, and led module having the same
US13/651,516 US20130037845A1 (en) 2008-09-25 2012-10-15 Lead frame, and light emitting diode module having the same

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US20130037845A1 (en) 2013-02-14
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US8319245B2 (en) 2012-11-27

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