CN101359654A - Structure of semiconductor component-buried loading board and preparation thereof - Google Patents
Structure of semiconductor component-buried loading board and preparation thereof Download PDFInfo
- Publication number
- CN101359654A CN101359654A CNA2007101398406A CN200710139840A CN101359654A CN 101359654 A CN101359654 A CN 101359654A CN A2007101398406 A CNA2007101398406 A CN A2007101398406A CN 200710139840 A CN200710139840 A CN 200710139840A CN 101359654 A CN101359654 A CN 101359654A
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- semiconductor element
- layer
- semiconductor component
- buried
- loading plate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a bearing plate embedded with semiconductor elements and a fabrication method thereof, providing a bearing plate and at least one semiconductor element. The bearing plate has a first surface, an opposite second surface and at least one through opening, and each semiconductor element has an active face and an opposite inactive face. A plurality of electrode pads are arranged on the active face and a plurality of concave parts are arranged on the inactive face. An adhesion layer is arranged on the second surface of the bearing plate to seal one end of the opening of the bearing plate. Thus, each semiconductor element can be housed in the opening of the bearing plate, with the inactive face connected to the adhesion layer, so that the adhesion layer can be filled in the concave parts and the gaps between the opening of the bearing plate and the semiconductor elements, thereby reducing the possibility of delamination of the semiconductor elements and the adhesion layer and furthermore improving the combination of the semiconductor elements and the bearing plate.
Description
Technical field
The present invention relates to a kind of structure and method for making thereof of semiconductor component-buried loading board, refer to that especially a kind of non-active surface of semiconductor element forms structure and the method for making thereof that recess is imbedded loading plate again.
Background technology
With the development trend of modern times compactization of various electronic product, the semiconductor industry be with in the semiconductor component-buried highdensity dimensional packaged circuit board with in response to this trend.
See also Fig. 1, imbed the cutaway view of the structure of circuit board, comprising: semiconductor element 11, loading plate 12 and adhesion layer 13 for having semiconductor element now; Wherein, this loading plate 12 is a circuit board or insulation board, and have a first surface 12a and second surface 12b, and be formed with at least one opening 120 that runs through this first surface 12a and second surface 12b, form this adhesion layer 13 in the second surface 12b of this loading plate 12, and this semiconductor element 11 has active surface 11a and with respect to the non-active surface 11b of this active surface 11a, on this active surface 11a, be formed with a plurality of electric connection pads 110, and the non-active surface 11b that makes this semiconductor element 11 connects and places this adhesion layer 13 surfaces, and this adhesion layer 13 is filled in the gap of this loading plate 12 and semiconductor element 11, thereby so that this semiconductor element 11 is bonded in the opening 120 of this loading plate 12.
Yet, for aforesaid structure, the semiconductor element 11 that is embedded in this loading plate 12 is to be combined in this opening 120 by adhesion layer 13, since with the non-active surface 11b of the semiconductor element 11 of these adhesion layer 13 gluings be level and smooth surface, cause this semiconductor element 11 not high with the bond strength of this adhesion layer 13, make in the successive process, this semiconductor element 11 and this adhesion layer 13 are easily because of the coefficient of expansion (Coefficient of thermal expansion, the phenomenon of difference CTE) thereby generation layering, also reduce simultaneously the bond strength of this semiconductor element 11 and loading plate 12, and the reduction meeting of this kind lamination and bond strength directly influences the yield and the reliability of semiconductor product, therefore limits semiconductor component-buried loading board to form the development of structure piece installing.
Therefore, how to reduce the layering possibility of semiconductor element and adhesion layer, and then promote the associativity of semiconductor element and circuit board, become the major issue of present semiconductor industry.
Summary of the invention
In view of the defective of aforementioned prior art, main purpose of the present invention provides a kind of structure and method for making thereof of semiconductor component-buried loading board, must reduce the layering possibility of semiconductor element and adhesion layer, and then promotes the associativity of semiconductor element and loading plate.
Another object of the present invention provides a kind of structure and method for making thereof of semiconductor component-buried loading board, does well out of follow-up manufacture of semiconductor, and then promotes product yield and reliability.
Be the purpose that achieves the above object and other is relevant, the invention provides a kind of method for making of structure of semiconductor component-buried loading board, comprise: a loading plate and at least one semiconductor element are provided, this loading plate has first and second relative surface, and at least one this first and second surperficial opening of running through, and this semiconductor element has the non-active surface of active surface and relative this active surface, is provided with a plurality of electronic padses in this active surface, and is formed with a plurality of recesses on this non-active surface; Second surface in this loading plate forms an adhesion layer to seal an end of this loading plate opening; And this semiconductor element is placed in the opening of this loading plate, and this non-active surface that is formed with a plurality of recesses is connect place on this adhesion layer, and this adhesion layer is filled in the gap of the recess of this semiconductor element and this loading plate and semiconductor element.
In addition in above-mentioned method for making again can with one for example the protective layer of metal level be formed at the outer surface of this adhesion layer; And the groove of the recess of this semiconductor element for being cut by cutting tool or forming via etching, this groove are wherein one of lateral trench, longitudinal groove, oblique groove and intersection trench institute cohort group; This semiconductor element is active member or passive device; This loading plate is insulation board, metallic plate or the circuit board with circuit; This adhesion layer is a dielectric layer or adhesion material.
Again, method for making of the present invention, be included in the first surface of this loading plate and the active surface of semiconductor element again and form a circuit layer reinforced structure, and be formed with a plurality of conductive structures in this circuit layer reinforced structure to be electrically connected to the electronic pads of this semiconductor element, and be formed with electric connection pad in this circuit layer reinforced structure surface, and form a welding resisting layer in this circuit layer reinforced structure surface, and this welding resisting layer surface has a plurality of openings, thereby to expose the electric connection pad of this circuit layer reinforced structure; And this circuit layer reinforced structure includes dielectric layer, is stacked and placed on the line layer on this dielectric layer, and is formed at the conductive structure in this dielectric layer.
The present invention provides a kind of structure of semiconductor component-buried loading board again, comprising: a loading plate, have opposite first and second surface, and at least one this first and second surperficial opening of running through; At least one semiconductor element places this opening, and this semiconductor element has relative active surface and non-active surface, is provided with a plurality of electronic padses in this active surface, and is provided with a plurality of recesses in this non-active surface; And an adhesion layer, be formed at the second surface of this loading plate and the non-active surface of this semiconductor element, and be filled in the gap of running through opening and semiconductor element of the recess of this semiconductor element and this loading plate.
The groove of the recess of the non-active surface of this semiconductor element for being cut by cutting tool or forming via etching, and this groove is wherein one of lateral trench, longitudinal groove, oblique groove, a group that intersection trench is formed.
Therefore, the structure of semiconductor component-buried loading board of the present invention and method for making, be that non-active surface prior to semiconductor element forms a plurality of recesses, be filled in the recess of this semiconductor element again by adhesion layer, and in the gap of the opening of this loading plate and semiconductor element, this semiconductor element is bonded among the loading plate.Because the non-active surface of this semiconductor element has recess, this has promptly increased the bonded area of semiconductor element and adhesion layer, that is, improved the adhesion between semiconductor element and adhesion layer, thereby in the checking of follow-up manufacture of semiconductor and reliability, the semiconductor element of imbedding loading plate promptly is difficult for because of causing the phenomenon of delamination with the adhesion layer coefficient of expansion (CTE) difference excessive (being that stress is excessive).
Description of drawings
Fig. 1 imbeds the cutaway view of the structure of loading plate for existing semiconductor element; And
Fig. 2 A to Fig. 2 E is the manufacturing process cutaway view of the structure and the method for making thereof of semiconductor component-buried loading board of the present invention.
The component symbol explanation
11,22 semiconductor elements
11a, 22a active surface
The non-active surface of 11b, 22b
110,254 electric connection pads
12,21 loading plates
12a, 21a first surface
12b, 21b second surface
120,210 openings
13,23 adhesion layers
220 electronic padses
221 recesses
24 protective layers
25 circuit layer reinforced structures
251 dielectric layers
252 line layers
253 conductive structures
26 welding resisting layers
260 perforates
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
See also Fig. 2 A to Fig. 2 E, describe the method for making of the structure of semiconductor component-buried loading board of the present invention in detail.
At first, see also Fig. 2 A and Fig. 2 B, it shows a loading plate 21 provided by the present invention and semiconductor element 22; Wherein, this loading plate 21 has opposite first 21a and second surface 21b, and at least one opening 210 that runs through this first surface 21a and second surface 21b, and this semiconductor element 22 has the non-active surface 22b of active surface 22a and relative this active surface 22a, and this active surface 22a is provided with a plurality of electronic padses 220; This semiconductor element 22 is an active member or passive device, and this loading plate 21 is an insulation board, metallic plate or the circuit board with circuit.
In addition form a plurality of recesses 221, and form adhesion layer 23 just like dielectric layer or adhesion material to seal an end of this loading plate opening 210 in the second surface 21b of this loading plate 21 in the non-active surface 22b of this semiconductor element 22.
The aforementioned recess 221 that is formed at the non-active surface 22b of this semiconductor element 22 is via the cutting tool cutting of mechanical type or laser light or the groove that forms via etching, this groove can be for lateral trench, longitudinal groove, oblique groove, intersection trench, also or be aforementioned groove institute cohort group, but its shape is not to exceed with aforementioned, and the size and location of this groove also can be according to actual demand elastic registration.
See also Fig. 2 C; this semiconductor element 22 is placed in the opening 210 of this loading plate 21; and the non-active surface 22b that makes this semiconductor element 22 be formed with a plurality of recesses 221 connects and places this adhesion layer 23 surfaces; this semiconductor element 22 has active surface 22a can be formed with protective layer (figure does not show) again; make by pressure programming in the gap of opening 210 that this adhesion layer 23 is filled in the recess 221 of this semiconductor element 22 and this loading plate 21 and semiconductor element 22; thereby this semiconductor element 22 is fixed in the opening 210 of this loading plate 21, removes protective layer to expose the active surface 22a of this semiconductor element 22.
Because the non-active surface 22b of this semiconductor element 22 has recess 221, make this semiconductor element 22 by the associativity of this recess 221, to avoid the excessive phenomenon that causes delamination of the coefficient of expansion (CTE) difference with increase and this adhesion layer 23.
In addition, see also Fig. 2 D, in addition can form the protective layer 24 of metal level for example in the outer surface of this adhesion layer 23.
Then, see also Fig. 2 E, form a circuit layer reinforced structure 25 in the first surface 21a of this loading plate 21 and the active surface 22a of this semiconductor element 22 again, this circuit layer reinforced structure 25 includes dielectric layer 251, be stacked and placed on the line layer 252 on this dielectric layer 251, and be formed at conductive structure 253 in this dielectric layer 251, and this conductive structure 253 is electrically connected to the electronic pads 220 of this semiconductor element 22, and be formed with electric connection pad 254 in these circuit layer reinforced structure 25 surfaces, form a welding resisting layer 26 in these circuit layer reinforced structure 25 surfaces again, and these welding resisting layer 26 surfaces have a plurality of perforates 260, thereby with the electric connection pad 254 that appears circuit layer reinforced structure 25, this electric connection pad 254 other conducting elements of power supply property connection (expression in graphic), by this conducting element with electrical other electronic installation.
By aforesaid method for making, the present invention also provides a kind of structure of semiconductor component-buried loading board, shown in Fig. 2 D, this structure mainly comprises: a loading plate 21, as insulation board, metallic plate or have the circuit board of circuit, and this loading plate 21 has opposite first 21a and second surface 21b, and at least one opening 210 that runs through this first surface 21a and second surface 21b; At least one semiconductor element 22 as active member or passive device, this semiconductor element 22 has relative active surface 22a and non-active surface 22b, establish a plurality of electronic padses 220 in this active surface 22a, and be provided with a plurality of recesses 221 in this non-active surface 22b, and this semiconductor element 22 is to be placed in the opening 210 of this loading plate 21 with its non-active surface 22b; And one adhesion layer 23 be formed at the second surface 21b of this loading plate 21 and the non-active surface 22b of this semiconductor element 22, and in the opening 210 that is filled in the recess 221 of this semiconductor element 22 and this loading plate 21 and the gap of semiconductor element 22, thereby so that this semiconductor element 22 is fixed in the opening 210 of this loading plate 21.
Therefore, the structure of semiconductor component-buried loading board of the present invention and method for making, be that non-active surface prior to semiconductor element forms a plurality of recesses, again by being filled in the recess of this semiconductor element, and the adhesion layer in the gap of this loading plate opening and semiconductor element is to be bonded to this semiconductor element in the loading plate.Because the non-active surface of this semiconductor element has recess, and can increase the bonded area of semiconductor element and adhesion layer, improve the associativity between semiconductor element and the adhesion layer, and then promote the adhesion between semiconductor element and loading plate.Thereby increase in follow-up circuit during manufacture of semiconductor such as layer and reliability detect, imbed semiconductor element in this loading plate promptly be difficult for because of with the excessive lamination that causes of the adhesion layer coefficient of expansion (CTE) difference, be beneficial to of the development of semiconductor component-buried loading board structure with the piece installing of formation structure.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention should be foundation with the scope of claims.
Claims (16)
1. the structure of a semiconductor component-buried loading board comprises:
One loading plate has a first surface and second surface, and at least one this first and second surperficial opening of running through;
At least one semiconductor element places this opening, and this semiconductor element has an active surface and relative non-active surface, is provided with a plurality of electronic padses in this active surface, and is provided with a plurality of recesses in this non-active surface; And
One adhesion layer is located at the second surface of this loading plate and the non-active surface of this semiconductor element, and is filled in the gap of the opening of the recess of this semiconductor element and this loading plate and semiconductor element.
2. the structure of semiconductor component-buried loading board according to claim 1 comprises a protective layer again, is formed at the outer surface of this adhesion layer.
3. the structure of semiconductor component-buried loading board according to claim 2, wherein, this protective layer is a metal level.
4. the structure of semiconductor component-buried loading board according to claim 1, wherein, this loading plate is wherein one of insulation board, metallic plate and the circuit board with circuit.
5. the structure of semiconductor component-buried loading board according to claim 1, wherein, this adhesion layer is wherein one of a dielectric layer and an adhesion material.
6. the structure of semiconductor component-buried loading board according to claim 1, comprise a circuit layer reinforced structure again, be formed at the first surface of this loading plate and the active surface of semiconductor element, and be formed with a plurality of conductive structures in this circuit layer reinforced structure being electrically connected to the electronic pads of this semiconductor element, and be formed with electric connection pad in this circuit layer reinforced structure surface.
7. the structure of semiconductor component-buried loading board according to claim 6 comprises a welding resisting layer again, is formed at this circuit layer reinforced structure surface, and this welding resisting layer surface has a plurality of perforates, thereby to appear the electric connection pad of circuit layer reinforced structure.
8. the structure of semiconductor component-buried loading board according to claim 6, wherein, this circuit layer reinforced structure includes dielectric layer, is stacked and placed on the line layer on this dielectric layer, and is formed at the conductive structure in this dielectric layer.
9. the method for making of the structure of a semiconductor component-buried loading board comprises:
At least one loading plate and semiconductor element are provided, this loading plate has first and second surface, and at least one this first and second surperficial opening of running through, and this semiconductor element has an active surface and relative non-active surface, be provided with a plurality of electronic padses in this active surface, and be provided with a plurality of recesses in this non-active surface;
Second surface in this loading plate forms an adhesion layer to seal an end of this loading plate opening; And
Semiconductor element is placed in the opening of this loading plate, this non-active surface that is formed with a plurality of recesses is connect place this adhesion layer surface, and this adhesion layer is filled in the gap of the recess of this semiconductor element and this loading plate and semiconductor element.
10. the method for making of the structure of semiconductor component-buried loading board according to claim 9 is included in this adhesion layer outer surface again and is formed with a protective layer.
11. the method for making of the structure of semiconductor component-buried loading board according to claim 10, wherein, this protective layer is a metal level.
12. the method for making of the structure of semiconductor component-buried loading board according to claim 9, wherein, this loading plate is wherein one of insulation board, metallic plate and the circuit board with circuit.
13. the method for making of the structure of semiconductor component-buried loading board according to claim 9, wherein, this adhesion layer is wherein one of a dielectric layer and an adhesion material.
14. the method for making of the structure of semiconductor component-buried loading board according to claim 9, be included in the first surface of this loading plate and the active surface of semiconductor element again and form a circuit layer reinforced structure, and be formed with a plurality of conductive structures in this circuit layer reinforced structure being electrically connected to the electronic pads of this semiconductor element, and be formed with electric connection pad in this circuit layer reinforced structure surface.
15. the method for making of the structure of semiconductor component-buried loading board according to claim 14 is included in this circuit layer reinforced structure surface again and forms a welding resisting layer, and this welding resisting layer surface has a plurality of perforates, thereby to appear the electric connection pad of circuit layer reinforced structure.
16. the method for making of the structure of semiconductor component-buried loading board according to claim 14, wherein, this circuit layer reinforced structure includes dielectric layer, is stacked and placed on the line layer on this dielectric layer, and is formed at the conductive structure in this dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710139840A CN100576532C (en) | 2007-08-02 | 2007-08-02 | The structure of semiconductor component-buried loading board and method for making thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710139840A CN100576532C (en) | 2007-08-02 | 2007-08-02 | The structure of semiconductor component-buried loading board and method for making thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101359654A true CN101359654A (en) | 2009-02-04 |
| CN100576532C CN100576532C (en) | 2009-12-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200710139840A Active CN100576532C (en) | 2007-08-02 | 2007-08-02 | The structure of semiconductor component-buried loading board and method for making thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386108A (en) * | 2010-08-31 | 2012-03-21 | 新科金朋有限公司 | Semiconductor device and method of forming adhesive material over semiconductor die and carrier |
| CN102869220A (en) * | 2012-09-25 | 2013-01-09 | 昆山市浩坤机械有限公司 | Electric component reinforcing structure |
| CN104979260A (en) * | 2014-04-03 | 2015-10-14 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package and support used by same |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2967697B2 (en) * | 1994-11-22 | 1999-10-25 | ソニー株式会社 | Lead frame manufacturing method and semiconductor device manufacturing method |
| US6277672B1 (en) * | 1999-09-03 | 2001-08-21 | Thin Film Module, Inc. | BGA package for high density cavity-up wire bond device connections using a metal panel, thin film and build up multilayer technology |
| JP4502564B2 (en) * | 1999-12-24 | 2010-07-14 | 富士通株式会社 | Semiconductor device having flip-chip mounted semiconductor bare chip, and substrate member with thin film structure capacitor for flip-chip mounted semiconductor bare chip |
| US20030197285A1 (en) * | 2002-04-23 | 2003-10-23 | Kulicke & Soffa Investments, Inc. | High density substrate for the packaging of integrated circuits |
| CN100530574C (en) * | 2003-03-31 | 2009-08-19 | 三洋电机株式会社 | Semiconductor module and its manufacturing method |
| JP4129837B2 (en) * | 2003-06-03 | 2008-08-06 | 松下電器産業株式会社 | Manufacturing method of mounting structure |
| CN100576476C (en) * | 2005-11-25 | 2009-12-30 | 全懋精密科技股份有限公司 | Chip buried in semiconductor encapsulation base plate structure and method for making thereof |
-
2007
- 2007-08-02 CN CN200710139840A patent/CN100576532C/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386108A (en) * | 2010-08-31 | 2012-03-21 | 新科金朋有限公司 | Semiconductor device and method of forming adhesive material over semiconductor die and carrier |
| CN102869220A (en) * | 2012-09-25 | 2013-01-09 | 昆山市浩坤机械有限公司 | Electric component reinforcing structure |
| CN104979260A (en) * | 2014-04-03 | 2015-10-14 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package and support used by same |
| CN104979260B (en) * | 2014-04-03 | 2019-02-12 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package and support used by same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100576532C (en) | 2009-12-30 |
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