CN104979260B - Method for manufacturing semiconductor package and support used by same - Google Patents
Method for manufacturing semiconductor package and support used by same Download PDFInfo
- Publication number
- CN104979260B CN104979260B CN201410150412.3A CN201410150412A CN104979260B CN 104979260 B CN104979260 B CN 104979260B CN 201410150412 A CN201410150412 A CN 201410150412A CN 104979260 B CN104979260 B CN 104979260B
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- insulating layer
- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 75
- 238000002360 preparation method Methods 0.000 claims description 37
- 238000012545 processing Methods 0.000 claims description 23
- 239000004744 fabric Substances 0.000 claims description 15
- 239000011230 binding agent Substances 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 5
- 230000003447 ipsilateral effect Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 9
- 238000000576 coating method Methods 0.000 description 8
- 238000003825 pressing Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 230000032798 delamination Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- XLTRGZZLGXNXGD-UHFFFAOYSA-N benzene;1h-pyrazole Chemical compound C=1C=NNC=1.C1=CC=CC=C1 XLTRGZZLGXNXGD-UHFFFAOYSA-N 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A method for preparing semiconductor package includes providing a package body with insulation layer and at least one semiconductor component embedded in said insulation layer, said semiconductor component having opposite active surface and non-active surface, said insulation layer having opposite first surface and second surface, said first surface being at same side of said active surface and said second surface being formed with at least one recess; then, forming a filling material in the concave part; and forming a circuit redistribution structure on the semiconductor element and the insulating layer. The filling material is used for filling the concave part to improve the flatness of the second surface of the insulating layer.
Description
Technical field
The present invention relates to a kind of preparation method of semiconductor package part, espespecially a kind of semiconductor packages that can promote processing procedure reliability
The preparation method of part and its supporting element used.
Background technique
With flourishing for electronic industry, electronic product is also gradually marched toward multi-functional, high performance trend.In order to meet
The package requirements of (miniaturization) are miniaturized in semiconductor package part, develop the skill for being fanned out to the encapsulation of (fan out) type
Art.
It is the diagrammatic cross-section of the preparation method of existing fan-out-type semiconductor package part such as Figure 1A to Fig. 1 E.
As shown in Figure 1A, a load-bearing part 10 is provided, and there is adhesion coating 101 on the load-bearing part 10.Then, multiple half are put
Conductor assembly 12 is on the adhesion coating 101, those semiconductor subassemblies 12 have opposite active surface 12a and non-active face 12b, respectively
Multiple electrode pads 120 are all had on active surface 12a, and respectively active surface 12a is adhered on the adhesion coating 101.
Due to being limited to board design, so those semiconductor subassemblies 12 can not be laid in the edge of the load-bearing part 10
There is no the semiconductor subassembly 12 on the 10a(i.e. peripheral region of the load-bearing part 10), thus make the outermost semiconductor subassembly 12
Difference of height h is generated between the edge 10a of the load-bearing part 10.In addition, can also generate height between the respectively semiconductor subassembly 12
Poor d.
As shown in Figure 1B, an insulating layer 13 is formed on the adhesion coating 101, to coat the semiconductor subassembly 12, and because of this
The reason of difference of height d, h, the insulating layer 13 generate multiple recess 130,130 '.
As shown in Figure 1 C, one pressing part 11 of pressing makes the insulating layer 13 outbound flow (i.e. to the carrying on the insulating layer 13
The edge 10a of part 10 flows), with the densification insulating layer 13.
As shown in figure iD, after the thermosetting insulating layer 13, then the load-bearing part 10 and adhesion coating 101 are removed, is partly led with exposed this
The active surface 12a of body component 12.
As referring to figure 1E, route redistribution layer (Redistribution layer, RDL) processing procedure is carried out, shape being aligned is passed through
Lu Chongbu structure 14 enables the route weight cloth structure 14 electrically on the active surface 12a of the insulating layer 13 and the semiconductor subassembly 12
Connect the electronic pads 120 of the semiconductor subassembly 12.
Then, an insulating protective layer 15 is formed in the route weight cloth structure 14, and the exposed line of the insulating protective layer 15
The part of the surface of Lu Chongbu structure 14, for combining the conductive component 16 such as solder bump.Later, the pressing part 11 is removed, then
Carry out singulation processing procedure.
However, showing in preparation method with a semiconductor package, when carrying out pressure programming, the reason because of difference of height h is understood, and
The increase of total thickness variations (Total Thickness Variation, TTV) is caused, so in subsequent removal load-bearing part 10
When carrying out RDL processing procedure afterwards, after the thermosetting insulating layer 13, i.e. this is recessed by gap t(between the pressing part 11 and the load-bearing part 10
130) falling into place will increase, and cause the pressing part 11 to fall off (Peeling), and the solvent of processing procedure is easy to enter along gap t
The surface of the insulating layer 13 simultaneously remains in the t of the gap, will also result in the pressing part 11 and falls off (Peeling), as shown in figure iD,
Cause process rate bad.
In addition, because of the difference in height d between each semiconductor subassembly 12, so after pressure programming, the table of the insulating layer 13
Face can generate clathrate, i.e. dent (dent) phenomenon (i.e. the recess 130 '), cause the pressing part 11 and the insulating layer 13 it
Between can generate bubble (void) phenomenon, when causing subsequent progress RDL processing procedure, which falls off.
Therefore, how to overcome above-mentioned problem of the prior art, have become the project for wanting to solve at present in fact.
Summary of the invention
In view of the disadvantages of the above-mentioned prior art, it is an object of the present invention to provide a kind of preparation method of semiconductor package part and
Supporting element used in it, to promote the planarization of the second surface of the insulating layer.
The preparation method of semiconductor package part of the invention a, comprising: packaging body is provided, with insulating layer and is embedded into this absolutely
At least semiconductor component in edge layer, which has opposite active surface and non-active face, and the insulating layer has
There are opposite first surface and second surface, the first surface and the active surface are ipsilateral, and the second surface of the insulating layer is formed
There is an at least recess；Dutchman is formed in the recess；And route weight cloth structure is formed in the semiconductor subassembly and is somebody's turn to do
On insulating layer.
In preparation method above-mentioned, which is set on a load-bearing part, and the active surface of the semiconductor subassembly and the insulating layer
First surface be incorporated on the load-bearing part, to remove the load-bearing part after forming the Dutchman.
In preparation method above-mentioned, which is located at the edge of the second surface of the insulating layer；Alternatively, the recess is located at extremely
Between few two semiconductor subassemblies.
In preparation method above-mentioned, which is blocky or gluey.
In preparation method above-mentioned, the processing procedure of the Dutchman is formed, comprising: provide a support plate with the Dutchman；And
In conjunction with the support plate on the second surface of the insulating layer, it is located at the Dutchman in the recess.For example, the Dutchman with should
Support plate is one of the forming；Alternatively, the Dutchman is the component being placed in the support plate.Also, the Dutchman is by binder course
It is fixed in the recess.
In preparation method above-mentioned, which is set to the active surface of the semiconductor subassembly and the first table of the insulating layer
On face.
It further include forming insulating protective layer to weigh in cloth structure in the route, and the insulating protective layer has in preparation method above-mentioned
There is the aperture of multiple exposed route weight cloth structures.
It further include carrying out singulation processing procedure after forming route weight cloth structure in preparation method above-mentioned.For example, in singulation processing procedure
When, the part that the insulating layer has the recess is removed together；Alternatively, the singulation processing procedure using the position of the corresponding recess as
Cutting path.
In addition, the present invention also provides a kind of supporting elements, comprising: support plate；And Dutchman, it is set in the support plate.
In supporting element above-mentioned, which is one of the forming with the support plate；Alternatively, the Dutchman is to be placed in the branch
Component on fagging.
In supporting element above-mentioned, which is located at the edge of the support plate；Alternatively, the Dutchman is located in the support plate
Between.
In supporting element above-mentioned, which is blocky or gluey.
Further include binder course in supporting element above-mentioned, is set on the support plate and the Dutchman.
From the foregoing, it will be observed that the preparation method of semiconductor package part of the invention, inserts the recess by the Dutchman, to fill up this
The recess of the second surface of insulating layer.Therefore, when carrying out pressure programming, total thickness variations not will increase, and be avoided that hair
Raw bubble phenomenon, so being avoided that generation delamination, and the solvent of processing procedure will not enter when subsequent progress RDL processing procedure
Any surface of the insulating layer, is also avoided that generation delamination, thus can effectively promote process rate.
Detailed description of the invention
Figure 1A to Fig. 1 E is the schematic cross-sectional view of existing preparation method with a semiconductor package；
Fig. 2A to Fig. 2 F is the schematic cross-sectional view of the preparation method of semiconductor package part of the invention；Wherein, Fig. 2 F ' is Fig. 2 F's
Another method；And
Fig. 3 A, Fig. 3 A ', Fig. 3 A ", Fig. 3 B and Fig. 3 C be supporting element of the invention different embodiments schematic cross-sectional view.
Symbol description
10,20 load-bearing parts
The edge 10a, 29c
101,201 adhesion coatings
11 pressing parts
12,22 semiconductor subassemblies
12a, 22a active surface
The non-active face 12b, 22b
120,220 electronic pads
13,23 insulating layers
130,130 ', 230,230 ' recess
14,24 routes weight cloth structure
15,25 insulating protective layers
16,26 conductive components
2 semiconductor package parts
2a packaging body
200 support plates
21 support plates
210,210 ', 310,310 ', 310 " Dutchmans
211 binder courses
23a first surface
23b second surface
240 dielectric layers
241 line layers
3,3 ', 3 " supporting elements
H, d difference of height
The horizontal imaginary line of L
S, S ' cutting path
The gap t.
Specific embodiment
Illustrate embodiments of the present invention by particular specific embodiment below, those skilled in the art can be by this explanation
The revealed content of book understands further advantage and effect of the invention easily.
It should be clear that this specification structure depicted in this specification institute accompanying drawings, ratio, size etc., are only used for cooperation specification and are taken off
The content shown is not intended to limit the enforceable qualifications of the present invention, institute for the understanding and reading of those skilled in the art
Not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing this hair
Under bright the effect of can be generated and the purpose that can reach, it should all still fall in disclosed technology contents and obtain and can cover
In range.Meanwhile cited such as "upper", " first ", " second " and " one " term in this specification, it is also only convenient for narration
Be illustrated, not for limiting the scope of the invention, relativeness is altered or modified, without essence change technology
It inside holds, when being also considered as the enforceable scope of the present invention.
Fig. 2A to Fig. 2 F is the diagrammatic cross-section of the preparation method of semiconductor package part 2 of the invention.
As shown in Figure 2 A, a load-bearing part 20 is provided, and multiple semiconductor subassemblies 22 are set on the load-bearing part 20.
In this present embodiment, the size of the load-bearing part 20 can select wafer type substrate (Wafer form on demand
Substrate) or general panel type substrate (Panel form substrate), and it is glass that the load-bearing part 20, which may include a material,
Glass, metal, ceramics or semiconductor crystal wafer support plate 200, and a release layer (figure omits) and one viscous has been sequentially formed on the support plate 200
Layer 201.
In addition, each semiconductor subassembly 22 has an opposite active surface 22a and non-active face 22b, on active surface 22a
With multiple electrode pads 220, and active surface 22a is connected on the adhesion coating 201 of the load-bearing part 20.
As shown in Figure 2 B, formed an insulating layer 23 in the load-bearing part 20 adhesion coating 201 and semiconductor subassembly 22 on, with shape
At packaging body 2a, and the semiconductor subassembly 22 is embedded into the insulating layer 23.
In this present embodiment, which has opposite first surface 23a and second surface 23b, the insulating layer 23
Second surface 23b be formed with multiple recess 230,230 '.
In addition, the insulating layer 23 is the film of pressure programming, but in other embodiments, which can also be such as
It is molded packing colloid or the glue material of printing process etc. of processing procedure, so the material or generation type of the insulating layer 23 have no spy
It does not limit.
Also, the first surface 23a of the active surface 22a of the semiconductor subassembly 22 and the insulating layer 23 be it is coplanar, make this
One surface 23a and active surface 22a are ipsilateral.
In addition, the part recess 230 is located at the edge of the second surface 23b of the insulating layer 23, the part recess
230 ' between at least two semiconductor subassemblies 22.
As shown in Figure 2 C, a support plate 21 with multiple Dutchmans 210 is provided, and combines the support plate 21 in the insulation
On the second surface 23b of layer 23, it is located at the Dutchman 210 in the recess 230,230 '.
In this present embodiment, the size of the support plate 21 can select wafer type substrate or general panel type substrate on demand,
Such as support plate 21 is glass plate, metal plate, ceramic version or semiconductor crystal wafer, and preferably, the support plate 21 and the support plate 200
Material it is identical.
In addition, the Dutchman 210 and the support plate 21 are integrally formed, such as the Dutchman 210 is the convex of the support plate 21
Portion, processing procedure is to etch the support plate 21, to form the protrusion, straight mesa-shaped Dutchman 310 as shown in Figure 3A, such as Fig. 3 A '
Shown in taper mesa-shaped Dutchman 310 ', the domatic mesa-shaped Dutchman 310 " as shown in Fig. 3 A ".Alternatively, in other embodiments,
As shown in Figure 3B, which can also be the component additionally adhered in the support plate 21.
Also, Fig. 3 C is referred to together, preferably, the support plate 21 is bound to the insulation by the binder course 211 just like glue material
On the second surface 23b of layer 23, the Dutchman 210 is enable to be fixed in the recess 230 by the binder course 211.
In addition, the Dutchman 210 is hard block (such as metal material) or glue material solidifies shape, but there is no particular restriction.
As shown in Figure 2 D, after the thermosetting insulating layer, the load-bearing part 20 is removed, to expose the active surface of the semiconductor subassembly 22
The first surface 23a of 22a and the insulating layer 23.
As shown in Figure 2 E, RDL processing procedure is carried out, forms a route weight cloth structure 24 in the active surface of the semiconductor subassembly 22
On the first surface 23a of 22a and the insulating layer 23, and the route weight cloth structure 24 is electrically connected those electronic pads 220.
In this present embodiment, which is specifically form a dielectric layer 240 in the active surface of the semiconductor subassembly 22
On 22a and the insulating layer 23, line layer 241 is re-formed on the dielectric layer 240, to be electrically connected those electronic pads 220, is used
Form the route weight cloth structure 24 of tool uniline layer 241.
Then, an insulating protective layer 25 is formed on the dielectric layer 240 and line layer 241, and the insulating protective layer 25 has
There is the aperture of multiple exposed line layers 241, to form the conductive component 26 such as solder bump in the tapping.
Also, the material of the dielectric layer 240 is, for example, polyimide (Polyimide, PI), benzocyclobutene (Benezocy-
Clobutene, BCB) or it is poly- to diazole benzene (Polybenzoxazole, PBO).
In addition, route weight cloth structure can also be the structure of multilayer line, and it includes multiple dielectrics in other embodiments
Layer 240 and the line layer 241 being formed on the dielectric layer 240.
As shown in Figure 2 F, the support plate 21 and its Dutchman 210 and binder course 211 are removed, then carries out singulation processing procedure, edge
Cutting path S is cut, to make multiple semiconductor package parts 2.Preferably, removing the insulation together when singulation processing procedure
The recess 230,230 ' of layer 23.
In another embodiment, as shown in Fig. 2 F ', which can also correspond to the position of the recess 230,230 '
As cutting path S '.
Therefore, which will not be formed on dielectric layer 240 corresponding to the cutting path S, S '.
In preparation method of the invention, by the design of the Dutchman 210, it is recessed that this can be filled up when carrying out pressure programming
Place 230 is fallen into, to flatten the second surface 23b(of the insulating layer 23 horizontal imaginary line L as shown in fig. 2 c), compensate the semiconductor group
Difference of height between part 22 and the load-bearing part 20 makes do not have air between the second surface 23b of the insulating layer 23 and support plate 21
Gap.
Therefore, when carrying out pressure programming, total thickness variations (Total Thickness Variation, TTV) will not increase
Add, and there is no air gap between the support plate 21 and the load-bearing part 20, as shown in Figure 2 C, so in subsequent removal load-bearing part
20 and when carrying out RDL processing procedure, be avoided that the support plate 21 falls off (Peeling), as shown in Fig. 2 D to Fig. 2 E, and processing procedure is molten
Agent will not enter any surface of the insulating layer 23, also be avoided that the support plate 21 falls off, thus can effectively promote process rate.
In addition, the second surface 23b of the insulating layer 23 is flat by the Dutchman 210 after pressure programming, make
Bubble (void) phenomenon will not be generated between the support plate 21 and the insulating layer 23, so when subsequent progress RDL processing procedure, the branch
Fagging 21 will not fall off.
Also, the support plate 21 is reusable, so cost of manufacture will not be wasted.
The present invention also provides a kind of supporting elements 3,3 ', 3 ", as shown in Fig. 3 A, Fig. 3 A ', Fig. 3 A ", Fig. 3 B and Fig. 3 C, comprising:
One support plate 21 and the Dutchman 310,310 ' in the support plate 21,310 ", 210 ', 210.
The Dutchman 310,310 ', 310 ", 210 ', 210 be blocky or gluey.
In an embodiment, the Dutchman 310,310 ', 310 ", 210 is one of the forming with the support plate 21.
In an embodiment, the Dutchman 210 ' is the component being placed in the support plate 21.
In an embodiment, the Dutchman 310,310 ', 310 ", 210 ', 210 is located at the edge of the support plate 21
29c and/or be located at 21 middle of support plate.
In an embodiment, the supporting element 3 " further includes binder course 211, is set to the support plate 21 and the Dutchman
On 210.
In conclusion the preparation method of semiconductor package part of the invention and its supporting element used, mainly utilize the Dutchman
Flatten the second surface of the insulating layer, to avoid occur delamination the problem of.
Above-described embodiment is only used for that the principle of the present invention and its effect is illustrated, and is not intended to limit the present invention.Appoint
What those skilled in the art without departing from the spirit and scope of the present invention, modifies to above-described embodiment.Therefore originally
The rights protection scope of invention, should be as listed in the claims.
Claims (22)
1. a kind of preparation method of semiconductor package part, comprising:
A packaging body is provided, with insulating layer and at least semiconductor component being embedded into the insulating layer, the semiconductor group
Part has opposite active surface and non-active face, and the insulating layer has opposite first surface and second surface, first table
Face and the active surface are ipsilateral, and the second surface of the insulating layer is formed with an at least recess；
One support plate with Dutchman is provided；
In conjunction with the support plate on the second surface of the insulating layer, it is located at the Dutchman in the recess；And
Route weight cloth structure is formed on the semiconductor subassembly and the insulating layer.
2. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the packaging body is set on a load-bearing part,
And the first surface of the active surface of the semiconductor subassembly and the insulating layer is incorporated on the load-bearing part, in formed the Dutchman it
Afterwards, the load-bearing part is removed.
3. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the recess is located at the of the insulating layer
The edge on two surfaces.
4. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the recess be located at least two this partly lead
Between body component.
5. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the Dutchman is bulk.
6. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the Dutchman is glue.
7. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the Dutchman is integrated with the support plate
Forming.
8. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the Dutchman is to be placed in the support plate
On component.
9. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the Dutchman is fixed on by binder course
In the recess.
10. the preparation method of semiconductor package part as described in claim 1, which is characterized in that route weight cloth structure is set to should be partly
On the active surface of conductor assembly and the first surface of the insulating layer.
11. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the preparation method further includes forming insulation to protect
Sheath weighs in cloth structure in the route, and the insulating protective layer has the aperture of multiple exposed routes weight cloth structures.
12. the preparation method of semiconductor package part as described in claim 1, which is characterized in that the preparation method further includes in the formation line
After Lu Chongbu structure, singulation processing procedure is carried out.
13. the preparation method of semiconductor package part as claimed in claim 12, which is characterized in that the preparation method further includes in singulation processing procedure
When, the part that the insulating layer has the recess is removed together.
14. the preparation method of semiconductor package part as claimed in claim 12, which is characterized in that the singulation processing procedure is with the corresponding recess
The position at place is as cutting path.
15. a kind of supporting element, comprising:
Support plate；And
Dutchman is set in the support plate, and to fill up the recess of packaging body, which includes being formed with the recess
Insulating layer and the semiconductor subassembly being embedded into the insulating layer.
16. supporting element as claimed in claim 15, which is characterized in that the Dutchman is one of the forming with the support plate.
17. supporting element as claimed in claim 15, which is characterized in that the Dutchman is the component being placed in the support plate.
18. supporting element as claimed in claim 15, which is characterized in that the Dutchman is located at the edge of the support plate.
19. supporting element as claimed in claim 15, which is characterized in that the Dutchman is located at the support plate middle.
20. supporting element as claimed in claim 15, which is characterized in that the Dutchman is bulk.
21. supporting element as claimed in claim 15, which is characterized in that the Dutchman is glue.
22. supporting element as claimed in claim 15, which is characterized in that the supporting element further includes binder course, is set to the support
On plate and the Dutchman.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103112457A TWI582866B (en) | 2014-04-03 | 2014-04-03 | Manufacturing method of semiconductor package and support element used thereof |
| TW103112457 | 2014-04-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104979260A CN104979260A (en) | 2015-10-14 |
| CN104979260B true CN104979260B (en) | 2019-02-12 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359654A (en) * | 2007-08-02 | 2009-02-04 | 全懋精密科技股份有限公司 | Structure of semiconductor component-buried loading board and preparation thereof |
| CN102324418A (en) * | 2011-08-09 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor component packaging structure and its manufacturing approach |
| CN102956468A (en) * | 2011-08-25 | 2013-03-06 | 英特尔移动通信有限责任公司 | Semiconductor device and method of manufacturing a semiconductor device including grinding steps |
| CN103295978A (en) * | 2012-03-03 | 2013-09-11 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW200919595A (en) * | 2007-10-31 | 2009-05-01 | United Test Ct Inc | Method of manufacturing semiconductor device |
| WO2012121377A1 (en) * | 2011-03-10 | 2012-09-13 | 住友ベークライト株式会社 | Semiconductor device, and process for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359654A (en) * | 2007-08-02 | 2009-02-04 | 全懋精密科技股份有限公司 | Structure of semiconductor component-buried loading board and preparation thereof |
| CN102324418A (en) * | 2011-08-09 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor component packaging structure and its manufacturing approach |
| CN102956468A (en) * | 2011-08-25 | 2013-03-06 | 英特尔移动通信有限责任公司 | Semiconductor device and method of manufacturing a semiconductor device including grinding steps |
| CN103295978A (en) * | 2012-03-03 | 2013-09-11 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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| TW201539592A (en) | 2015-10-16 |
| CN104979260A (en) | 2015-10-14 |
| TWI582866B (en) | 2017-05-11 |
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