TW201539592A - Manufacturing method of semiconductor package and support element used thereof - Google Patents

Abstract

Provided is a manufacturing method of semiconductor package, which includes first providing a package body having at least one insulating layer and a semiconductor element embedded in the insulating layer, wherein the semiconductor element has an active face and a non-active face in opposite position, and the insulating layer has a first surface and a second surface in opposite position, and the first surface and the active face are on the same side, and at least one dent portion is formed on the second surface of the insulating layer; forming a filling material in the dent portion; and forming a redistribution structure on the semiconductor element and the insulating layer. By filling the dent portion with the filling material, the second surface of the insulating layer can be ensured flat.

Description

Semiconductor package manufacturing method and support member thereof

The present invention relates to a method of fabricating a semiconductor package, and more particularly to a method of fabricating a semiconductor package capable of improving process reliability and a support member therefor.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of semiconductor package miniaturization, a technology of fan out type packaging has been developed.

1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional fan-out type semiconductor package.

As shown in FIG. 1A, a carrier 10 is provided, and the carrier 10 has an adhesive layer 101 thereon. Next, a plurality of semiconductor elements 12 are disposed on the adhesive layer 101. The semiconductor elements 12 have opposite active and uninitiated faces 12a, 12b, and each of the active faces 12a has a plurality of electrode pads 120, and each of the active faces 12a is adhered to the adhesive layer 101.

Due to the limitation of the machine design, the semiconductor components 12 cannot be disposed on the edge 10a of the carrier 10 (ie, the surrounding area of the carrier 10). The semiconductor element 12) is absent from the domain, thereby creating a height difference h between the outermost semiconductor component 12 and the edge 10a of the carrier 10. Furthermore, a height difference d is also generated between the semiconductor elements 12.

As shown in Fig. 1B, an insulating layer 13 is formed on the adhesive layer 101 to cover the semiconductor device 12, and the insulating layer 13 generates a plurality of recesses 130, 130' due to the height difference d, h.

As shown in Fig. 1C, a pressing member 11 is press-fitted onto the insulating layer 13, and the insulating layer 13 is caused to flow outward (i.e., to the edge 10a of the carrier member 10) to pressurize the insulating layer 13.

As shown in FIG. 1D, after the insulating layer 13 is thermally cured, the carrier 10 and the adhesive layer 101 are removed, and the active surface 12a of the semiconductor element 12 is exposed.

As shown in FIG. 1E, a circuit redistribution layer (RDL) process is performed to form a line redistribution structure 14 on the insulating layer 13 and the active surface 12a of the semiconductor component 12, so that the circuit is re-wired. The electrode pad 120 of the semiconductor element 12 is electrically connected.

Next, an insulating protective layer 15 is formed on the circuit redistribution structure 14, and the insulating protective layer 15 exposes a portion of the surface of the circuit redistribution structure 14 for bonding the conductive elements 16 such as solder bumps. Thereafter, the pressing member 11 is removed, and then a singulation process is performed.

However, in the manufacturing method of the conventional semiconductor package, when the pressing process is performed, the total thickness variation (TTV) is increased due to the height difference h, so the carrier is subsequently removed. After the RDL process is performed after 10, after the heat insulating of the insulating layer 13, the gap t between the pressing member 11 and the carrier 10 (i.e., the recess 130) is increased. Large, causing the pressing member 11 to fall off (Peeling), and the solvent for the process easily enters the surface of the insulating layer 13 along the slit t and remains in the slit t, which also causes the pressing member 11 to fall off (Peeling) ), as shown in Figure 1D, results in poor process yield.

Moreover, due to the height difference d between the semiconductor elements 12, after the pressing process, the surface of the insulating layer 13 may have a lattice shape, that is, a dent phenomenon (ie, the recess 130'). A void phenomenon is generated between the pressing member 11 and the insulating layer 13, and the pressing member 11 is detached when the RDL process is subsequently performed.

Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

The present invention provides a method of fabricating a semiconductor package, comprising: providing a package having an insulating layer and at least one semiconductor component embedded in the insulating layer, the semiconductor component having The active surface and the inactive surface are opposite to each other, and the insulating layer has opposite first and second surfaces, the first surface is on the same side as the active surface, and the second surface of the insulating layer is formed with at least one recess Forming a fill material in the recess; and forming a line redistribution structure on the semiconductor component and the insulating layer.

In the above method, the package system is disposed on a carrier, and the active surface of the semiconductor component and the first surface of the insulating layer are coupled to the carrier to remove the carrier after forming the filler. .

In the above method, the recess is located on the second surface of the insulating layer The edge; or the recess is located between at least two of the semiconductor elements.

In the above method, the filler material is in the form of a block or a gel.

In the above method, the process of forming the filler comprises: providing a support plate having the filler; and bonding the support plate to the second surface of the insulation layer, such that the filler is located in the depression. For example, the filler material is integrally formed with the support plate; or the filler material is a member placed on the support plate. Further, the filler material is fixed in the recess by a bonding layer.

In the above method, the line redistribution structure is disposed on the active surface of the semiconductor element and the first surface of the insulating layer.

In the above manufacturing method, the insulating layer is formed on the line redistribution structure, and the insulating protection layer has a plurality of openings for exposing the line redistribution structure.

In the above-mentioned manufacturing method, after the formation of the line redistribution structure, the singulation process is performed. For example, in the singulation process, the insulating layer is removed from the portion having the recess; or the singulation process is performed as a cutting path corresponding to the position of the recess.

In addition, the present invention provides a support member, comprising: a support plate; and a filler material, which is attached to the support plate.

In the above support member, the filler material is integrally formed with the support plate; or the filler material is a member placed on the support plate.

In the foregoing support member, the filler material is located at an edge of the support plate; or the filler material is located at the middle of the support plate.

In the aforementioned support member, the filler material is in the form of a block or a gel.

In the foregoing support member, the bonding layer is further included on the support plate and the filling material.

It can be seen from the above that the semiconductor package of the present invention is formed by filling the recess by the filling material to fill the recess of the second surface of the insulating layer. Therefore, when the pressing process is performed, the total thickness variation does not increase, and the bubble phenomenon can be avoided, so that delamination can be avoided in the subsequent RDL process, and the solvent for the process does not enter the insulating layer. Any surface can also avoid delamination, which can effectively improve the process yield.

10,20‧‧‧Carrier

10a, 29c‧‧‧ edge

101,201‧‧‧Adhesive layer

11‧‧‧ Pressing parts

12,22‧‧‧Semiconductor components

12a, 22a‧‧‧ active surface

12b, 22b‧‧‧ inactive surface

120,220‧‧‧electrode pads

13,23‧‧‧Insulation

130,130’,230,230’‧‧‧

14,24‧‧‧Line redistribution structure

15,25‧‧‧Insulation protective layer

16,26‧‧‧ conductive elements

2‧‧‧Semiconductor package

2a‧‧‧Package

200‧‧‧ Carrier Board

21‧‧‧Support board

210,210’,310,310’,310”‧‧‧

211‧‧‧ bonding layer

23a‧‧‧ first surface

23b‧‧‧ second surface

240‧‧‧ dielectric layer

241‧‧‧Line layer

3,3’,3”‧‧‧support

h,d‧‧‧ height difference

L‧‧‧ horizontal imaginary line

S, S’‧‧‧ cutting path

T‧‧‧ gap

1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; and FIGS. 2A to 2F are cross-sectional views showing a method of fabricating the semiconductor package of the present invention; wherein the 2F' is a 2F image Another method; and 3A, 3A', 3A", 3B, and 3C are schematic cross-sectional views of different embodiments of the support of the present invention.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The qualifications are not technically meaningful, and any modification of the structure, change of the proportional relationship or adjustment of the size does not affect the work that can be produced by the present invention. Both the effects and the achievable objectives should still fall within the scope of the technical contents disclosed in the present invention. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2F are schematic cross-sectional views showing a method of fabricating the semiconductor package 2 of the present invention.

As shown in FIG. 2A, a carrier 20 is provided and a plurality of semiconductor components 22 are disposed on the carrier 20.

In this embodiment, the size of the carrier 20 can be selected as a wafer type substrate or a general panel type substrate, and the carrier 20 can include a material of glass or metal. A carrier 200 is mounted on the ceramic or semiconductor wafer, and a release layer (not shown) and an adhesive layer 201 are sequentially formed on the carrier 200.

Moreover, each of the semiconductor elements 22 has an opposite active surface 22a and a non-active surface 22b. The active surface 22a has a plurality of electrode pads 220, and the active surface 22a is attached to the adhesive layer 201 of the carrier 20.

As shown in FIG. 2B, an insulating layer 23 is formed on the adhesive layer 201 of the carrier 20 and the semiconductor device 22 to form the package 2a, and the semiconductor device 22 is embedded in the insulating layer 23.

In this embodiment, the insulating layer 23 has opposite first and second surfaces 23a, 23b, and the second surface 23b of the insulating layer 23 is formed with a plurality of recesses 230, 230'.

In addition, the insulating layer 23 is a film for a press-bonding process. However, in other embodiments, the insulating layer 23 may be, for example, a sealing gel for a molding process or a rubber for a printing process, etc., so the insulating layer 23 The material or formation method is not particularly limited.

Moreover, the active surface 22a of the semiconductor element 22 is coplanar with the first surface 23a of the insulating layer 23 such that the first surface 23a is on the same side as the active surface 22a.

In addition, a portion of the recess 230 is located at an edge of the second surface 23b of the insulating layer 23, and a portion of the recess 230' is located between at least two of the semiconductor elements 22.

As shown in Fig. 2C, a support plate 21 having a plurality of fillers 210 is provided, and the support plate 21 is bonded to the second surface 23b of the insulating layer 23 such that the filler 210 is positioned in the recesses 230, 230'.

In this embodiment, the size of the support plate 21 can be selected as a wafer type substrate or a general panel type substrate, for example, the support plate 21 is a glass plate, a metal plate, a ceramic plate or a semiconductor wafer, and preferably The support plate 21 is made of the same material as the carrier 200.

Furthermore, the filler 210 is integrally formed with the support plate 21. For example, the filler 210 is a convex portion of the support plate 21, and the process is to etch the support plate 21 to form the convex portion, as shown in FIG. 3A. The flat-shaped padding material 310 shown in Fig. 3A is a tapered trap-shaped filler material 310' as shown in Fig. 3A', and the slope-shaped padding material 310" as shown in Fig. 3A". Alternatively, in other embodiments, as shown in Fig. 3B, the filler 210' may also be a member that is additionally attached to the support plate 21.

Moreover, referring to FIG. 3C, preferably, the support plate 21 is bonded to the second surface 23b of the insulating layer 23 by a bonding layer 211 such as a rubber material, so that the filling material 210 can be The bonding layer 211 is fixed in the recess 230.

Further, the filler 210 is a solid block (such as a metal material) or a solidified shape of the rubber, but is not particularly limited.

As shown in FIG. 2D, after the insulating layer is thermally cured, the carrier 20 is removed to expose the active surface 22a of the semiconductor component 22 and the first surface 23a of the insulating layer 23.

As shown in FIG. 2E, the RDL process is performed to form a line redistribution structure 24 on the active surface 22a of the semiconductor component 22 and the first surface 23a of the insulating layer 23, and the circuit redistribution structure 24 is electrically connected. The electrode pads 220.

In this embodiment, the RDL process specifically forms a dielectric layer 240 on the active surface 22a of the semiconductor device 22 and the insulating layer 23, and then forms a wiring layer 241 on the dielectric layer 240 to electrically The electrode pads 220 are connected to form a line redistribution structure 24 having a single circuit layer 241.

Next, an insulating protective layer 25 is formed on the dielectric layer 240 and the wiring layer 241, and the insulating protective layer 25 has a plurality of openings exposing the wiring layer 241 to form a conductive such as solder bumps at the opening. Element 26.

Moreover, the material of the dielectric layer 240 is, for example, Polyimide (PI), Benezocy-clobutene (BCB) or Polybenzoxazole (PBO).

In addition, in other embodiments, the line redistribution structure may also be multiple layers. The structure of the line includes a plurality of dielectric layers 240 and a circuit layer 241 formed on the dielectric layer 240.

As shown in FIG. 2F, the support plate 21 and its filler 210 and the bonding layer 211 are removed, and then a singulation process is performed, and cutting is performed along the cutting path S to fabricate a plurality of semiconductor packages 2. Preferably, the recesses 230, 230' of the insulating layer 23 are removed together during the singulation process.

In another embodiment, as shown in Fig. 2F', the singulation process may also correspond to the position of the recess 230, 230' as the cutting path S'.

Therefore, the wiring layer 241 is not formed on the dielectric layer 240 corresponding to the cutting paths S, S'.

In the manufacturing method of the present invention, the filling material 210 is designed to fill the recess 230 during the pressing process to level the second surface 23b of the insulating layer 23 (as shown in FIG. 2C). The horizontal imaginary line L) is shown to compensate for the height difference between the semiconductor element 22 and the carrier 20 such that there is no air gap between the second surface 23b of the insulating layer 23 and the support plate 21.

Therefore, when the press-bonding process is performed, the total thickness variation (TTV) does not increase, and there is no air gap between the support plate 21 and the carrier 20, as shown in FIG. 2C, so When the RDL process is performed in addition to the carrier 20, the support plate 21 can be prevented from falling off (Peling), as shown in FIGS. 2D to 2E, and the solvent for the process does not enter any surface of the insulating layer 23, and can also be avoided. The support plate 21 is detached, thereby effectively improving the process yield.

Moreover, after the pressing process, the second surface 23b of the insulating layer 23 is flattened by the filling material 210, and the supporting plate 21 is insulated from the insulating plate 21 No void phenomenon occurs between the layers 23, so that the support plate 21 does not fall off during the subsequent RDL process.

Moreover, the support plate 21 can be reused, so that the manufacturing cost is not wasted.

The present invention provides a support member 3, 3', 3", as shown in Figures 3A, 3A', 3A", 3B and 3C, comprising: a support plate 21, and a filling provided on the support plate 21. Materials 310, 310', 310", 210', 210.

The filler material 310, 310', 310", 210', 210 is in the form of a block or a gel.

In one embodiment, the filler material 310, 310', 310", 210 is integrally formed with the support plate 21.

In one embodiment, the filler 210' is a member placed on the support plate 21.

In one embodiment, the filler material 310, 310', 310", 210', 210 is located at the edge 29c of the support plate 21 and/or at the middle of the support plate 21.

In one embodiment, the support member 3 ′′ includes a bonding layer 211 disposed on the support plate 21 and the filling material 210 .

In summary, the method for fabricating the semiconductor package of the present invention and the support member used thereof mainly use the filler material to level the second surface of the insulating layer to avoid the problem of delamination.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as follows. Listed around.

2a‧‧‧Package

20‧‧‧Carrier

200‧‧‧ Carrier Board

201‧‧‧Adhesive layer

21‧‧‧Support board

210‧‧‧Material

211‧‧‧ bonding layer

22‧‧‧Semiconductor components

23‧‧‧Insulation

23a‧‧‧ first surface

23b‧‧‧ second surface

230,230’‧‧‧ Depression

L‧‧‧ horizontal imaginary line

Claims (23)

A method of fabricating a semiconductor package, comprising: providing a package having an insulating layer and at least one semiconductor element embedded in the insulating layer, the semiconductor element having opposite active and inactive surfaces, and the insulating layer The first surface and the second surface are opposite to each other, the first surface is on the same side as the active surface, and the second surface of the insulating layer is formed with at least one recess; the filler is formed in the recess; and the line is formed A redistribution structure is on the semiconductor element and the insulating layer. The method of manufacturing the semiconductor package of claim 1, wherein the package system is disposed on a carrier, and the active surface of the semiconductor component and the first surface of the insulating layer are bonded to the carrier. After the formation of the filler, the carrier is removed. The method of fabricating a semiconductor package according to claim 1, wherein the recess is located at an edge of the second surface of the insulating layer. The method of fabricating a semiconductor package according to claim 1, wherein the recess is located between at least two of the semiconductor elements. The method of fabricating a semiconductor package according to claim 1, wherein the filler material is in a block shape. The method of fabricating a semiconductor package according to claim 1, wherein the filler material is in a gel form. The method of manufacturing a semiconductor package according to claim 1, wherein the process of forming the filler comprises: Providing a support plate having the filler; and bonding the support plate to the second surface of the insulating layer such that the filler is located in the recess. The method of fabricating a semiconductor package according to claim 7, wherein the filler material is integrally formed with the support plate. The method of fabricating a semiconductor package according to claim 7, wherein the filler is a member placed on the support plate. The method of fabricating a semiconductor package according to claim 7, wherein the filler is fixed in the recess by a bonding layer. The method of fabricating a semiconductor package according to claim 1, wherein the line redistribution structure is disposed on the active surface of the semiconductor element and the first surface of the insulating layer. The method for fabricating a semiconductor package according to claim 1, further comprising forming an insulating protective layer on the circuit redistribution structure, and the insulating protective layer has a plurality of openings exposing the circuit redistribution structure. The method for manufacturing a semiconductor package according to claim 1 is further included in the process of forming the line redistribution structure, and performing a singulation process. The method for manufacturing a semiconductor package according to claim 13 is further included in the singulation process, and the portion of the insulating layer having the recess is removed. The method of fabricating a semiconductor package according to claim 13, wherein the singulation process is a cutting path corresponding to a position corresponding to the recess. A support member comprising: a support plate; and a filler material is attached to the support plate. The support member of claim 16, wherein the filler material is integrally formed with the support plate. The support member of claim 16, wherein the filler material is a member placed on the support plate. The support member of claim 16, wherein the filler material is located at an edge of the support plate. The support member of claim 16, wherein the filler material is located at the middle of the support plate. The support member according to claim 16, wherein the filler material is in the form of a block. The support member of claim 16, wherein the filler material is in the form of a gel. The support member as claimed in claim 16 further comprising a bonding layer disposed on the support plate and the filling material.