CN104979260A - Method for manufacturing semiconductor package and support used by same - Google Patents
Method for manufacturing semiconductor package and support used by same Download PDFInfo
- Publication number
- CN104979260A CN104979260A CN201410150412.3A CN201410150412A CN104979260A CN 104979260 A CN104979260 A CN 104979260A CN 201410150412 A CN201410150412 A CN 201410150412A CN 104979260 A CN104979260 A CN 104979260A
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- China
- Prior art keywords
- dutchman
- making
- semiconductor package
- insulating barrier
- supporting bracket
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Links
- 238000000034 method Methods 0.000 title claims abstract description 71
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title description 2
- 230000004888 barrier function Effects 0.000 claims description 57
- 238000012545 processing Methods 0.000 claims description 26
- 238000005520 cutting process Methods 0.000 claims description 12
- 239000011230 binding agent Substances 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 9
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 9
- 238000009413 insulation Methods 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 18
- 238000003825 pressing Methods 0.000 description 10
- 238000000576 coating method Methods 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000032798 delamination Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- XLTRGZZLGXNXGD-UHFFFAOYSA-N benzene;1h-pyrazole Chemical compound C=1C=NNC=1.C1=CC=CC=C1 XLTRGZZLGXNXGD-UHFFFAOYSA-N 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
A method for preparing semiconductor package includes providing a package body with insulation layer and at least one semiconductor component embedded in said insulation layer, said semiconductor component having opposite active surface and non-active surface, said insulation layer having opposite first surface and second surface, said first surface being at same side of said active surface and said second surface being formed with at least one recess; then, forming a filling material in the concave part; and forming a circuit redistribution structure on the semiconductor element and the insulating layer. The filling material is used for filling the concave part to improve the flatness of the second surface of the insulating layer.
Description
Technical field
The present invention relates to a kind of method for making of semiconductor package part, espespecially a kind ofly can promote the method for making of the semiconductor package part of processing procedure reliability and strutting piece used thereof.
Background technology
Flourish along with electronic industry, electronic product is also marched toward multi-functional, high performance trend gradually.In order to meet the package requirements of semiconductor package part microminiaturization (miniaturization), develop the technology of fan-out (fan out) type encapsulation.
As Figure 1A to Fig. 1 E, it is the generalized section of the method for making of existing fan-out-type semiconductor package part.
As shown in Figure 1A, provide a bearing part 10, and this bearing part 10 has adhesion coating 101.Then, put multiple semiconductor subassembly 12 on this adhesion coating 101, those semiconductor subassemblies 12 have relative active surface 12a and non-active 12b, respectively this active surface 12a all has multiple electronic pads 120, and respectively this active surface 12a are adhered on this adhesion coating 101.
Owing to being limited to board design, so not this semiconductor subassembly 12 on the edge 10a(i.e. peripheral region of this bearing part 10 that those semiconductor subassemblies 12 cannot be laid in this bearing part 10), thus make outermostly between this semiconductor subassembly 12 and edge 10a of this bearing part 10, to produce difference of height h.In addition, in respectively also producing difference in height d between this semiconductor subassembly 12.
As shown in Figure 1B, form an insulating barrier 13 on this adhesion coating 101, with this semiconductor subassembly 12 coated, and because of this difference of height d, the cause of h, this insulating barrier 13 produces multiple recess 130,130 '.
As shown in Figure 1 C, pressing one pressing part 11, on this insulating barrier 13, makes this insulating barrier 13 outbound flow (the edge 10a namely to this bearing part 10 flows), with this insulating barrier 13 of densification.
As shown in figure ip, after this insulating barrier 13 of thermosetting, then remove this bearing part 10 and adhesion coating 101, to expose the active surface 12a of this semiconductor subassembly 12.
As referring to figure 1e, carry out circuit redistribution layer (Redistribution layer, RDL) processing procedure, by forming a circuit rerouting structure 14 in this insulating barrier 13 with on the active surface 12a of this semiconductor subassembly 12, this circuit rerouting structure 14 is made to be electrically connected the electronic pads 120 of this semiconductor subassembly 12.
Then, form an insulating protective layer 15 in this circuit rerouting structure 14, and this insulating protective layer 15 exposes the part surface of this circuit rerouting structure 14, for the conductive component 16 combined as solder bump.Afterwards, remove this pressing part 11, then carry out cutting single processing procedure.
But, in the method for making of existing semiconductor package part, in time carrying out pressure programming, can because of the cause of this difference of height h, and cause total thickness variations (Total Thickness Variation, TTV) increase, so in follow-up remove carry out RDL processing procedure after this bearing part 10 time, after this insulating barrier 13 of thermosetting, gap t(between this pressing part 11 and this bearing part 10 i.e. this recess 130) can increase, and cause this pressing part 11 to come off (Peeling), and the solvent of processing procedure easily enters the surface of this insulating barrier 13 along this gap t and residues in the t of this gap, also this pressing part 11 can be caused to come off (Peeling), as shown in figure ip, cause process rate not good.
In addition, because of the difference in height d respectively between this semiconductor subassembly 12, so after pressure programming, the surface of this insulating barrier 13 can produce clathrate, i.e. indenture (dent) phenomenon (i.e. this recess 130 '), cause between this pressing part 11 and this insulating barrier 13 and can produce bubble (void) phenomenon, cause follow-up when carrying out RDL processing procedure, this pressing part 11 comes off.
Therefore, how to overcome the problem of above-mentioned prior art, become the problem of desiring most ardently solution at present in fact.
Summary of the invention
In view of the disadvantages of above-mentioned prior art, object of the present invention for providing a kind of method for making of semiconductor package part and strutting piece used thereof, to promote the planarization of the second surface of this insulating barrier.
The method for making of semiconductor package part of the present invention, comprise: a packaging body is provided, it has insulating barrier and is embedded at least one semiconductor subassembly in this insulating barrier, this semiconductor subassembly has relative active surface and non-active, and this insulating barrier has relative first surface and second surface, this first surface and this active surface homonymy, and the second surface of this insulating barrier is formed with at least one recess; Form Dutchman in this recess; And form circuit rerouting structure on this semiconductor subassembly and this insulating barrier.
In aforesaid method for making, this packaging body is located on a bearing part, and the first surface of the active surface of this semiconductor subassembly and this insulating barrier is incorporated on this bearing part, with after this Dutchman of formation, removes this bearing part.
In aforesaid method for making, this recess is positioned at the edge of the second surface of this insulating barrier; Or this recess is between at least two these semiconductor subassemblies.
In aforesaid method for making, this Dutchman is block or gluey.
In aforesaid method for making, form the processing procedure of this Dutchman, comprising: the supporting bracket that has this Dutchman is provided; And in conjunction with this supporting bracket on the second surface of this insulating barrier, make this Dutchman be arranged in this recess.Such as, this Dutchman and this supporting bracket are one of the forming; Or this Dutchman is be placed in the component in this supporting bracket.Again, this Dutchman is fixed in this recess by binder course.
In aforesaid method for making, this circuit rerouting structure is located on the active surface of this semiconductor subassembly and the first surface of this insulating barrier.
In aforesaid method for making, also comprise and form insulating protective layer in this circuit rerouting structure, and this insulating protective layer has multiple perforate exposing this circuit rerouting structure.
In aforesaid method for making, be also included in after forming circuit rerouting structure, carry out cutting single processing procedure.Such as, in time cutting single processing procedure, remove the part that this insulating barrier has this recess in the lump; Or, this cut single processing procedure using to should the position of recess as cutting path.
In addition, the present invention also provides a kind of strutting piece, comprising: supporting bracket; And Dutchman, it is located in this supporting bracket.
In aforesaid strutting piece, this Dutchman and this supporting bracket are one of the forming; Or this Dutchman is be placed in the component in this supporting bracket.
In aforesaid strutting piece, this Dutchman is positioned at the edge of this supporting bracket; Or this Dutchman is positioned at this supporting bracket middle.
In aforesaid strutting piece, this Dutchman is block or gluey.
In aforesaid strutting piece, also comprise binder course, be located on this supporting bracket and this Dutchman.
As from the foregoing, the method for making of semiconductor package part of the present invention, inserts this recess by this Dutchman, to fill up the recess of the second surface of this insulating barrier.Therefore, in time carrying out pressure programming, total thickness variations can not increase, and gassing phenomenon can be avoided, so in follow-up carry out RDL processing procedure time, can avoid delamination occurs, and the solvent of processing procedure can not enter any surface of this insulating barrier, also can avoid delamination occurs, thus effectively can promote process rate.
Accompanying drawing explanation
Figure 1A to Fig. 1 E is the cross-sectional schematic of the method for making of existing semiconductor package part;
Fig. 2 A to Fig. 2 F is the cross-sectional schematic of the method for making of semiconductor package part of the present invention; Wherein, Fig. 2 F ' is the other method of Fig. 2 F; And
Fig. 3 A, Fig. 3 A ', Fig. 3 A ", Fig. 3 B and Fig. 3 C is the cross-sectional schematic of the different embodiments of strutting piece of the present invention.
Symbol description
10,20 bearing parts
10a, 29c edge
101,201 adhesion coatings
11 pressing parts
12,22 semiconductor subassemblies
12a, 22a active surface
Non-active of 12b, 22b
120,220 electronic padses
13,23 insulating barriers
130,130 ', 230,230 ' recess
14,24 circuit rerouting structures
15,25 insulating protective layers
16,26 conductive components
2 semiconductor package parts
2a packaging body
200 support plates
21 supporting brackets
210,210 ', 310,310 ', 310 " Dutchman
211 binder courses
23a first surface
23b second surface
240 dielectric layers
241 line layers
3,3 ', 3 " strutting piece
H, d difference of height
The horizontal imaginary line of L
S, S ' cutting path
T gap.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only for coordinating specification to disclose, for understanding and the reading of those skilled in the art, be not intended to limit the enforceable qualifications of the present invention, so the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, quote in this specification as " on ", " first ", the term such as " second " and " ", be also only be convenient to describe understand, but not for limiting the enforceable scope of the present invention, the change of its relativeness or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the present invention.
Fig. 2 A to Fig. 2 F is the generalized section of the method for making of semiconductor package part 2 of the present invention.
As shown in Figure 2 A, provide a bearing part 20, and multiple semiconductor subassembly 22 is set on this bearing part 20.
In the present embodiment, the size of this bearing part 20 can select wafer type substrate (Wafer form substrate) or general panel type substrate (Panel form substrate) on demand, and this bearing part 20 can comprise the support plate 200 that a material is glass, metal, pottery or semiconductor crystal wafer, and this support plate 200 is sequentially formed with a release layer (figure slightly) and an adhesion coating 201.
In addition, each this semiconductor subassembly 22 has relative active surface 22a and non-active 22b, and this active surface 22a has multiple electronic pads 220, and this active surface 22a is connected on the adhesion coating 201 of this bearing part 20.
As shown in Figure 2 B, form the adhesion coating 201 of an insulating barrier 23 in this bearing part 20 with on semiconductor subassembly 22, to form packaging body 2a, and this semiconductor subassembly 22 is embedded in this insulating barrier 23.
In the present embodiment, this insulating barrier 23 has relative first surface 23a and second surface 23b, and the second surface 23b of this insulating barrier 23 is formed with multiple recess 230,230 '.
In addition, the film that this insulating barrier 23 is pressure programming, but in other embodiment, this insulating barrier 23 also can the packing colloid of such as mold pressing processing procedure or the glue material etc. of printing process, thus the material of this insulating barrier 23 or generation type there is no particular restriction.
Again, the active surface 22a of this semiconductor subassembly 22 and first surface 23a of this insulating barrier 23 is copline, makes this first surface 23a and this active surface 22a homonymy.
In addition, this recess 230 of part is positioned at the edge of the second surface 23b of this insulating barrier 23, and this recess 230 ' of part is between at least two these semiconductor subassemblies 22.
As shown in Figure 2 C, the supporting bracket 21 that has multiple Dutchman 210 is provided, and in conjunction with this supporting bracket 21 on the second surface 23b of this insulating barrier 23, makes this Dutchman 210 be positioned at this recess 230, in 230 '.
In the present embodiment, the size of this supporting bracket 21 can select wafer type substrate or general panel type substrate on demand, and if this supporting bracket 21 is glass plate, metallic plate, ceramic version or semiconductor crystal wafer, and preferably, this supporting bracket 21 is identical with the material of this support plate 200.
In addition, this Dutchman 210 is integrally formed with this supporting bracket 21, such as this Dutchman 210 is the protuberance of this supporting bracket 21, its processing procedure is this supporting bracket 21 of etching, to form this protuberance, straight mesa-shaped Dutchman 310 as shown in Figure 3A, the taper mesa-shaped Dutchman 310 ' as shown in Fig. 3 A ', as Fig. 3 A " shown in domatic mesa-shaped Dutchman 310 ".Or in other embodiment, as shown in Figure 3 B, this Dutchman 210 ' also can be the component additionally adhered in this supporting bracket 21.
Again, in the lump with reference to figure 3C, preferably, this supporting bracket 21 is bonded on the second surface 23b of this insulating barrier 23 by the binder course 211 just like glue material, and this Dutchman 210 can be fixed in this recess 230 by this binder course 211.
In addition, this Dutchman 210 solidifies shape for hard block (as metal material) or glue material, but there is no particular restriction.
As shown in Figure 2 D, after this insulating barrier of thermosetting, remove this bearing part 20, with the first surface 23a of the active surface 22a and this insulating barrier 23 that expose this semiconductor subassembly 22.
As shown in Figure 2 E, carry out RDL processing procedure, form a circuit rerouting structure 24 on the active surface 22a of this semiconductor subassembly 22 and the first surface 23a of this insulating barrier 23, and this circuit rerouting structure 24 is electrically connected those electronic padses 220.
In the present embodiment, this RDL processing procedure forms a dielectric layer 240 particularly on the active surface 22a and this insulating barrier 23 of this semiconductor subassembly 22, form line layer 241 again on this dielectric layer 240, to be electrically connected those electronic padses 220, use the circuit rerouting structure 24 forming tool uniline layer 241.
Then, form an insulating protective layer 25 in this dielectric layer 240 with on line layer 241, and this insulating protective layer 25 has multiple perforate exposing this line layer 241, to form the conductive component 26 as solder bump in this tapping.
Again, the material of this dielectric layer 240 is such as Polyimide (Polyimide, PI), benzocyclobutene (Benezocy-clobutene, BCB) or poly-to diazole benzene (Polybenzoxazole, PBO).
In addition, in other embodiment, this circuit rerouting structure also can be the structure of multilayer line, its line layer 241 comprising multiple dielectric layer 240 and be formed on this dielectric layer 240.
As shown in Figure 2 F, remove this supporting bracket 21 and Dutchman 210 thereof and binder course 211, then carry out cutting single processing procedure, it cuts along cutting path S, to make multiple semiconductor package part 2.Preferably, in time cutting single processing procedure, remove the recess 230,230 ' of this insulating barrier 23 in the lump.
In another embodiment, as shown in Fig. 2 F ', this cut single processing procedure also can to should the position of recess 230,230 ' as cutting path S '.
Therefore, this line layer 241 can not be formed at this cutting path S, on the dielectric layer 240 corresponding to S '.
In method for making of the present invention, by the design of this Dutchman 210, with in time carrying out pressure programming, this recess 230 can be filled up, to flatten the second surface 23b(horizontal imaginary line L as that shown in fig. 2 c of this insulating barrier 23), compensate the difference of height between this semiconductor subassembly 22 and this bearing part 20, make there is no air gap between the second surface 23b of this insulating barrier 23 and supporting bracket 21.
Therefore, in time carrying out pressure programming, total thickness variations (Total ThicknessVariation, TTV) can not increase, and there is no air gap between this supporting bracket 21 and this bearing part 20, as shown in Figure 2 C, so in follow-up remove this bearing part 20 and carry out RDL processing procedure time, this supporting bracket 21 can be avoided to come off (Peeling), as shown in Fig. 2 D to Fig. 2 E, and the solvent of processing procedure can not enter any surface of this insulating barrier 23, this supporting bracket 21 also can be avoided to come off, thus effectively can promote process rate.
In addition, after pressure programming, the second surface 23b of this insulating barrier 23 is flat by this Dutchman 210, makes can not produce between this supporting bracket 21 and this insulating barrier 23 bubble (void) phenomenon, so in follow-up carry out RDL processing procedure time, this supporting bracket 21 can not come off.
Again, this supporting bracket 21 is reusable, so can not waste cost of manufacture.
The present invention also provides a kind of strutting piece 3,3 ', 3 ", as Fig. 3 A, Fig. 3 A ', Fig. 3 A ", shown in Fig. 3 B and Fig. 3 C, comprising: a supporting bracket 21 and the Dutchman 310,310 ', 310 be located in this supporting bracket 21 ", 210 ', 210.
Described Dutchman 310,310 ', 310 ", 210 ', 210 is block or gluey.
In an embodiment, described Dutchman 310,310 ', 310 ", 210 are one of the forming with this supporting bracket 21.
In an embodiment, described Dutchman 210 ' is for being placed in the component in this supporting bracket 21.
In an embodiment, described Dutchman 310,310 ', 310 ", 210 ', 210 are positioned at the edge 29c of this supporting bracket 21 and/or are positioned at this supporting bracket 21 middle.
In an embodiment, described strutting piece 3 " also comprise binder course 211, be located at this supporting bracket 21 with on this Dutchman 210.
In sum, the method for making of semiconductor package part of the present invention and strutting piece used thereof, mainly utilize this Dutchman to flatten the second surface of this insulating barrier, to avoid the problem that delamination occurs.
Above-described embodiment only for illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can modify to above-described embodiment.Therefore the scope of the present invention, should listed by claims.
Claims (23)
1. a method for making for semiconductor package part, comprising:
One packaging body is provided, it has insulating barrier and is embedded at least one semiconductor subassembly in this insulating barrier, this semiconductor subassembly has relative active surface and non-active, and this insulating barrier has relative first surface and second surface, this first surface and this active surface homonymy, and the second surface of this insulating barrier is formed with at least one recess;
Form Dutchman in this recess; And
Form circuit rerouting structure on this semiconductor subassembly and this insulating barrier.
2. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, this packaging body is located on a bearing part, and the first surface of the active surface of this semiconductor subassembly and this insulating barrier is incorporated on this bearing part, with after this Dutchman of formation, remove this bearing part.
3. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, this recess is positioned at the edge of the second surface of this insulating barrier.
4. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, this recess is between at least two these semiconductor subassemblies.
5. the method for making of semiconductor package part as claimed in claim 1, is characterized in that, this Dutchman is block.
6. the method for making of semiconductor package part as claimed in claim 1, is characterized in that, this Dutchman is gluey.
7. the method for making of semiconductor package part as claimed in claim 1, is characterized in that, form the processing procedure of this Dutchman, comprising:
The supporting bracket that one has this Dutchman is provided; And
In conjunction with this supporting bracket on the second surface of this insulating barrier, this Dutchman is made to be arranged in this recess.
8. the method for making of semiconductor package part as claimed in claim 7, it is characterized in that, this Dutchman and this supporting bracket are one of the forming.
9. the method for making of semiconductor package part as claimed in claim 7, it is characterized in that, this Dutchman is be placed in the component in this supporting bracket.
10. the method for making of semiconductor package part as claimed in claim 7, it is characterized in that, this Dutchman is fixed in this recess by binder course.
The method for making of 11. semiconductor package parts as claimed in claim 1, is characterized in that, this circuit rerouting structure is located on the active surface of this semiconductor subassembly and the first surface of this insulating barrier.
The method for making of 12. semiconductor package parts as claimed in claim 1, is characterized in that, this method for making also comprises formation insulating protective layer in this circuit rerouting structure, and this insulating protective layer has multiple perforate exposing this circuit rerouting structure.
The method for making of 13. semiconductor package parts as claimed in claim 1, is characterized in that, this method for making carries out cutting single processing procedure after being also included in and forming this circuit rerouting structure.
The method for making of 14. semiconductor package parts as claimed in claim 13, is characterized in that, when this method for making is also included in and cuts single processing procedure, removes the part that this insulating barrier has this recess in the lump.
The method for making of 15. semiconductor package parts as claimed in claim 13, is characterized in that, this cut single processing procedure using to should the position of recess as cutting path.
16. 1 kinds of strutting pieces, comprising:
Supporting bracket; And
Dutchman, it is located in this supporting bracket.
17. strutting pieces as claimed in claim 16, it is characterized in that, this Dutchman and this supporting bracket are one of the forming.
18. strutting pieces as claimed in claim 16, it is characterized in that, this Dutchman is be placed in the component in this supporting bracket.
19. strutting pieces as claimed in claim 16, it is characterized in that, this Dutchman is positioned at the edge of this supporting bracket.
20. strutting pieces as claimed in claim 16, it is characterized in that, this Dutchman is positioned at this supporting bracket middle.
21. strutting pieces as claimed in claim 16, is characterized in that, this Dutchman is block.
22. strutting pieces as claimed in claim 16, is characterized in that, this Dutchman is gluey.
23. strutting pieces as claimed in claim 16, it is characterized in that, this strutting piece also comprises binder course, and it is located on this supporting bracket and this Dutchman.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103112457 | 2014-04-03 | ||
| TW103112457A TWI582866B (en) | 2014-04-03 | 2014-04-03 | Manufacturing method of semiconductor package and support element used thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104979260A true CN104979260A (en) | 2015-10-14 |
| CN104979260B CN104979260B (en) | 2019-02-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410150412.3A Active CN104979260B (en) | 2014-04-03 | 2014-04-15 | Method for manufacturing semiconductor package and support used by same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104979260B (en) |
| TW (1) | TWI582866B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359654A (en) * | 2007-08-02 | 2009-02-04 | 全懋精密科技股份有限公司 | Structure of semiconductor component-buried loading board and preparation thereof |
| TWI350572B (en) * | 2007-10-31 | 2011-10-11 | United Test Ct Inc | |
| CN102324418A (en) * | 2011-08-09 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor component packaging structure and its manufacturing approach |
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| CN102956468A (en) * | 2011-08-25 | 2013-03-06 | 英特尔移动通信有限责任公司 | Semiconductor device and method of manufacturing a semiconductor device including grinding steps |
| CN103295978A (en) * | 2012-03-03 | 2013-09-11 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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- 2014-04-03 TW TW103112457A patent/TWI582866B/en active
- 2014-04-15 CN CN201410150412.3A patent/CN104979260B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359654A (en) * | 2007-08-02 | 2009-02-04 | 全懋精密科技股份有限公司 | Structure of semiconductor component-buried loading board and preparation thereof |
| TWI350572B (en) * | 2007-10-31 | 2011-10-11 | United Test Ct Inc | |
| TW201240032A (en) * | 2011-03-10 | 2012-10-01 | Sumitomo Bakelite Co | Semiconductor device and method for producing the same |
| CN102324418A (en) * | 2011-08-09 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor component packaging structure and its manufacturing approach |
| CN102956468A (en) * | 2011-08-25 | 2013-03-06 | 英特尔移动通信有限责任公司 | Semiconductor device and method of manufacturing a semiconductor device including grinding steps |
| CN103295978A (en) * | 2012-03-03 | 2013-09-11 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
Also Published As
| Publication number | Publication date |
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| TWI582866B (en) | 2017-05-11 |
| TW201539592A (en) | 2015-10-16 |
| CN104979260B (en) | 2019-02-12 |
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