CN101359020A - Aging testing substrates - Google Patents
Aging testing substrates Download PDFInfo
- Publication number
- CN101359020A CN101359020A CN 200710044557 CN200710044557A CN101359020A CN 101359020 A CN101359020 A CN 101359020A CN 200710044557 CN200710044557 CN 200710044557 CN 200710044557 A CN200710044557 A CN 200710044557A CN 101359020 A CN101359020 A CN 101359020A
- Authority
- CN
- China
- Prior art keywords
- aging testing
- testing substrates
- chip
- circuit board
- edge connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to an aging test substrate which uses the on-board chip package technology on chips. The aging test substrate comprises a frame, wherein, the frame is provided with a plurality of edge connectors which are evenly arranged. The application of the aging test substrate can realize and support the aging test of various chips, and simplify the design, layout and production flow of the aging test substrates.
Description
Technical field
The present invention relates to a kind of aging testing substrates, particularly chip is used the aging testing substrates of chip on board encapsulation technology.
Background technology
In semiconductor fabrication, wafer forms chip (IC) after overexposure, etching, cutting, encapsulation, but the performance of chip also need be tested the quality of judging its performance through product reliability, and aging of product life experiment is a link of the extremely important and necessary process of product reliability test.General common life experiment project has burn-in testing (Burn-in, BI), earlier failure period (Early Failure Rate, EFR), high-temperature operation life test (High Temperature Operating Life, HTOL) etc., in general, above-mentioned experiment all be under conditions such as high temperature, high voltage to be positioned at aging testing substrates (Burn-in Board, BIB) chip on is tested, the speed-up chip operational process forces fault to occur in the shorter time.
In the prior art, aging testing substrates is an element by Chip Packaging decision, a kind of aging testing substrates correspondence a kind of form of Chip Packaging.That is to say, in order to meet the form of various Chip Packaging, need to prepare many kinds of aging testing substrates, and different chip products has many packing forms now, so corresponding a kind of chip product provides various aging testing substrates can increase production cost, and the cycle that designs and produces of aging testing substrates is long, and generally need just can be finished in about 5 months, influences chip reliability authentication and listing progress.
Though occurred the Chip Packaging form of some standards now, such as DIP48, TSOPII-44, TSOPII-54 etc., the aging testing substrates of corresponding said chip packing forms generally adopt socket to electrically connect with the chip of corresponding chip, and promptly this carries out burn-in test.But the specification of above-mentioned socket can not be unified, so socket can not be applied to the same Chip Packaging form of other Chip Packaging form or different pin numbers.
In order to improve test speed and to save cost, press for a kind of aging testing substrates that can satisfy various chip requirements.
Summary of the invention
The object of the present invention is to provide a kind of aging testing substrates, can not only realize supporting the test of various chips by this test base, and can simplify design, layout and the manufacturing process of aging testing substrates chip use chip on board encapsulation technology.
In order to reach described purpose, the invention provides a kind of aging testing substrates, comprise a framework, wherein, have several evenly distributed edge connectors on the described framework.
In above-mentioned aging testing substrates, described adjacent edge connector is identical in the spacing of directions X.
In above-mentioned aging testing substrates, described framework one end has the leader to connect.
In above-mentioned aging testing substrates, described edge connector comprises insulating body, with several contact heads that are arranged in parallel that are positioned at the inner both sides of insulating body, and the stitch that corresponding each contact head connects.
In above-mentioned aging testing substrates, described edge connector is connected with circuit board by contact head.
In above-mentioned aging testing substrates, described circuit board comprises chip, passes through the golden finger of several pads and chip electric connection.
In above-mentioned aging testing substrates, the quantity that described circuit board has golden finger is less than or equal to the edge connector quantity of aging testing substrates at directions X.
In above-mentioned aging testing substrates, the spacing of described adjacent golden finger is identical and equate with the spacing of adjacent edge connector.
In above-mentioned aging testing substrates, described circuit board adopts the chip on board encapsulation to chip.
The present invention makes it compared with prior art owing to adopted above-mentioned technical scheme, has following advantage and good effect:
1. utilize the circuit board of chip on board encapsulation technology can support dissimilar chips and more golden finger, connector, reduce construction cycle, the cost of new product.
2. aging testing substrates adopts edge connector reliably to contact with circuit board, simplifies design, layout and the manufacturing process of aging testing substrates, compares with other aging testing substrates, improves test speed, and has higher density, longer serviceable life.
3. circuit board utilizes chip on board encapsulation technology and aging testing substrates to adopt the principle of edge connector can also be applied to highly quicken stress test (Highly Accelerated Stress Test, HAST), the test of temperature-humidity bias (Temperature Humidity Bias Test, THBT), final test plate (FinalTest Board) waits the test base of other failtestss.
Description of drawings
Aging testing substrates of the present invention is provided by following embodiment and accompanying drawing.
Fig. 1 is for adopting the circuit board synoptic diagram of chip on board encapsulation;
Fig. 2 is an aging testing substrates structural representation of the present invention;
Fig. 3 is the edge connector structural representation in Fig. 2 aging testing substrates.
Fig. 4 A, 4B are the chip on board dimensional packaged circuit board synoptic diagram with different golden finger quantity.
Embodiment
Below will be described in further detail aging testing substrates of the present invention.
Fig. 1 is for adopting chip on board encapsulation (Chip On Board, circuit board synoptic diagram COB).The COB technology is that chip 2 is implanted on the special circuit board 1, the main wire bonds (Wire Bonding) that adopts is electrically connected the pin of several pads 4 (inner finger) on the circuit board 1 with chip 2, and pad 4 and golden finger 14a (golden finger) are that the built-in copper-connection by circuit board 1 is connected.The epoxide resin material that has the special protection function after the last thawing of utilization again covers the later stage encapsulation of finishing chip on the chip.Wherein golden finger 14a is made up of several gold-plated conductive contact blades 3 and is positioned at the two-sided of circuit board 1 one ends.
Fig. 2 is an aging testing substrates structural representation of the present invention.Aging testing substrates 5 of the present invention mainly comprises a framework 7; With the handle 6 of framework 7 one ends, this handle 6 can be inserted into aging testing substrates 5 in the container of aging equipment calibration cell; Several are evenly distributed, and wherein edge connector 8 is connected with circuit board 1 in the edge connector 8 (edgeconnector) of framework 7, and neighboring edge connector 8 is identical and all be a in the spacing of directions X; Relative with handle 6 and be positioned at framework 7 other ends several connect finger 9, the drive plate (not shown) that connects finger 9 and aging equipment electrically connects, drive plate produces the voltage of measured device chip 2 or the test signal of regulation, thereby the performance of test chip.
Fig. 3 is the edge connector structural representation in Fig. 2 aging testing substrates.This edge connector 8 mainly comprises insulating body 10; Be positioned at several contact heads 11 that are arranged in parallel of insulating body 10 inner both sides, those contact heads 11 and circuit board 1 corresponding conductive contact blade 3 electrically connects; With the stitch 12 of each contact head 11 corresponding connection, the circuit in stitch 12 and the framework 7 is connected to be connected and points on 9.
Fig. 4 A, 4B are the chip on board dimensional packaged circuit board synoptic diagram with different golden finger quantity.Wherein Fig. 4 A has the circuit board 13 of two golden finger 14a, 14b for expression, each golden finger 14b, 14c have stationary phase conductive contact blade 3 together, such as 48, perhaps 72 conductive contact blades, the conductive contact blade quantity of golden finger 14b, 14c can be done corresponding adjustment as required.The conductive contact blade 3 of golden finger 14b, 14c is identical in quantity, spacing with the contact head 11 of edge connector 7.Similarly, Fig. 4 B is the COB circuit board 15 with four golden finger 14d, 14e, 14f, 14g.Above-mentioned circuit board 13,15 with different golden finger quantity, wherein adjacent golden finger 14b, 14c, 14d, 14e, 14f, 14g spacing b, the c of directions X all equate and and the spacing a of neighboring edge connector 8 also equate, so, foregoing circuit plate 13,15 can insert in the edge connector 8 of corresponding aging testing substrates 5 and test, and the golden finger quantity that circuit board 13,15 has is less than or equal to edge connector 8 quantity of aging testing substrates 5 at directions X.
Learn that according to test most chip all can adopt chip on board encapsulation (COB) technology and carry out burn-in test in conjunction with aging testing substrates of the present invention.That is to say, adopt an aging testing substrates of the present invention correspondence to have equal number conductive contact blade and different kinds of chips, thereby saved cost of development, and chip adopts the encapsulation of chip on board encapsulation (COB) technology, speed is fast, has saved new product development cycle.The conductive contact blade that the contact head of aging testing substrates is corresponding with circuit board electrically connects, and has more reliable contact in test.In addition, chip of the present invention adopts chip on board encapsulation (COB) technology aging testing substrates principle corresponding with it also to can be applicable to highly quicken stress test (Highly Accelerated Stress Test, HAST), the test of temperature-humidity bias (Temperature Humidity Bias Test, THBT), final test plate (Final Test Board) waits in the test base of other failtestss.
That more than introduces only is based on preferred embodiment of the present invention, can not limit scope of the present invention with this.Any aging testing substrates of the present invention is done replacement, the combination, discrete of step well know in the art, and the invention process step is done well know in the art being equal to change or replace and all do not exceed exposure of the present invention and protection domain.
Claims (9)
1, a kind of aging testing substrates comprises a framework, it is characterized in that: have several evenly distributed edge connectors on the described framework.
2, aging testing substrates as claimed in claim 1 is characterized in that: the spacing of described adjacent edge connector is identical.
3, aging testing substrates as claimed in claim 1 is characterized in that: described framework one end has the leader to connect.
4, aging testing substrates as claimed in claim 1 is characterized in that: described edge connector comprises insulating body, with several contact heads that are arranged in parallel that are positioned at the inner both sides of insulating body, and the stitch that corresponding each contact head connects.
5, aging testing substrates as claimed in claim 4 is characterized in that: described edge connector is connected with a circuit board by contact head.
6, aging testing substrates as claimed in claim 5 is characterized in that: described circuit board comprises a chip, passes through the golden finger of several pads and chip electric connection.
7, aging testing substrates as claimed in claim 6 is characterized in that: the quantity that described circuit board has golden finger is less than or equal to the edge connector quantity of aging testing substrates at directions X.
8, aging testing substrates as claimed in claim 7 is characterized in that: the spacing of described adjacent golden finger is identical and equate with the spacing of adjacent edge connector.
9, aging testing substrates as claimed in claim 6 is characterized in that: described circuit board adopts the chip on board encapsulation to chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710044557 CN101359020A (en) | 2007-08-03 | 2007-08-03 | Aging testing substrates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710044557 CN101359020A (en) | 2007-08-03 | 2007-08-03 | Aging testing substrates |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101359020A true CN101359020A (en) | 2009-02-04 |
Family
ID=40331519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710044557 Pending CN101359020A (en) | 2007-08-03 | 2007-08-03 | Aging testing substrates |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101359020A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102053220A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Burn-in architecture and burn-in method |
| CN102043100B (en) * | 2009-10-09 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Aging test system |
| CN103630824A (en) * | 2012-08-28 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Chip concurrent test system |
| CN104460652A (en) * | 2014-10-27 | 2015-03-25 | 上海原动力通信科技有限公司 | Board card ageing device and using method thereof |
| CN105277863A (en) * | 2014-07-17 | 2016-01-27 | 中国运载火箭技术研究院 | Aging device for power amplifier |
| CN106383304A (en) * | 2016-10-24 | 2017-02-08 | 上海华力微电子有限公司 | Aging test board |
| CN109061233A (en) * | 2018-07-27 | 2018-12-21 | 广州华望汽车电子有限公司 | A kind of multipurpose drawer and its trolley |
| CN111487521A (en) * | 2020-04-29 | 2020-08-04 | 江苏七维测试技术有限公司 | Wafer-level testing device for liquid environment of temperature sensor |
| CN113219314A (en) * | 2021-04-23 | 2021-08-06 | 深圳市时代速信科技有限公司 | Semiconductor batch test system |
-
2007
- 2007-08-03 CN CN 200710044557 patent/CN101359020A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102043100B (en) * | 2009-10-09 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Aging test system |
| CN102053220A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Burn-in architecture and burn-in method |
| CN103630824A (en) * | 2012-08-28 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Chip concurrent test system |
| CN103630824B (en) * | 2012-08-28 | 2016-10-19 | 上海华虹宏力半导体制造有限公司 | Chip concurrent test system |
| CN105277863A (en) * | 2014-07-17 | 2016-01-27 | 中国运载火箭技术研究院 | Aging device for power amplifier |
| CN104460652A (en) * | 2014-10-27 | 2015-03-25 | 上海原动力通信科技有限公司 | Board card ageing device and using method thereof |
| CN106383304A (en) * | 2016-10-24 | 2017-02-08 | 上海华力微电子有限公司 | Aging test board |
| CN109061233A (en) * | 2018-07-27 | 2018-12-21 | 广州华望汽车电子有限公司 | A kind of multipurpose drawer and its trolley |
| CN111487521A (en) * | 2020-04-29 | 2020-08-04 | 江苏七维测试技术有限公司 | Wafer-level testing device for liquid environment of temperature sensor |
| CN113219314A (en) * | 2021-04-23 | 2021-08-06 | 深圳市时代速信科技有限公司 | Semiconductor batch test system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101359020A (en) | Aging testing substrates | |
| US7132841B1 (en) | Carrier for test, burn-in, and first level packaging | |
| US9362187B2 (en) | Chip package having terminal pads of different form factors | |
| US7485969B2 (en) | Stacked microelectronic devices and methods for manufacturing microelectronic devices | |
| US5763947A (en) | Integrated circuit chip package having configurable contacts and a removable connector | |
| CN102012470B (en) | Electrical test adapter plate of sealing base plate and method thereof | |
| CN101504923B (en) | Semiconductor device, its manufacturing method and its testing method | |
| US7808092B2 (en) | Semiconductor device with a plurality of ground planes | |
| JP2004138405A (en) | Probe for measuring semiconductor device | |
| US20020063317A1 (en) | Tape carrier, semiconductor assembly, and semiconductor device, methods of manufacture thereof, and electronic instrument | |
| US9082644B2 (en) | Method of manufacturing and testing a chip package | |
| JP4980232B2 (en) | System in package | |
| US20080265389A1 (en) | Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications | |
| US20090065922A1 (en) | Semiconductor device package structure | |
| US6788092B2 (en) | Test assembly for integrated circuit package | |
| KR100723518B1 (en) | Interposer pattern including the pad chain | |
| US20130169302A1 (en) | System and adapter for testing packaged integrated circuit chips | |
| KR20040080739A (en) | Semiconductor chip having test pads and tape carrier package using thereof | |
| KR101425606B1 (en) | Manufacturing mathod of film type contact complex for semiconductor package test socket | |
| JP2004138391A (en) | Method for manufacturing semiconductor device | |
| KR101781895B1 (en) | System for testing multi chip package | |
| JP2001272435A (en) | Outlet for measurement of electric characteristic of semiconductor chip and evaluation method for electric characteristic of semiconductor device | |
| KR0141453B1 (en) | Manufacturing method of known-good die | |
| US20070085554A1 (en) | Replaceable modular probe head | |
| Kong et al. | The reliability challenges of qfn packaging |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20090204 |