CN101351873A - 封装级结构中的集成电容器、制作其的工艺和包含其的系统 - Google Patents

封装级结构中的集成电容器、制作其的工艺和包含其的系统 Download PDF

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Publication number
CN101351873A
CN101351873A CNA2006800501422A CN200680050142A CN101351873A CN 101351873 A CN101351873 A CN 101351873A CN A2006800501422 A CNA2006800501422 A CN A2006800501422A CN 200680050142 A CN200680050142 A CN 200680050142A CN 101351873 A CN101351873 A CN 101351873A
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core
dielectric film
layer
tube core
core layer
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CN101351873B (zh
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J·J·唐
X·Y·曾
J·何
D·海
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Intel Corp
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Intel Corp
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Abstract

本发明提供的制品包括嵌入焊接掩模中的顶部电极。制品包括核心结构上的顶部电极。形成顶部电极的工艺包括减小焊接掩模厚度，并在减小厚度的焊接掩模上形成顶部电极。形成顶部电极的工艺包括在处于核心结构的形成图案部分中的高K电介质上形成顶部电极。

Description

封装级结构中的集成电容器、制作其的工艺和包含其的系统
技术领域
一般来说，本发明实施例涉及芯片封装中的电容器。
背景技术
例如电容器、电感器和电阻器等无源器件在集成电路(IC)芯片封装中具有不断增加的重要性。例如，电容器用于去耦合、响应处理器负荷、调谐和调制的射频(RF)应用及其它的功能。微型无源RF器件受到越来越大的压力，以便为了用户便利而获得越来越小的封装。结果是，电容器和其它无源RF器件难以设置在这些小封装中。
附图说明
为了说明获得实施例的方式，将参照附图示出的示范实施例来提供以上概述的实施例的更具体描述。要理解，这些附图仅说明典型实施例，它们不一定按规定比例绘制，因而不要看作是对其范围的限制，将通过使用附图以附加细节来描述和说明这些实施例，附图包括：
图1A是根据一个实施例的处理期间的管芯(die)的核心支撑结构的截面立视图；
图1B是根据一个实施例的形成图案(patterning)之后的图1A所示核心支撑结构的截面立视图；
图1C是根据一个实施例的模制(stenciling)和应用介电膜之后的图1B所示核心支撑结构的截面立视图；
图1D是根据一个实施例的形成顶部和底部电极及电镀通孔之后的图1C所示核心支撑结构的截面立视图；
图1E是根据一个实施例的形成焊接掩模(solder mask)层之后的图1D所示核心支撑结构的截面立视图；
图2A是根据一个实施例的与核心嵌入电容器(embedded-in-corecapacitor)装配期间的芯片封装的截面立视图；
图2B是根据一个实施例的进行处理之后的图2A中所示芯片封装的截面立视图；
图2是根据一个实施例的具有核心嵌入电容器的芯片封装的截面立视图；
图3是根据一个实施例、具有核心嵌入电容器的芯片封装的截面立视图；
图4A是根据一个实施例的进行处理期间的丝焊安装(wire-bondmounting)衬底的截面立视图；
图4B是根据一个实施例的制备焊接掩模膜之后的图4A中所示丝焊安装衬底的截面立视图；
图4C是根据一个实施例的形成焊接掩模膜的图案之后的图4B所示丝焊安装衬底的截面立视图；
图4D是根据一个实施例的焊接掩模结构的高度减小之后的图4C中所示丝焊安装衬底的截面立视图；
图4E是根据一个实施例的暴露高度减小的焊接掩模和管芯焊盘(die land)的图4D所示核心支撑结构的截面立视图；
图4F是根据一个实施例的进一步进行处理以便形成顶部电极以及将管芯安置于管芯焊盘之后的图4E所示核心支撑结构的截面立视图；
图5是根据一个实施例的取自图4F的衬底中的焊接掩模嵌入电容器的顶视图；
图6是描述方法流程实施例的流程图；
图7是示出根据一个实施例的计算系统的断面立视图；以及
图8是根据一个实施例的计算系统的示意图。
具体实施方式
本公开中的实施例涉及设置在焊接掩模结构和核心结构中的嵌入式无源器件。一个实施例包括电容器，包含焊接掩模结构中的顶部电极。焊接掩模结构经过修改，以便允许现有焊接掩模结构中的零剖面电容器(zero-profile capacitor)。类似地，核心结构经过修改，以便允许与电镀通孔相邻的零剖面电容器。
以下描述包括例如上、下、第一、第二等术语，它们仅用于进行描述而不是要理解为限制。本文所述的设备或制品的实施例可通过多个位置和取向来制造、使用或装运。术语“管芯”和“芯片”一般指的是作为通过各种过程操作变换为预期集成电路装置的基本工件的物理对象。管芯通常从晶片分割，以及晶圆可由半导体、非半导体或者半导体和非半导体材料的组合来制作。底板通常是充当管芯的安装衬底的树脂浸渍玻璃纤维结构。
现在参照附图，其中，对相似结构提供相似尾标参考标号。为了最清楚地示出各种实施例的结构，本文包含的附图是集成电路结构的图解表示。因此，例如显微照片中的制造结构的实际外观可能看起来不同，但仍然结合了所示实施例的本质结构。此外，附图示出理解所示实施例所需的结构。没有包括本领域已知的其它结构，以便保持附图的清晰。
图1A是根据一个实施例的进行处理期间的管芯的核心支撑结构100的截面立视图。根据一个实施例，核心支撑结构(以下称作“核心结构”)100是有机-无机化合物。根据一个实施例，核心结构100是硬有机材料(stiff organic)，例如FR4树脂浸渍玻璃纤维。根据一个实施例，核心结构100是有机材料和无机材料的组合，例如双马来酰亚胺三嗪树脂(bismalde trazine，BT)材料。
图1B是根据一个实施例的形成图案之后的图1A所示核心支撑结构100的截面立视图。形成图案的核心结构101包括周边形成图案结构层110和内部形成图案结构层112。在周边形成图案结构层110附近制备用于接收介电膜的第一凹槽114。形成图案核心结构101还包括第二凹槽116，它为随后将要制作的电镀通孔(PTH)作准备。
图1C是根据一个实施例、模制和应用介电膜118之后的图1B所示核心支撑结构101的截面立视图。模制层120设置在核心结构102之上，并且使介电膜118流通过模版开口，以便填充第一凹槽114的每一个存在。
在一个实施例中，形成介电膜118之后的核心结构102呈现基本共面的介电第一表面122和核心第一表面124。类似地，在一个实施例中，形成介电膜118之后的核心结构102呈现基本共面的介电第二表面126和核心第二表面128。根据要求权益的实施例，核心结构102又称作结构层102。
在第一凹槽114中模制或者以其它方式形成介电膜118之后，介电膜118经过固化(cured)或者至少经过预聚合(B-staged)，以便取得充分稳定性供进一步处理核心结构102。在一个实施例中，介电膜118是高K材料，它的电容率Er大约为20(呈现大约17.7picoFarads/mm2(pF/mm2))。在一个实施例中，介电膜118的Er大约为50(44pF/mm2)。在一个实施例中，介电膜118的Er的范围从大约15至大约60。
图1D是根据一个实施例的形成顶部电极130和底部电极132及电镀通孔(PTH)134之后的图1C所示核心支撑结构102的截面立视图。可通过若干阶段来执行形成电极和结构层的过程。例如，通过在介电第一表面122和核心第一表面124上方非电镀层籽晶层，来形成顶部电极130以及PTH 134中处于核心第一表面124之上或者附近的部分。此后，执行电镀过程，以便取得顶部电极130的设计厚度，将产生处于核心第一表面124处或附近的PTH 134中的给定厚度。此后，在介电第二表面126和核心第二表面128上电镀核心结构103。因此，填充第二凹槽116的PTH 134具有其中的电镀接缝。
图1E是根据一个实施例的形成焊接掩模层136之后的图1D所示核心支撑结构103的截面立视图。在一个实施例中，焊接掩模层136用作焊接掩模以及用作沉积在顶部电极130和底部电极132其中至少一个上方的封装层。核心支撑104被焊接掩模层136覆盖，准备对它形成图案并将它应用于例如处理器等微电子器件或者RF应用的应用专用集成电路(ASIC)等。
图2A是根据一个实施例的装配核心嵌入电容器期间的芯片封装200的截面立视图。芯片封装200包括核心结构238，与图1E所示的核心结构104相似。根据一个实施例，已经对焊接掩模层236形成图案，以便形成电容器掩模开口240。根据一个实施例，还对焊接掩模层236形成图案，以便形成PTH掩模开口242。具有活性表面246和后侧表面248的倒装晶片244通过方向箭头表示为与核心结构238集合在一起。根据一个实施例，倒装晶片244包括焊料突起250，它配置成匹配电容器掩模开口240的图案形成。根据一个实施例，焊料突起250的其它出现情况匹配PTH掩模开口242的图案形成。
在一个实施例中，没有使用焊接掩模层236的图案形成，而是对焊接掩模层236进行预聚合。此后，将具有焊料突起250的倒装晶片244压入焊接掩模层236，以及通过将焊接掩模层236移入原本由电容器掩模开口240和PTH掩模开口242准备的位置，来进行电接触。
图2B是根据一个实施例的进行处理之后的图2A所示芯片封装200的截面立视图。芯片封装201说明将倒装晶片244与核心结构238集合在一起。此后，在倒装晶片244与核心结构238之间插入底部填充材料252，以便保护电气连接和其它结构。
图3是根据一个实施例的具有核心嵌入电容器的芯片封装300的截面立视图。与图2A所示的芯片封装201相似，使倒装晶片344和核心结构338匹配。在这个实施例中，多个焊料突起350是图2B所示的大约两倍。因此，焊料突起350的两次出现碰触嵌入核心结构338的顶部电极330。在倒装晶片344与核心结构338之间插入底部填充材料352，以便保护电气连接和其它结构。
图4A是根据一个实施例的进行处理期间的丝焊安装衬底(WBMS)400的截面立视图。根据一个实施例，WBMS 400包括WBMS核心454、顶部涂层456和底部涂层458。在一个实施例中，将WBMS400选择用于手持装置、如无线装置的制造。根据一个实施例，WBMS400包括第一键合指(bond finger)460垫。类似地，在将WBMS 400选择成其中具有电容器时，WBMS 400包括底部电极432。在一个实施例中，WBMS 400包括第二键合指462垫。
图4B是根据一个实施例的制备焊接掩模膜464之后的图4A所示WBMS 400的截面立视图。WBMS 401包括第一掩模466，对它形成图案以便相应于底部电极432的出现。示出去除焊接掩模膜464中通过第一掩模466暴露的所有部分的焊接掩模膜464的第一图案形成。
图4C是根据一个实施例的焊接掩模膜465的第二图案形成之后的图4B所示WBMS 401的截面立视图。WBMS 402包括已经覆盖底部电极432的介电膜468。根据一个实施例，将介电膜468选择成具有高电容率。在一个实施例中，图4C所示的图案形成方案用于在去除第一掩模466之前在介电膜468上设置电镀籽晶层。
图4D是根据一个实施例的进一步进行处理之后的图4C所示WBMS 402的截面立视图。已经通过对图4C所示焊接掩模膜464进行第二次图案形成来处理WBMS 403，以便获得第二形成图案焊接掩模膜465。根据一个实施例，使用了第二掩模470，不仅暴露第一键合指垫(pad)460和第二键合指垫462，而且还暴露WBMS 403的中心附近的管芯焊盘472。
图4E是根据一个实施例的进一步进行处理之后的图4D所示核心支撑结构403的截面立视图。核心结构404中已经清除了第二掩模470。在一个实施例中，形成介电膜468之后核心结构404呈现不一定共面的介电第一表面474和结构层第一表面476。在一个实施例中，形成介电膜468之后核心结构404呈现基本上共面的介电第二表面478和结构层第二表面480。
图4F是根据一个实施例的进一步进行处理之后的图4E所示核心支撑结构404的截面图。支撑结构405包括已经电镀到介电膜468上方的顶部电极482。类似地，第一键合指垫460已经镀有第一键合指上部484，并且第二键合指垫462已经镀有第二键合指上部486。在一个实施例中，通过提供第三掩模488来进行电镀。在一个实施例中，从单电镀膜对顶部电极482、第一键合指上部484和第二键合指上部486形成图案，形成图案实质上是第三掩模488的倒转。
图4G是根据一个实施例的进一步进行处理之后的图4E所示核心支撑结构404的截面立视图。核心支撑结构405经过处理，使管芯490安置在管芯焊盘472上。在这个过程阶段制备核心支撑结构405，以便接收管芯490到核心支撑结构405的丝焊耦合。
在一个实施例中，底部电极432是核心支撑结构405中的地环(ground ring)432的组成部分，而第一键合垫460是电源环(powerring)460的一部分。在一个实施例中，底部电极432是核心支撑结构405中的电源环432的一部分，而第一键合垫460是地环460的一部分。根据一个实施例，电源环和地环共同提供电导管，用于到管芯490的充足电源。
虽然顶部电极482和底部电极432示为电容器的一部分，但是，根据各种实施例，可类似地制作例如嵌入电感器或嵌入电阻器等其它结构。
图5是根据一个实施例的衬底500中的焊接掩模嵌入电容器的顶视图。剖面线4G-4G提供取自与图4G的核心支撑结构405相似的结构的截面立视图。管芯590设置在衬底500的管芯焊盘位置。以虚线将电源环532示为围绕管芯590。还以虚线将地环560示为围绕电源环532和管芯590。通过焊接掩模565来暴露上部电极582，焊接掩模565可以是第二形成图案焊接掩模膜，例如图4G所示的第二形成图案的焊接掩模膜465。第一键合指上部584也示为通过焊接掩模565被暴露。上部电极582和第一键合指上部584看起来是整体结构，例如对于图4G的上部电极482和第一键合指上部484所述。
通过第一键合导线594在第一管芯键合指592与第一键合指上部584之间实现管芯590与衬底500之间的电通信。还可以第二管芯键合指596与第二键合指上部586之间通过第二键合导线598来实现管芯598与衬底500之间的电通信。因此，根据一个实施例，制造嵌入式无源器件、如平行板电容器，而无需增加核心支撑结构500的竖向形状因素。
图6是描述方法流程实施例的流程图600。
在610，该过程包括形成与作为焊接掩模和核心其中之一的结构层相邻与接触的介电膜。
在620，该过程包括在介电膜上形成顶部电极。在一个实施例中，该过程在610开始，并在620结束。
在630，该过程包括将顶部电极耦合到管芯。在一个实施例中，该过程在630结束。
图7是示出根据一个实施例的计算系统700的断面立视图。核心嵌入式无源器件或焊接掩模嵌入式无源器件的上述实施例的一个或多个可用于计算系统，如图7的计算系统700。下文中，任何核心嵌入式无源器件或焊接掩模嵌入式无源器件实施例单独或者与任何其它实施例结合称作实施例配置。
计算系统700包括例装入IC芯片封装710中的至少一个处理器(未示出)、数据存储系统712、例如键盘714等至少一个输入装置以及诸如监测器716等至少一个输出装置。计算系统700包括处理数据信号的处理器，并且可包括例如可向Intel公司购买的微处理器。除了键盘714之外，计算系统700可包括另外的用户输入装置，例如鼠标718。计算系统700可包括在如图1和图2-5所示处理给定核心嵌入式无源器件或焊接掩模嵌入式无源器件实施例之后的结构。
为了本公开的目的，包含根据要求权益的主题的组件的计算系统700可包括使用微电子器件系统的任何系统，例如可包括与例如动态随机存取存储器(DRAM)、聚合物存储器、闪速存储器和相变存储器等数据存储耦合的核心嵌入式无源器件或焊接掩模嵌入式无源器件实施例中的至少一个。在这个实施例中，实施例通过与处理器耦合来与这些功能性的任何组合耦合。但是，在一个实施例中，本公开中提出的实施例配置与任何这些功能性耦合。对于一个示例实施例，数据存储包括管芯上的嵌入式DRAM高速缓存。另外，在一个实施例中，与处理器(未示出)耦合的实施例配置是具有与DRAM高速缓存的数据存储耦合的实施例配置的系统的一部分。另外，在一个实施例中，实施例配置与数据存储712耦合。
在一个实施例中，计算系统700还可包括包含数字信号处理器(DSP)、微控制器、专用集成电路(ASIC)或者微处理器的管芯。在这个实施例中，实施例配置通过与处理器耦合来与这些功能性的任何组合耦合。对于一个示例实施例，DSP是可包括独立处理器以及底板720上作为芯片组的分离部分的DSP的芯片组的一部分。在这个实施例中，实施例配置与DSP耦合，以及可存在与IC芯片封装710中的处理器耦合的分离实施例配置。另外，在一个实施例中，实施例配置耦合到在与IC芯片封装710相同的底板720上安装的DSP。现在可以理解，结合通过本公开的核心嵌入式无源器件或焊接掩模嵌入式无源器件的各种实施例及其等效方案所提出的实施例配置，实施例配置可如针对计算系统700所提出那样进行组合。
现在可以理解，本公开中提出的实施例可适用于与传统计算机不同的装置和设备。例如，管芯可采用实施例配置来封装，并设置在例如无线通信器等便携装置或者例如个人数据助理等手持装置中。另一个示例是可采用实施例配置来封装并设置在例如汽车、机车、船只、飞机或太空船等交通工具中的管芯。
图8是根据一个实施例的电子系统800的示意图。所示的电子系统800可包含图7所示的计算系统700，但更一般地示出了该电子系统。电子系统800结合了至少一个电子部件810，例如图2-5所示的IC管芯。在一个实施例中，电子系统800是计算机系统，它包括电耦合电子系统800的各个组件的系统总线820。根据各种实施例，系统总线820是单总线或者总线的任何组合。电子系统800包括电压源830，它向集成电路810提供电力。在一些实施例中，电压源830通过系统总线820向集成电路810提供电流。
根据一个实施例，集成电路810电耦合到系统总线820，并且包括任何电路或者电路的组合。在一个实施例中，集成电路810包括可以是任何类型的处理器812。本文所使用的处理器812表示任何类型的电路，例如但不限于微处理器、微控制器、图形处理器、数字信号处理器或者另一种处理器。可包含在集成电路810中的其它类型的电路是定制电路或ASIC，例如用于诸如蜂窝电话、寻呼机、便携计算机、双向无线电和类似电子系统等无线装置的通信电路814。在一个实施例中，处理器810包括管芯上存储器816，如SRAM。在一个实施例中，处理器810包括管芯上存储器816，如eDRAM。
在一个实施例中，电子系统800还包括外部存储器840，它又可包括适合于特定应用的一个或多个存储器元件，例如采取RAM形式的主存储器842、一个或多个硬驱动826和/或处理诸如磁盘、光盘(CD)、数字视频光盘(DVD)、闪速存储器密钥以及本领域已知的其它可移动介质之类的可移动介质848的一个或多个驱动。
在一个实施例中，电子系统800还包括显示装置850、音频输出860。在一个实施例中，电子系统800包括控制器870，例如键盘、鼠标、轨迹球、游戏控制器、话筒、语音识别装置或者将信息输入电子系统800的任何其它装置。
如本文所示，集成电路810可在许多不同的实施例中实现，例如电子封装、电子系统、计算机系统、制作集成电路的一种或多种方法，制作包括本文中各个实施例及其行业认可等效中提出的RF无源器件包含层以及集成电路的电子部件的一种或多种方法。元件、材料、几何形状、尺寸和操作序列均可改变以适应特定封装要求。
“摘要”是根据要求允许读者快速确定技术公开的性质和要点的摘要的37C.F.R.§1.72(b)来提供的。应当理解，它的提供并不是用于解释或限制权利要求书的范围或含义。
在以上详细说明中，各种功能集中到单一实施例中，用于简化本公开。这种公开的方法不应解释为反映了要求权益的本发明的实施例要求超过各权利要求书中明确描述的功能的目的。相反，如以下权利要求所反映的那样，创造性主题在于少于单个公开实施例的全部特征。因此，以下权利要求结合到详细说明中，其中各权利要求本身代表独立优选实施例。
本领域的技术人员易于理解，已经描述和说明以便解释本发明的性质的部分和方法阶段的细节、材料及设置方面的其它各种变更均可进行，而不会背离所附权利要求书中表达的本发明的原理和范围。

Claims (22)

1.一种制品，包括：
底部电极；
介电膜，包括第一表面和第二表面，其中，所述介电膜设置在所述底部电极上方和在所述底部上面；
结构层，设置成邻近于所述介电膜并与其接触，其中，在所述第一表面和所述第二表面中的至少一个上所述结构层与所述介电膜基本上共面，以及其中，所述结构层是焊接掩模和核心层中的至少一个；以及
顶部电极，设置在所述介电膜上方和在所述介电膜上面。
2.如权利要求1所述的制品，其中，所述底部电极与封装中的电源环和地环中的一个相耦合。
3.如权利要求1所述的制品，其中，所述底部电极是封装中的地环的一部分，以及其中，所述顶部电极是所述封装中的电源环的一部分。
4.如权利要求1所述的制品，其中，所述介电膜和所述结构层具有基本上相同的组成。
5.如权利要求1所述的制品，其中，所述结构层是核心层，所述核心层还包括与所述介电膜相邻并通过所述核心层与所述介电膜间隔开的电镀通孔。
6.如权利要求1所述的制品，其中，所述结构层是核心层，所述核心层还包括与所述介电膜相邻并通过所述核心层间隔开的电镀通孔，所述制品还包括设置在所述顶部电极和所述底部电极中的至少一个上方的封装层。
7.如权利要求1所述的制品，其中，所述结构层是核心层，所述制品还包括：
与所述顶部电极接触的第一焊料突起；以及
与所述第一焊料突起接触的管芯。
8.如权利要求1所述的制品，其中，所述结构层是核心层，所述核心层还包括与所述介电膜相邻且通过所述核心层与所述介电膜间隔开的电镀通孔，所述制品还包括：
第一焊料突起，耦合到所述顶部电极；
第一管芯，耦合到所述第一焊料突起；
第二焊料突起，耦合到所述电镀通孔；以及
所述第二焊料突起耦合到所述第一管芯。
9.一种工艺，包括：
在核心层中形成第一通孔，其中，所述核心层包括第一侧和第二侧；
在所述第一通孔中形成介电层；
在所述介电层上和所述核心层第二侧之下形成底部电极；
在所述介电层上和所述核心层上方形成顶部电极；
在所述核心层中形成第二通孔；
从所述第二通孔形成电镀通孔；以及
将所述核心层与管芯耦合。
10.如权利要求9所述的工艺，其中，耦合包括将所述管芯上的电容器焊料突起耦合到所述顶部电极，并将所述管芯上的电源焊料突起或信号焊料突起耦合到所述电镀通孔。
11.如权利要求9所述的工艺，其中，形成介电层包括通过设置在所述核心层上方的模版来形成所述介电层。
12.如权利要求9所述的工艺，其中，形成所述顶部电极和所述底部电极其中之一包括完成所述电镀通孔。
13.如权利要求9所述的工艺，在耦合之前，所述工艺还包括：
用焊接掩模层来覆盖所述第一侧；
对所述焊接掩模层形成图案，以便暴露所述顶部电极的至少一部分以及所述电镀通孔的至少一部分。
14.一种工艺，包括：
在衬底上形成焊接掩模；
对所述焊接掩模第一形成图案，以便暴露底部电极；
在所述底部电极上形成介电膜，其中，所述介电膜和所述焊接掩模共享共面表面；
对所述焊接掩模第二形成图案，以便暴露至少第一键合指垫和管芯焊盘；以及
在所述介电膜上方电镀顶部电极。
15.如权利要求14所述的工艺，还包括在第二形成图案期间暴露的管芯焊盘处定位管芯。
16.如权利要求14所述的工艺，还包括：
在第二形成图案期间暴露的管芯焊盘处定位管芯；以及
通过将所述管芯耦合到所述顶部电极，而对所述管芯进行第一丝焊。
17.如权利要求14所述的工艺，还包括：
在第二形成图案期间暴露的管芯焊盘处定位管芯；
通过将所述管芯耦合到电源环和地环之一而对所述管芯进行第一丝焊；以及
通过将所述管芯耦合到键合指上部而对所述管芯进行第二次丝焊。
18.一种系统，包括：
底部电极；
介电膜，包括第一表面和第二表面，其中，所述介电膜设置在所述底部电极上方和所述底部电极上面；
结构层，设置成邻近所述介电膜并与其接触，其中，所述结构层在所述第一表面和所述第二表面的至少一个上与所述介电膜基本上共面，以及其中，所述结构层是焊接掩模和核心层中的至少一个；
顶部电极，设置在所述介电膜上方和所述介电膜上面；
管芯，耦合到所述顶部电极；以及
动态随机存取数据存储器，与所述管芯耦合。
19.如权利要求18所述的系统，其中，所述管芯设置在焊接掩模层中。
20.如权利要求18所述的系统，其中，所述结构层是核心层，并且还包括设置成邻近于所述介电膜并通过所述核心层与所述介电膜间隔开的电镀通孔。
21.如权利要求18所述的系统，其中，所述系统设置在如下之一中：计算机、无线通信器、手持装置、汽车、机车、飞行器、船只和太空船。
22.如权利要求18所述的系统，其中，所述管芯从数据存储装置、数字信号处理器、微控制器、专用集成电路和微处理器中选取。
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US20070158818A1 (en) 2007-07-12
KR20110107876A (ko) 2011-10-04
WO2007078714A3 (en) 2007-10-04
US7670919B2 (en) 2010-03-02
CN101351873B (zh) 2010-09-01
KR101312135B1 (ko) 2013-09-26
KR20080081291A (ko) 2008-09-09
KR20130056365A (ko) 2013-05-29
TWI334615B (en) 2010-12-11
WO2007078714A2 (en) 2007-07-12
US20100059858A1 (en) 2010-03-11
TW200733161A (en) 2007-09-01
US7989916B2 (en) 2011-08-02

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