CN101339929A - 半导体元件、超薄晶粒封装体与半导体晶粒封装体 - Google Patents

半导体元件、超薄晶粒封装体与半导体晶粒封装体 Download PDF

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CN101339929A
CN101339929A CNA2007101939958A CN200710193995A CN101339929A CN 101339929 A CN101339929 A CN 101339929A CN A2007101939958 A CNA2007101939958 A CN A2007101939958A CN 200710193995 A CN200710193995 A CN 200710193995A CN 101339929 A CN101339929 A CN 101339929A
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package body
die package
welding
corner
semiconductor
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CN101339929B (zh
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李新辉
李明机
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明为一种半导体元件、超薄晶粒封装体与半导体晶粒封装体，该半导体元件为晶片级芯片尺寸封装(wafer level chip size packaging，WLCSP)结构，包括半导体晶粒，其具有多个突出物在该半导体晶粒的表面，用以与有源层间提供电性连接。各突出物不高于该半导体晶粒的表面10μm以上。本元件也具有多个焊棒设置在该晶粒的角落，其中各焊棒不高于该半导体晶粒的表面10μm以上。本发明还提供一种超薄晶粒封装体与一种半导体晶粒封装体。本发明为半导体元件提供了超薄封装高度。更进一步，在晶粒角落额外设置的焊接棒还增强了焊接点的可靠度。

Description

半导体元件、超薄晶粒封装体与半导体晶粒封装体
技术领域
本发明涉及晶片级芯片尺寸封装，且特别涉及在晶片级芯片尺寸封装中使用的超薄接触栅格阵列。
背景技术
过去数十年间已经见到许多电子技术与半导体封装的发展，其影响了整个电子产业。表面粘着技术(surface mount technology，SMT)、球栅阵列(ballgrid array，BGA)与基板栅格阵列(land grid array，LGA)封装对于多种集成电路的高产能装配为重要步骤，且同时允许减少印刷电路板上的连接垫间距。一般经封装的集成电路是通过细金线来连结在晶粒上的金属垫与分布在铸模树脂封装体外的电极。双列直插式封装(dual inline package，DIP)或四面扁平封装(quad flat package，QFP)为现今集成电路封装的基本结构。然而增加封装体外围的针脚数通常会导致铅线间距太短，而在封装芯片的基板架设中产生限制。
芯片级或芯片尺寸封装(chip-size packaging，CSP)、球栅阵列与基板栅格阵列正好是使电极密集而不需增加封装尺寸的一些方法。芯片级封装提供了在芯片尺寸上的晶片封装。芯片级封装通常产生1.2倍晶粒尺寸内的封装体，其大幅减低了元件潜在的尺寸。虽然这些发展已使电子元件缩小化，但永远要求朝向更小、更轻与更薄的消耗产品促使封装需要更加缩小化。
为了满足朝向缩小化与功能性的市场需求，近几年引进晶片级芯片尺寸封装以增加密度、性能与成本效益，而减少了电子封装产业中元件的重量与尺寸。在晶片级芯片尺寸封装中，一般直接在晶粒上产生封装，并由球栅阵列或基板栅格阵列提供接点。近来所发展的电子元件，例如移动电话、移动电脑、摄录像机、个人电子助理(personal digital assistants，PDAs)等使用小型、轻、薄与非常密集的封装集成电路。使用晶片级芯片尺寸封装可封装针脚数目较少的较小晶粒，可增加同一晶片上的芯片数目，因此通常较具有优势与经济效益。然而，相对而言第二层连接器，即在半导体封装与印刷电路板间的连接器仍然相当高-介于0.2与0.3mm之间。
目前晶片级芯片尺寸封装接触技术的一个缺点为封装尺寸与晶粒尺寸越来越小，但连接器的高度却维持不变。图1为晶粒封装体10的剖面图。晶粒封装体10包括半导体元件100与焊球101，位于凸块底层金属(under-bump metallurgy，UBM)层102之上，其沉积于晶粒封装体10之上以帮助设置。焊球的传统封装高度为0.2-0.3mm。不论可以制造多小的晶粒封装体10，焊球101的高度仍维持在0.2-0.3mm。
目前晶片级芯片尺寸封装接触技术的第二个缺点为在焊球阵列中所产生的应力。在传统引脚封装中，通过鸥翼型的引线来释放应力。在面阵列(area-array)焊球封装中，应力一般集中在焊接点(solderjoint)中。于封装寿命周期中，接触应力常使焊接点失败。在晶片级芯片尺寸封装技术中，与应力/可靠度相关的重要机械性参数为：(a)相距中性点的球距(distance from neutralpoint，DNP)，其为通过芯片尺寸与凸块间距来决定；(b)凸块均衡(bumpstandoff)；(c)凸块的数目。相距中性点的球距越大(即凸块离中性点越远)，在焊接凸块中与下层表面上所产生的应力就越大。因此离晶粒中性点最远的焊接凸块，其焊接点失败的问题最严重。现今用来降低或释放面阵列接触封装的应力的方法包括，维持较大的焊球或沉积材料层包围着凸块，其热膨胀系数与下层的封装相似。较相配的热膨胀系数会减少在焊接点上的应力。然而，增加包围层会增加晶粒制造的材料与工艺步骤。
发明内容
通过本发明的实施例可解决或防止上述或其他的问题，且通常可达到技术性优势，而本发明的实施例提供低高度突出物或连结器的阵列，其各高于晶粒封装体表面10μm或比10μm小。为了补偿在此种晶片级芯片尺寸封装结构所发生的可靠度问题，在晶粒角落放置一系列的焊接棒或角落棒状物。这些焊接棒为在晶粒上离中性点最远的焊接点提供额外的邻近表面区域，因此增加了所有晶粒连接的可靠度。
本发明提供一种半导体元件，包括半导体晶粒，其具有多个突出物，在印刷电路板与该半导体晶粒间提供电性连接，其中各突出物不高于该半导体晶粒的表面10μm以上。本元件也具有多个焊棒，设置在该晶粒的角落，其中各焊棒不高于该半导体晶粒的表面10μm以上。
如上所述的半导体元件，其中该每一个突出物与该每一个焊棒具有下述剖面形状之一：蕈状；以及柱状。
如上所述的半导体元件，还包括：焊接增强薄膜，设置在该多个突出物与多个焊棒之上。
如上所述的半导体元件，其中该焊接增强薄膜是由选自由下列所组成的群组之一的材料所形成：金；铂；以及金铂合金。
如上所述的半导体元件，还包括重分布层，其在该多个突出物与该多个焊棒间提供连接。
如上所述的半导体元件，其中该每一个焊棒具有下述平面形状之一：L形；矩形；以及几何图形，其长度大于其宽度。本发明还提供一种超薄晶粒封装体，包括多个突出物，设置在该超薄晶粒封装体的连接表面上，其中各突出物延伸出该连接表面小于或等于10μm。该晶粒封装体也包括角落棒状物，设置在该超薄晶粒封装体的各角落，其中该角落棒状物的表面区域大于该多个突出物之一，且延伸出该连接表面的距离约等于该多个突出物。
如上所述的超薄晶粒封装体，还包括：增强薄膜，沉积于该多个突出物的每一个突出物与该角落棒状物上。
如上所述的超薄晶粒封装体，该增强薄膜选自由下列所组成的群组之一：金；铂；以及金铂合金
如上所述的超薄晶粒封装体，其中该多个突出物与该角落棒状物具有下述剖面形状之一：蘑菇状；以及柱状。
如上所述的超薄晶粒封装体，其中该角落棒状物具有下述平面形状之一：L形；矩形；以及几何图形，其长度大于其宽度。
本发明还提供一种半导体晶粒封装体，包括多层晶粒，具有从该多层晶粒的表面延伸的连接器阵列，其中各连接器延伸出该表面的距离小于或等于10μm。多个焊棒，设置在该半导体晶粒封装体的各角落，其中该多个焊棒从该表面延伸的高度约等于该连接器的延伸距离。
如上所述的半导体晶粒封装体，还包括焊接增强薄膜在该连接器阵列与该多个焊棒上，其中该焊接增强薄膜为无铅材料。
如上所述的半导体晶粒封装体，其中该连接器阵列的每一个连接器与该多个焊棒的每一个焊棒具有下述剖面形状之一：蘑菇状；以及柱状。
如上所述的半导体晶粒封装体，其中该多个焊棒的每一个焊棒具有下述平面形状之一：L形；矩形；以及几何图形，其长度大于其宽度。
本发明较佳实施例的优点为：其为半导体元件提供了超薄封装高度。
本发明较佳实施例的更进一步优点为：在晶粒角落，额外的焊接棒增强了焊接点的可靠度。
为了让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举较佳实施例，并配合附图，作详细说明如下。
附图说明
图1显示传统晶粒封装体的剖面图。
图2显示本发明一个实施例的晶片级芯片尺寸封装结构的剖面图。
图3显示本发明一个实施例的晶片级芯片尺寸封装结构的剖面图。
图4A显示本发明一个实施例的晶粒封装体的平面图，其使用晶片级芯片尺寸封装结构来配置。
图4B显示本发明一个实施例的晶粒封装体的剖面图，其使用晶片级芯片尺寸封装结构来配置。
图5显示本发明一个实施例的超薄晶粒封装体的平面图，其使用晶片级芯片尺寸封装结构来配置。
其中，附图标记说明如下：
10～晶粒封装体
100～半导体元件
101～焊球
102～凸块底层金属层
20、30～晶片级芯片尺寸封装结构
200、300、40～晶粒封装体
201、301～重分布层
202、302、401～低高度突出物
303～增强薄膜
40～晶粒封装体
400～晶粒表面
402～角落棒状物
403～晶粒
50～超薄晶粒封装体
500～晶粒晶片
501～焊接突出物
502～焊接棒
具体实施方式
图2显示本发明一个实施例的晶片级芯片尺寸封装结构20的剖面图。晶片级芯片尺寸封装结构20包括低高度突出物202，其形成于晶粒封装体200之上。晶粒封装体200为常见的晶粒，具有多层半导体材料，包括重分布层201，其提供低高度突出物202与晶粒封装体200的有源部分的连接。低高度突出物202连接至印刷电路板(未显示)，以提供印刷电路板至晶粒封装体200的有源部分的电性连接。
在本发明的一个较佳实施例中，低高度突出物202比晶粒封装体200的表面高出10μm。需注意的是在本发明的额外及/或替代实施例中，低高度突出物202的高度可小于10μm，且仍然高于晶粒封装体200的表面。
需注意的是，叙述与示出于图2的本发明实施例只显示单一阵列的连接器/突出物。为了简明，只显示单一连接器。实际上，根据本发明实施例，晶粒封装体可配置数十或数百个阵列连接器。因此，此处的附图只示出一个或者少数阵列连接器是为了简单说明，并不限制本发明只具有特定数目的突出物或连接器。
图3显示本发明一个实施例的晶片级芯片尺寸封装结构30的剖面图。晶片级芯片尺寸封装结构30包括低高度突出物302，其形成于晶粒封装体300之上。晶粒封装体300包括多层半导体材料，包括重分布层301。图3中的晶片级芯片尺寸封装结构30的实施例显示，低高度突出物302的形状为蕈状，其包括块状物延伸于晶粒封装体300的顶部上。此外，在低高度突出物302的顶部上沉积增强薄膜303，以增强晶片级芯片尺寸封装结构30的焊接能力与可靠度。
需注意的是在本发明一个较佳实施例中，连接器与重分布层所使用的材料于制造时不使用铅。使用无铅材料可制造与环境更相容的元件。可使用来当作增强薄膜303的无铅材料的例子为金、铂、金铂合金或上述的类似物。
图4A显示本发明一个实施例的晶粒封装体40的平面图，其使用晶片级芯片尺寸封装结构来配置。晶粒封装体40包括低高度突出物401，其沉积于晶粒表面400上的面阵列中。在晶片级芯片尺寸封装技术中，与中性点的距离让传统焊接凸块与焊球的焊接点可靠度降低。当凸块的高度降低时，自然发生于焊接点中的压力或应力就不会散布于较小的结构上。然而，为了增强焊接点的可靠度，可在晶粒封装体40的角落设置角落棒状物402。通过角落棒状物来增加覆盖的区域，其位于在晶粒封装体40上相距中性点的最大距离处，增加了晶粒封装体40全部焊接点的可靠度。
图4B显示本发明一个实施例的晶粒封装体40的剖面图，其使用晶片级芯片尺寸封装结构来配置。角落棒状物402约与低高度突出物401相同高度，且形成在晶粒403的晶粒表面400中。当之后将晶粒封装体40连接至终点位置，焊接点区域不只发生在低高度突出物401的接点，还包括角落棒状物402的较大相邻区域。此增加的焊接点区域增加与增强了晶粒封装体40的整体连接的可靠度。
需注意的是在本发明的额外及/或替代实施例中，焊接棒，例如角落棒状物402的剖面形状可以是蕈状，如图4B所示，或者可以是简单的筒状或柱状。更需注意的是，虽然角落棒状物402显示为L形，但也可使用其他形状以利于增强晶粒封装体的焊接能力与可靠度。此外，本发明的额外及/或替代实施例可在角落棒状物402的顶部上沉积焊接增强薄膜，例如增强薄膜303(图3)以增强实施例结构的焊接能力与可靠度。
图5显示本发明一个实施例的超薄晶粒封装体50的平面图，其使用晶片级芯片尺寸封装结构来配置。显示于图5的实施例通过增加焊接棒502至晶粒封装体50的角落来增强焊接点的可靠度。以焊接棒502所覆盖的增加的区域，其位于在晶粒晶片500上相距中性点的最大距离，增加了焊接突出物501的所有焊接点的可靠度。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (15)

1.一种半导体元件，包括：
半导体晶粒；
多个突出物，在印刷电路板与该半导体晶粒间提供电性连接，其中该多个突出物的每一个突出物不高于该半导体晶粒的表面10μm以上；以及
多个焊棒，设置在该晶粒的角落，其中该多个焊棒的每一个焊棒不高于该半导体晶粒的表面10μm以上。
2.如权利要求1所述的半导体元件，其中该每一个突出物与该每一个焊棒具有下述剖面形状之一：
蕈状；以及
柱状。
3.如权利要求1所述的半导体元件，还包括：焊接增强薄膜，设置在该多个突出物与多个焊棒之上。
4.如权利要求3所述的半导体元件，其中该焊接增强薄膜是由选自由下列所组成的群组之一的材料所形成：
金；
铂；以及
金铂合金。
5.如权利要求1所述的半导体元件，还包括重分布层，其在该多个突出物与该多个焊棒间提供连接。
6.如权利要求1所述的半导体元件，其中该每一个焊棒具有下述平面形状之一：
L形；
矩形；以及
几何图形，其长度大于其宽度。
7.一种超薄晶粒封装体，包括：
多个突出物，设置在该超薄晶粒封装体的连接表面上，其中该多个突出物的每一个突出物延伸出该连接表面小于或等于10μm；以及
角落棒状物，设置在该超薄晶粒封装体的各角落，其中该角落棒状物的表面区域大于该多个突出物之一，且延伸出该连接表面的距离约等于该多个突出物。
8.如权利要求7所述的超薄晶粒封装体，还包括：增强薄膜，沉积于该多个突出物的每一个突出物与该角落棒状物上。
9.如权利要求8所述的超薄晶粒封装体，其中该增强薄膜选自由下列所组成的群组之一：
金；
铂；以及
金铂合金。
10.如权利要求7所述的超薄晶粒封装体，其中该多个突出物与各角落棒状物具有下述剖面形状之一：
蕈状；以及
柱状。
11.如权利要求7所述的超薄晶粒封装体，其中各该角落棒状物具有下述平面形状之一：
L形；
矩形；以及
几何图形，其长度大于其宽度。
12.一种半导体晶粒封装体，包括：
多层晶粒；
连接器阵列，从该多层晶粒的表面延伸，其中各该连接器延伸出该表面小于或等于10μm；以及
多个焊棒，设置在该半导体晶粒封装体的各角落，其中该多个焊棒从该表面延伸的高度约等于该连接器。
13.如权利要求12所述的半导体晶粒封装体，还包括：焊接增强薄膜，设置在该连接器阵列与该多个焊棒上，其中该焊接增强薄膜为无铅。
14.如权利要求12所述的半导体晶粒封装体，其中各该连接器与该多个焊棒的每一个焊棒具有下述剖面形状之一：
蕈状；以及
柱状。
15.如权利要求12所述的半导体晶粒封装体，其中该多个焊棒的每一个焊棒具有下述平面形状之一：
L形；
矩形；以及
几何图形，其长度大于其宽度。
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