CN101325198A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN101325198A CN101325198A CNA2008101094797A CN200810109479A CN101325198A CN 101325198 A CN101325198 A CN 101325198A CN A2008101094797 A CNA2008101094797 A CN A2008101094797A CN 200810109479 A CN200810109479 A CN 200810109479A CN 101325198 A CN101325198 A CN 101325198A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 279
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 210000000746 body region Anatomy 0.000 claims abstract description 39
- 238000009792 diffusion process Methods 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 41
- 238000010586 diagram Methods 0.000 description 31
- 238000004088 simulation Methods 0.000 description 18
- 230000005684 electric field Effects 0.000 description 15
- 238000012986 modification Methods 0.000 description 14
- 230000004048 modification Effects 0.000 description 14
- 238000011084 recovery Methods 0.000 description 14
- 238000009826 distribution Methods 0.000 description 10
- 239000002800 charge carrier Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000013459 approach Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
A semiconductor device includes a spaced-channel IGBT and an antiparalell diode that are formed in a same semiconductor substrate (31). The IGBT includes a base layer (32) and insulated gate trenches (GT) by which the base layer (32) is divided into a body region (32b) connected to an emitter electrode (E) and a floating region (32f) disconnected from the emitter electrode (E). The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing (Wx) between adjacent gate trenches (GT) in the boundary region is less than a spacing (Wf) between adjacent gate trenches (GT) between which the floating region (32f) is located in the cell region.
Description
Specification
The present invention relates to a kind of semiconductor device that all is formed at interval trench igbt in the semi-conductive substrate and inverse parallel diode that comprises.
As everyone knows, inverter circuit becomes to exchange (AC) voltage and supplies with AC voltage to the inductive load (that is inductance L) such as induction motor direct current (DC) voltage transitions.For example, utilize the such inverter circuit of semiconductor device 100 structures shown in Figure 23 A.Semiconductor device 100 comprises igbt (IGBT) 100i and the inverse parallel diode 100d that is connected with IGBT 100i inverse parallel.
Utilize six semiconductor device 100 to be configured for producing the inverter circuit of three-phase AC voltage.As shown in Figure 23 B, utilize two semiconductor device 100 that between DC power supply and ground potential, are connected in series to produce each mutually.IGBT 100i is as switch element.Inverse parallel diode 100d is as free-wheel diode.When closing IGBT 100i, the load current of the inductance (not shown) that is connected in output of the flowing through diode 100d that can flow through.Therefore, can prevent the flip-flop of load current.This diode 100d is known as free-wheel diode (FWD).
Semiconductor device 100 can so be realized so that in the Semiconductor substrate (chip) of separating, form IGBT 100i and diode 100d.Yet,, preferably in semi-conductive substrate, form IGBT 100i and diode 100d in order to reduce the size of semiconductor device 100.
Figure 24 is illustrated in corresponding to disclosed semiconductor device 91 among the US 7,154,145 of JP-A-2005-101514.In this semiconductor device 91, in semi-conductive substrate, form IGBT and inverse parallel diode.Particularly, for each IGBT unit, p type base layer (trap) 2 is formed at N
-On first side of N-type semiconductor N substrate 1.N
+Type cathode layer 4 and P
+Type collector layer 5 be formed on second side of Semiconductor substrate 1 and be positioned at base layer 2 under.The p type base layer 2 of each IGBT unit comprises the first and second side diffusion zone 2SDR1,2SDR2 and the flat site 2FR between the first and second side diffusion zone 2SDR1,2SDR2.Flat site 2FR has emitter region 3 and is insulated the lower surface that gate groove 6 penetrates.The first side diffusion zone 2SDR1 is positioned at N
+Directly over the type cathode layer 4.N
+Type cathode layer 4 and P
+Type collector layer 5 is adjacent.Utilize N
-N-type semiconductor N substrate 1, p type base layer 2 and N
+Type cathode layer 4 structure diodes.The emission electrode 10 of IGBT unit is integrated with the anode electrode of diode, and the collector electrode 11 of IGBT is integrated with the cathode electrode of diode.Therefore, diode is connected with the inverse parallel of IGBT unit.
IGBT unit in the semiconductor device 91 is trench-gate IGBT.In trench-gate IGBT, form raceway groove so that can increase gully density in insulated gate groove both sides.Therefore, IGBT compares with planar gate, and trench-gate IGBT can have low conducting voltage.
Figure 25 is illustrated in corresponding to disclosed trench-gate IGBT 92 among the US 6,737,705 of JP-A-2001-308327.This IGBT 92 is designed to not only realize that low conducting voltage also obtains low switching loss, reduces total loss thus.As shown in Figure 25, IGBT 92 comprises silicon substrate 21, light dope N type drift layer 22, P type base layer 23, N
+ Type source area 24, be arranged in gate oxidation films 25 in the groove that penetrates p type base layer 23, be arranged in gate electrode 26, interlayer dielectric 27 in the groove, be connected in N by this gate oxidation films 25
+The emission electrode 28 of type source area 24 and the collector electrode 29 that is connected in the apparent surface of silicon substrate 21.Groove is divided into body region 23a and float zone 23b with p type base layer 23.Body region 23a is connected in emission electrode 28 and has the N that locatees adjacent to groove
+Type source region 24.Therefore, body region 23a is as channel region.Float zone 23b is free of attachment to emission electrode 28 and does not have N
+Type source region 24.Float zone 23b is as the charge carrier storage area of storage charge carrier.
As mentioned above, IGBT 92i has a kind of structure, in this structure, by charge carrier storage area (that is float zone 23b) channel region (that is body region 23a) is separated mutually.Therefore, the IGBT as IGBT 92i is known as " raceway groove IGBT at interval " hereinafter.According to US 6,737,705, when the ratio of the width of the width of body region 23a and float zone 23b during from 1: 2 to 1: 7, IGBT 92i has low conducting voltage and low switching loss, to such an extent as to can reduce total loss.
In the time will being applied to be used for the semiconductor device of inverter circuit, preferably in semi-conductive substrate, form raceway groove IGBT and inverse parallel diode at interval as the interval raceway groove IGBT of IGBT 92i.In this method, the semiconductor device 91 shown in the image pattern 24 is such, can reduce size of semiconductor device.Yet, when in semi-conductive substrate, forming at interval raceway groove IGBT and inverse parallel diode, between interval raceway groove IGBT and inverse parallel diode, can have mutual interference mutually.
Because above-mentioned problem, the purpose of this invention is to provide a kind of semiconductor device with the structure that is used for reducing the mutual interference mutually between the interval raceway groove IGBT that forms with semi-conductive substrate and inverse parallel diode.
Realize semiconductor device having on first side and the first conductive-type semiconductor substrate with respect to second side of first side.This substrate comprises that transistor area and inverse parallel are connected in the diode area of transistor area.Transistor area comprise the surface portion of first side that is formed up to substrate the second conductivity type base layer, be formed up to base layer a plurality of insulated gate grooves, be formed up to substrate second side surface portion second conductivity type, first diffusion layer and be formed on emission electrode on first side of substrate.Diode area comprises first conductivity type, second diffusion layer of the surface portion of second side that is formed up to substrate.Second diffusion layer has the impurity concentration higher than substrate.Diode area comprises and is repeated to arrange and be combined in together to form a plurality of diodes of a diode.Transistor area comprises unit area and the borderline region between unit area and diode area.In the unit area, base layer is divided into a plurality of body region and a plurality of float zone by a plurality of insulated gate grooves.Alternately arrange body and float zone.Each body region is connected in emission electrode, and each float zone is not attached to emission electrode.The unit area comprises and is repeated to arrange and be combined in together to form the trench igbt unit, a plurality of interval of trench igbt at interval.Each transistor unit has corresponding in corresponding and a plurality of float zone in a plurality of body region.In borderline region, base layer is divided into a plurality of zones that are divided by a plurality of insulated gate grooves.Interval between the adjacent insulated gate groove in the borderline region is less than the interval between the adjacent insulated gate groove in the unit area, between the adjacent insulated gate groove of each float zone in the unit area.
By the following detailed description with accompanying drawings, above and other objects of the present invention, feature and advantage will become apparent.In the accompanying drawings:
Fig. 1 is the schematic diagram that the cross-sectional view of the semiconductor device that is used for first simulation is shown;
Fig. 2 is the equivalent circuit diagram that the circuit model of the inverter circuit that is used for first simulation is shown;
Fig. 3 be illustrate by with the semiconductor device application of Fig. 1 in the electric current of first Simulation result that circuit model carried out of Fig. 2 and semiconductor device that Fig. 1 is shown and the schematic diagram of temperature;
Fig. 4 A illustrates first Simulation result and is illustrated in the schematic diagram that the hole current density in the semiconductor device of P1 Fig. 1 constantly of Fig. 3 distributes, and Fig. 4 B illustrates first Simulation result it is illustrated in the schematic diagram that the hole current density in the semiconductor device of P2 Fig. 1 constantly of Fig. 3 distributes;
Fig. 5 A illustrates first Simulation result and is illustrated in the schematic diagram that the hole current density in the semiconductor device of P3 Fig. 1 constantly of Fig. 3 distributes, and Fig. 5 B illustrates first Simulation result and is illustrated in the schematic diagram that the hole current density in the semiconductor device of P4 Fig. 1 constantly of Fig. 3 distributes;
Fig. 6 A is the schematic diagram that first Simulation result is shown and is illustrated in the electric field strength in the semiconductor device of P4 Fig. 1 constantly of Fig. 3, and Fig. 6 B illustrates first Simulation result and is illustrated in the schematic diagram that charge carrier in the semiconductor device of P4 Fig. 1 constantly of Fig. 3 produces distributed number;
Fig. 7 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of first embodiment of the invention;
Fig. 8 be illustrate by with the semiconductor device application of Fig. 7 in the electric current of second Simulation result that circuit model carried out of Fig. 2 and semiconductor device that Fig. 7 is shown and the schematic diagram of temperature;
Fig. 9 illustrates second Simulation result and is illustrated in the schematic diagram that the hole current density of semiconductor device of P5 Fig. 7 constantly of Fig. 8 distributes;
Figure 10 A is the schematic diagram that second Simulation result is shown and is illustrated in the electric field strength in the semiconductor device of P5 Fig. 7 constantly of Fig. 8, and Figure 10 B illustrates second Simulation result and is illustrated in the schematic diagram that charge carrier in the semiconductor device of P5 Fig. 7 constantly of Fig. 8 produces distributed number;
Figure 11 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of the modification of the semiconductor device of Fig. 7;
Figure 12 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of another modification of the semiconductor device of Fig. 7;
Figure 13 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of the modification of the semiconductor device of Figure 11;
Figure 14 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of another modification of the semiconductor device of Fig. 7;
Figure 15 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of the modification of the semiconductor device of Figure 14;
Figure 16 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of another modification of the semiconductor device of Fig. 7;
Figure 17 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of second embodiment of the invention;
Figure 18 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of third embodiment of the invention;
Figure 19 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of the application example of the semiconductor device of Figure 18;
Figure 20 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of the Another Application example of the semiconductor device of Figure 18;
Figure 21 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of the modification of the semiconductor device of Figure 18;
Figure 22 is the schematic diagram that illustrates according to the cross-sectional view of the semiconductor device of another modification of the semiconductor device of Figure 18;
Figure 23 A is the circuit diagram that the basic module of inverter circuit is shown, and Figure 23 B is the circuit diagram that the elementary cell that is used for each phase of inverter circuit is shown;
Figure 24 is the schematic diagram that the cross-sectional view of conventional semiconductor device is shown; And
Figure 25 is the schematic diagram that the cross-sectional view of another conventional semiconductor device is shown.
The present invention relates to all be formed on the interval trench igbt (IGBT) in the semi-conductive substrate and the semiconductor device of inverse parallel diode a kind of comprising.Raceway groove IGBT has float zone at interval, by this float zone channel region is separated each other.Compare with the conventional IGBT that does not have float zone with reference to as described in Figure 25 as previous, this interval raceway groove IGBT with float zone not only can have low conducting voltage, also has low switching loss.
Normally, when IGBT was formed in the same first conductive-type semiconductor substrate with the diode that is connected with the IGBT inverse parallel, the body region (that is channel region) that is connected in the emission electrode of IGBT had second conductivity type.Because the anode electrode of diode also has second conductivity type, the emission electrode of IGBT is connected in the anode electrode of diode.As a result, similar with semiconductor device shown in Figure 24 91, the body region of IGBT is served as the parasitic body diode that causes mutual interference mutually between IGBT and diode.
With reference to as described in the figure 23A, comprise that the semiconductor device of IGBT and inverse parallel diode uses in pairs with the structure inverter circuit as previous.In this case, especially, the diode reverse recovery characteristic of phase mutual interference becomes problem.Especially, when diode is used as free-wheel diode in inverter circuit, switches to the moment that ends reverse overshoot current at diode by conducting and flow.
Be formed at the general IGBT that does not have float zone of semi-conductive substrate and the semiconductor device of diode about comprising, know, because the charge carrier of storing during the turn-on cycle of diode causes reverse overshoot current at diode by the fact that conducting switches to the moment outflow that ends.
To this comprise being formed at the general IGBT that does not have float zone in the semi-conductive substrate and the semiconductor device of diode carried out some researchs.Yet, almost do not carry out research to comprising the semiconductor device that is formed at interval raceway groove IGBT in the semi-conductive substrate and diode with float zone.How will continue elaboration interval raceway groove IGBT and diode interferes with each other.
In order to determine to be formed at interval raceway groove IGBT in the semi-conductive substrate and the phase mutual interference between the diode, the inventor has carried out the characteristic of simulation with the semiconductor device 110 shown in the evaluation graph 1.In semiconductor device 110, raceway groove IGBT is formed at same N with the diode that is connected with the IGBT inverse parallel at interval
-In the conductive-type semiconductor substrate 31.In the IGBT zone, a plurality of IGBT unit combination (that is, are repeated to arrange) with formation IGBT together, and in diode area, a plurality of diodes are combined to form diode.As can be seen from Figure 1, be arranged to IGBT and diode adjacent one another are simply.
In the IGBT zone, P conductivity type base layer 32 is formed up to the surf zone of first side of Semiconductor substrate 31.By insulated gate groove GT base layer 32 is divided into body region 32b and float zone 32f.As shown in fig. 1, body region 32b is connected in the emission electrode E of IGBT, and float zone 32f is not attached to emission electrode E.N as the emitter region of IGBT
+ Conductive area 37 is formed at body region 32b and contacts with gate groove GT.With P
+Conductivity type first diffusion layer 33 be formed up to Semiconductor substrate 31 second side surf zone and be arranged to relative with base layer 32.First diffusion layer 33 is connected to the collector electrode C of IGBT.On first diffusion layer 33, form N conductive layer 34 as the field cutoff layer of IGBT.
In diode area, with P
+ Conductive area 35 is formed up to the surf zone of first side of Semiconductor substrate 31.This zone 35 is connected in the anode electrode A of diode.With N
+Conductivity type second diffusion layer 36 be formed up to Semiconductor substrate 31 second side surf zone and be arranged to 35 relative with the zone.Second diffusion layer 36 has than the high impurity concentration of Semiconductor substrate 31 and is connected to the cathode electrode K of diode.
As can be seen from Figure 1, the emission electrode E of IGBT and the anode electrode A of diode integrate (that is, connecting) mutually, and the cathode electrode K of the collector electrode C of IGBT and diode integrates mutually.Therefore, diode is connected with the IGBT inverse parallel.
The inventor simulates by the semiconductor device 101,102 that the semiconductor device shown in Fig. 1 110 is applied to the circuit model M1 shown in Fig. 2.With the grid of the IGBT of semiconductor device 102 and emitter terminal short circuit together with simulation when the diode 102d of semiconductor device 102 from conducting switch to by the time moment (, the moment when the IGBT of semiconductor device 101 101 i switch to conducting from ending).In this simulation, the IGBT 101i of semiconductor device 101 is as switching device, and the diode 102d of semiconductor device 102 is as free-wheel diode (FWD).
Fig. 3-6B describes the Simulation result of being carried out is used as the semiconductor device 110 of the semiconductor device 101,102 among the circuit model M1 with assessment characteristic.Fig. 3 illustrates the temperature of the total current Id and the semiconductor device 110 of the entire semiconductor device 110 of flowing through.In Fig. 3, solid line is represented total current Id, long dotted line represent the to flow through electric current I dd of diode of semiconductor device 110, the electric current I di of the IGBT of semiconductor device 110 and short dash line is represented to flow through.The hole current density that Fig. 4 A is illustrated in the semiconductor device 110 of moment P1 of Fig. 3 distributes.The hole current density that Fig. 4 B is illustrated in the semiconductor device 110 of moment P2 of Fig. 3 distributes.The hole current density that Fig. 5 A is illustrated in the semiconductor device 110 of moment P3 of Fig. 3 distributes.The hole current density that Fig. 5 B is illustrated in the semiconductor device 110 of moment P4 of Fig. 3 distributes.In Fig. 4 A, 4B, 5A and 5B, go out the hole electric current distribution by utilizing isopycnic and arrow indicative icon.Isopycnic connects the wherein equal point of current density.Arrow has length and the thickness that changes along with current density.
The current concentration that destroys semiconductor device 110 is by being stored in N
-Hole in the conductive-type semiconductor substrate 31 causes from the fact that Semiconductor substrate 31 upwards flows out and quilt is concentrated owing to the structure of semiconductor 110.Consider above-mentioned reason,, analyze hole current density and distribute important more than the analytical electron electric current distribution in order to determine the reason of current concentration.Therefore, shown in Fig. 4 A-5B, the inventor by analysis the hole current density distribution.
In semiconductor device 110, as shown in Figure 3, when diode is in conducting state, 306 amperes the electric current I dd diode of flowing through, and 100 amperes the electric current I di IGBT that flows through.As shown in Fig. 4 A, 100 amperes the electric current I di body region 32b that flows through, this body region 32b can serve as parasitic body diode.Get back to Fig. 3, when diode from conducting switch to by the time, during diode reverse recovery, the high reverse overshoot current Id semiconductor device 110 of flowing through to negative 147 amperes.The major part of overshoot current Id is the electric current I di up to negative 121 amperes of IGBT of flowing through.As from Fig. 5 B as can be seen, more near diode area, overshoot current density is big more.For example, 46897A/cm
2Maximum current density appear in the body diode of the IGBT unit that is bordering on diode area most.Generally speaking, analog result shows that current concentration appears near the diode area.
The electric field strength of the boundary vicinity when Fig. 6 A is illustrated in the moment P4 of Fig. 3 between IGBT zone and the diode area.The distribution of the charge carrier amount that produces at boundary vicinity by ionization by collision when Fig. 6 B is illustrated in the moment P4 of Fig. 3.
As shown in Fig. 6 A, at moment P4 place, the electric field strength below the gate trench GT of the IGBT unit that approaches diode area most is up to 0.53 MV/cm.As shown in Fig. 6 B, at moment P4 place, the current-carrying that produces below the gate trench GT of the IGBT unit that approaches diode area most is in measuring up to 3.2 * 10
27Right/cm
3Sec.Therefore, analog result shows: during diode reverse recovery, and concentrated electric field below the gate trench GT of the IGBT unit that approaches diode area most.As a result, at the voltage place much smaller than the puncture voltage of IGBT unit avalanche breakdown takes place, and current concentration takes place.As a result, the IGBT unit that approaches diode area most can be destroyed by current concentration.
Conclusion based on obtaining from analog result describes below the semiconductor device according to the embodiment of the invention.
(first embodiment)
Fig. 7 illustrates the semiconductor device 200 according to first embodiment of the invention.
Similar to the semiconductor device 110 shown in Fig. 1, semiconductor device 200 comprises that interval raceway groove IGBT and inverse parallel are connected in the diode of IGBT.At same N
-Form IGBT and diode in the conductive-type semiconductor substrate 31.In the IGBT zone, a plurality of IGBT unit combination (are repeated to arrange) with formation IGBT together, and in diode area, a plurality of diodes are combined to form diode.
Difference between the semiconductor device 110,200 is as described below.As shown in Figure 7, the IGBT Region Segmentation with semiconductor device 200 becomes unit area and borderline region.In the unit area in IGBT zone with the IGBT unit combination together.The borderline region in IGBT zone is between the unit area in diode area and IGBT zone.Therefore, the IGBT in the semiconductor device 110 locatees adjacent to diode, and the IGBT of semiconductor device 200 locatees away from diode.
Between in unit area and borderline region according to different graphical layout insulated gate groove GT.In the unit area, base layer 32 is divided into body region 32a and float zone 32f by gate trench GT.Body region 32a is connected in the emission electrode E of IGBT, and float zone 32f and emission electrode E disconnect.N
+ Conductive area 37 is formed among the body region 32b and with gate trench GT and contacts.In borderline region, base layer 32 is divided into the zone, each zone corresponds to body region 32a.That is, the zone that is divided in the borderline region is connected in emission electrode E, and N
+ Conductive area 37 is formed in the zone that is divided to contact with gate trench GT.
As can be seen from Figure 7, the spacing Wx between the neighboring gates groove GT in the borderline region is arranged to less than the spacing Wf between the neighboring gates groove GT that float zone 32f is set therebetween in the unit area.In other words, the width in the zone that is divided in the borderline region is arranged to width less than the float zone 32f in the unit area.In addition, the spacing Wx between the adjacent insulated gate electrode groove GT in the borderline region is arranged to equal spacing Wb between the neighboring gates groove GT that body region 32b is set in the unit area therebetween.In other words, the width in the zone that is divided in the borderline region is arranged to equal the width of the body region 32b in the unit area.
The inventor simulates by the semiconductor device 101,102 that semiconductor device 200 is applied to the circuit model M1 shown in Fig. 2.Fig. 8,9,10A describe Simulation result and corresponding with Fig. 3,5B, 6A and 6B respectively with 10B.
Fig. 8 illustrates the temperature of the total current Id and the semiconductor device 200 of the entire semiconductor device 200 of flowing through.In Fig. 8, solid line is represented total current Id, long dotted line represent the to flow through electric current I dd of diode of semiconductor device 200, the electric current I di of the IGBT of semiconductor device 200 and short dash line is represented to flow through.
The hole current density that Fig. 9 is illustrated in the semiconductor device 200 at moment P5 place of Fig. 8 distributes.In Fig. 9, come indicative icon to go out the hole electric current distribution by using isopycnic and arrow.Isopycnic connects the point that current density equates.Arrow has length and the thickness that changes along with current density.
Figure 10 A is illustrated in constantly the IGBT zone of the semiconductor device 200 at P5 place and the electric field strength of the boundary vicinity between the diode area.Figure 10 B illustrates the distribution of the charge carrier amount that produces at boundary vicinity by passing through ionization by collision at moment P5 place.
Below the analog result of semiconductor device 200 and the analog result of semiconductor device 110 are compared.By comparison diagram 3,8 as can be seen, when diode was conducting state, between semiconductor device 110,200, total current Id much at one.Yet electric current I dd reduces to 260 amperes from 306 amperes, and electric current I di is increased to 145 amperes from 100 amperes.In addition, during diode reverse recovery, total overshoot current Id of the entire semiconductor device of flowing through reduces to from negative 147 amperes and bears 126 amperes, and the overshoot current Idi of the IGBT that flows through reduces to negative 107 amperes from negative 121 amperes.
As shown in Figure 9, the overshoot current density distribution in the semiconductor device 200 changes on the borderline region in IGBT zone little by little, continuously.By comparing 5B, 9 as can be seen, the current concentration in the semiconductor device 200 is alleviated, particularly at the place, IGBT unit that approaches diode area.In semiconductor device 200,23300A/cm
2Maximum current density appear at from the body diode of the 2nd IGBT unit of borderline region number.Maximum current density (23300A/cm with semiconductor device 200
2) reduce to the maximum current density (46897A/cm of semiconductor device 110
2) only about half of.
As mentioned above, according to analog result, compare with the semiconductor device 110 shown in Fig. 1, in semiconductor device 200, near the current concentration at the body diode place of the IGBT unit the diode area is alleviated.Therefore, compare, in semiconductor device 200, reduced reverse overshoot current with semiconductor device 110.Especially, in semiconductor device 200, occur on the avalanche current distribution borderline region of gate trench GT below, wherein so that (that is, Wf) narrow spacing (that is, Wx) is arranged gate trench GT than the width of the float zone 32f in the unit area.Therefore, the borderline region in IGBT zone has reduced to be formed at interval raceway groove IGBT in the Semiconductor substrate 31 and the phase mutual interference between the inverse parallel diode, prevents that thus IGBT is destroyed during diode reverse recovery.Therefore, semiconductor device 200 can have little size and the high resistance to puncturing.
Can revise the semiconductor device 200 shown in Fig. 7 in every way.For example, Figure 11 illustrates the semiconductor device 201 according to the modification of semiconductor device 200.Difference between the semiconductor device 200,201 is as described below.
As previously mentioned, in the semiconductor device shown in Fig. 7 200, the spacing Wx between will the adjacent gate trench GT in borderline region is arranged to less than the spacing Wf between the neighboring gates groove GT that float zone 32f is set therebetween in the unit area.In addition, this spacing Wx is arranged to equal spacing Wb between the neighboring gates groove GT that body region 32b is set in the unit area therebetween.In this method, electric field strength almost is distributed on the borderline region coequally so that can be distributed on the borderline region almost evenly at the reverse current that is flowed during the diode reverse recovery.As a result, near the body diode place of the IGBT unit diode area, current concentration is alleviated.
In semiconductor device shown in Figure 11 201, the spacing Wx between will the adjacent gate trench GT in borderline region is arranged to less than the spacing Wf between the neighboring gates groove GT that float zone 32f is set therebetween in the unit area.Yet the spacing Wx in the semiconductor device 200 is well-regulated, and the spacing Wx in the semiconductor device 201 is irregular.Especially, the spacing Wx in the semiconductor device 201 narrows down continuously towards diode area.
In semiconductor device 201, electric field is concentrated below the gate trench GT of borderline region.Because spacing Wx narrows down continuously towards diode area, so the electric field strength in the borderline region dies down towards the unit area continuously from diode area.Therefore, in borderline region, change continuously and be distributed on the borderline region at the reverse current that is flowed during the diode reverse recovery.As a result, near the body diode place of the IGBT unit diode area, current concentration is alleviated.
Figure 12 illustrates the semiconductor device of revising according to the another kind of semiconductor device 200 202.Difference between the semiconductor device 200,202 is as described below.
In the semiconductor device shown in Fig. 7 200, each zone of the base layer 32 of dividing by the gate trench GT in the borderline region is connected in emission electrode E, and N
+Conductive area 37 is formed in each zone that is divided and with gate trench GT and contacts.That is, each zone that is divided of the base layer in the borderline region 32 corresponds to the body region 32b of the base layer 32 in the unit area.Therefore, can think, only utilize body region 32b tectonic boundary zone.
On the contrary, in the semiconductor device shown in Figure 17 202, any one zone that is divided of the base layer 32 in the borderline region is not attached to emission electrode E, and does not form N in the zone that any one is divided
+Conductive area 37.Be the float zone 32f that each zone that is divided of the base layer 32 in the borderline region corresponds to the base layer 32 in the unit area.Therefore, can think, only utilize float zone 32f tectonic boundary zone.
Figure 13 illustrates the semiconductor device 203 according to the modification of the semiconductor device shown in Figure 11 201.Difference between the semiconductor device 201,203 is identical with difference between the semiconductor device 200,202.That is, only utilize the borderline region of body region 32b structure semiconductor device 201, and only utilize the borderline region of float zone 32f structure semiconductor device 203.
In semiconductor device 200,201, owing to only utilize body region 32b tectonic boundary zone, therefore whole borderline region all has contribution to the increase of the current capacity of IGBT.Therefore, compare, can reduce the size of semiconductor device 200,201 with semiconductor device 202,203.Yet, mainly be the effect that is created in distributed current density during the diode reverse recovery by the gate trench GT that in borderline region, arranges with thin space.Therefore,, semiconductor device 202,203 200,201 similar to semiconductor device can be implemented in the effect of distributed current density during the diode reverse recovery.Therefore, in semiconductor device 202,203, near the body diode place of the IGBT unit diode area, current concentration can be alleviated.
Figure 14 illustrates the semiconductor device of revising according to the another kind of the semiconductor device shown in Fig. 7 200 204.Difference between the semiconductor device 200,204 is as described below.Only utilize the borderline region of body region 32b structure semiconductor device 200.On the contrary, utilize the body region 32b of arranged alternate and the borderline region of float zone 32f structure semiconductor device 204.Spacing Wx between the neighboring gates groove GT in the borderline region is arranged to equal spacing Wb between the neighboring gates groove GT that body region 32b is set in the unit area therebetween.That is, in semiconductor device 204, unit area and borderline region all have the alternating structure that is made of body region 32b and float zone 32f.Similar to semiconductor device 200, semiconductor device 204 realized during the diode reverse recovery on borderline region the effect of distributed current density, alleviate near the current concentration at the body diode place of the IGBT the diode area thus.
Figure 15 illustrates the semiconductor device 205 according to a kind of modification of the semiconductor device shown in Figure 14 204.Difference between the semiconductor device 204,205 is as described below.In semiconductor device 204, the spacing Wx between the neighboring gates groove GT in the borderline region is well-regulated.On the contrary, in semiconductor device 205, the spacing Wx between the neighboring gates groove GT in the borderline region is irregular, wherein between the neighboring gates groove GT of float zone 32f in this borderline region.Especially, the spacing Wx in the borderline region narrows down continuously towards diode area.Therefore, the electric field strength in the borderline region dies down towards the unit area continuously from diode area.Thereby the reverse current that is flowed during the diode reverse recovery changes continuously in borderline region and is distributed on the borderline region.As a result, near the body diode place of the IGBT unit diode area, current concentration is alleviated.
Figure 16 illustrates the semiconductor device of revising according to the another kind of the semiconductor device shown in Fig. 7 200 206.Difference between the semiconductor device 200,206 is as described below.
In semiconductor device 200, the degree of depth of the gate trench GT in the unit area is arranged to equal the degree of depth of the gate trench GT in the borderline region.In this method, simplified the manufacturing process of semiconductor device 200 so that can reduce the manufacturing cost of semiconductor device 200.
On the contrary, in semiconductor device 206, the depth d 1 of the insulated gate groove GT1 in the unit area is arranged to depth d 2 greater than the insulated gate groove GT2 in the borderline region.In this method, compare with semiconductor device 200, in semiconductor device 206, can reduce the electric field strength in the borderline region.Therefore, compare, in semiconductor device 206, can reduce the current density in the borderline region during diode reverse recovery with semiconductor device 200.As a result, compare, in semiconductor device 206, can alleviate current concentration with semiconductor device 200.
Can be with the structure applications of semiconductor device 206 in semiconductor device 201-205, so that semiconductor device 201-205 can have the effect identical with semiconductor device 206.That is, the degree of depth of gate trench GT in the unit area of semiconductor device 201-205 can be greater than the degree of depth in borderline region.
(second embodiment)
Below with reference to the semiconductor device 207 of Figure 17 introduction according to second embodiment of the invention.Difference between the semiconductor device 200,207 is as described below.
In semiconductor device 207, in diode area, form insulated trench ZT.This insulated trench ZT have be formed at the IGBT zone in the identical degree of depth and the cross-sectional structure of insulated gate groove GT.Therefore, electric field is concentrated below insulated trench ZT, to such an extent as to compare with semiconductor device 200, in semiconductor device 207, the electric field strength in the diode area increases.As a result, compare with semiconductor device 200, in semiconductor device 207, the reverse current during diode reverse recovery in the diode area increases.Therefore, compare with semiconductor device 200, in semiconductor device 207, the reverse current in the IGBT zone reduces.Therefore, reverse current is distributed on the entire semiconductor device 207, so that compare with semiconductor device 200, in semiconductor device 207, can alleviate the current concentration in the IGBT zone.
Preferably, repeat to arrange insulated trench ZT with as shown in Figure 17 regular spaces.In this method, the electric field strength in the diode area almost equality distributes so that the reverse current in the diode area that almost can distribute equably.As a result, can alleviate current concentration in the diode area.
Can be with the structure applications of semiconductor device 207 in semiconductor device 201-206 so that semiconductor device 201-206 can have the effect identical with semiconductor device 207.That is, can in the diode area of semiconductor device 201-206, form insulated trench.
(the 3rd embodiment)
Below with reference to the semiconductor device 208 of Figure 18 introduction according to third embodiment of the invention.Difference between the semiconductor device 200,208 is as described below.In semiconductor device 208, base layer 32 extends to the diode area from the IGBT zone, and forms insulated gate groove GT3 in diode area.Gate trench GT3 have be formed at the IGBT zone in the identical degree of depth and the cross section of gate trench GT.Can use base layer 32 in the diode area as the anode region of diode.Therefore, can eliminate the special anode region 35 of semiconductor device 200,, can make semiconductor device 208 with low cost so that compare with semiconductor device 200 from semiconductor device 208.
In addition, in semiconductor device 208, the unit area in IGBT zone has the identical alternating structure that is made of body region 32b on first side of Semiconductor substrate 31 and floating struction 32f with diode area.In this method, the design of semiconductor device 208 and manufacturing process have been simplified so that can reduce the manufacturing cost of semiconductor device 208.
Figure 19 illustrates the semiconductor device 209 according to the application example of semiconductor device shown in Figure 180 208.In semiconductor device 209, the gate trench GT3 that is formed in the diode area is connected in parallel with the gate trench GT that is formed on the IGBT zone.In this method, the structure division of the diode area on first side of Semiconductor substrate 31 can be as the part of IGBT.Therefore, this structure division can help the increase of the current capacity of IGBT.
Figure 20 illustrates the semiconductor device 210 according to the Another Application example of semiconductor device 208.In semiconductor device 210, be formed on gate trench GT3 in the diode area be shorted to emission electrode E with the structure division that prevents diode area as IGBT.Therefore, can make structure division be exclusively used in diode so that can simplify the design of diode.
Figure 21 illustrates the semiconductor device 211 according to the modification of semiconductor device 210.Similar to semiconductor device 210, semiconductor device 211 has the diode area that diode is made in special use.Therefore, can simplify the design of diode.Difference between the semiconductor device 210,211 is, does not form N in the diode area of semiconductor device 211
+Conductive area 37.Because having by the body region 32b on first side of Semiconductor substrate 31, unit area and diode area (remove N
+Conductive area 37 is outer) and the identical alternating structure of float zone 32f formation, so can utilize identical wiring figure that gate electrode GT, GT3 are connected.Therefore, can simplify the design of diode more.
Figure 22 illustrates the semiconductor device of revising according to the another kind of semiconductor device 210 212.Similar to semiconductor device 210, semiconductor device 212 has the diode area that diode is made in special use.Therefore, can simplify the design of diode.Difference between the semiconductor device 210,212 is, is formed on the N in the diode area of semiconductor device 211
+ Conductive area 37 is free of attachment to emission electrode E.
Among the semiconductor device 208-211 that illustrates respectively in Figure 18-21, the unit area has the identical alternating structure that is made of body region 32b on first side of Semiconductor substrate 31 and float zone 32f with diode area.Perhaps, similar to semiconductor device 212 shown in Figure 22, the unit area can have different structures with diode area on first side of Semiconductor substrate 31.
Have the structure identical respectively with the semiconductor device 200 shown in Fig. 7 in the IGBT unit area of the semiconductor device 207-212 shown in Figure 17-22.Therefore, similar to semiconductor device 200, semiconductor device 207-212 can make with low cost, reduced in size, and has the high-resistance to puncturing.
As mentioned above, semiconductor device 200-212 according to the embodiment of the invention, the borderline region in IGBT zone reduces the mutual interference mutually that is formed at between the interval raceway groove IGBT in the semi-conductive substrate 31 and the inverse parallel diode, prevents that thus IGBT is destroyed during diode reverse recovery.Therefore, semiconductor device 200-212 can make with low cost, reduced in size, and has the high-resistance to puncturing.
Therefore, semiconductor device 200-212 goes for inverter circuit.For example, the vehicles are provided with the inverter circuit with high voltage and high current capacity and provide power supply to use the DC power supply to equipment (that is engine).Especially, semiconductor device 200-212 goes for being installed on this inverter circuit on the vehicles.
(modification)
Can revise the foregoing description in a different manner.For example, in the diode area of the semiconductor device 201-206 that the structure applications of the diode area of the semiconductor device 207-212 that illustrates respectively among Figure 17-22 can be illustrated respectively in Figure 11-16.In this method, semiconductor device 201-206 can have the effect identical with semiconductor device 207-212.
This change and modification should be considered to be in the scope of the present invention that limits as appended claims.
Claims (17)
1, a kind of semiconductor device comprises:
Has first side and with respect to the first conductive-type semiconductor substrate (31) of second side of this first side;
Transistor area comprises: be formed up to this substrate (31) first side surface portion the second conductivity type base layer (32), be formed up to this base layer (32) a plurality of insulated gate grooves (GT), be formed up to this substrate (31) second side surface portion second conductivity type, first diffusion layer (33) and be formed on emission electrode (E) on first side of this substrate (31); With
Diode area, inverse parallel are connected in this transistor area, and comprise: be formed up to first conductivity type, second diffusion layer (36) of surface portion of second side of this substrate (31), this second diffusion layer (36) has than the high impurity concentration of this substrate (31),
Wherein said diode area comprises and being repeated to arrange and be combined in together forming a plurality of diodes of diode,
Wherein said transistor area comprises unit area and the borderline region between described unit area and described diode area,
Wherein in described unit area, by described a plurality of insulated gate grooves (GT) described base layer (32) is divided into a plurality of body region (32b) and a plurality of float zone (32f), with described body and float zone (32b, 32f) arranged alternate, each body region (32b) is connected to described emission electrode (E), each float zone (32f) disconnects with described emission electrode (E)
Wherein said unit area comprises and is repeated to arrange and be combined in together to form the trench igbt unit, a plurality of interval of trench igbt at interval, each transistor unit has corresponding in corresponding and the described a plurality of float zone (32f) in described a plurality of body region (32b)
Wherein in described borderline region, described base layer (32) is divided into a plurality of zones that are divided by described a plurality of insulated gate grooves (GT), and
Between the adjacent insulated gate groove (GT) in the wherein said borderline region first interval (Wx) is less than second spacing (Wf) between the adjacent insulated gate groove (GT) that is provided with each float zone (32f) therebetween in the described unit area.
2, semiconductor device according to claim 1,
Wherein said first spacing (Wx) equals the 3rd spacing (Wb) between the adjacent insulated gate groove that is provided with each body region (32b) therebetween in the described unit area.
3, semiconductor device according to claim 1,
Wherein said first spacing (Wx) narrows down towards described diode area.
4, semiconductor device according to claim 1,
In a plurality of zones that are divided in the wherein said borderline region each is connected to described emission electrode (E).
5, semiconductor device according to claim 1,
Described a plurality of zones that are divided in the wherein said borderline region comprise a plurality of first zones that are divided and a plurality of second zone that is divided, the described first and second regional arranged alternate that are divided, each first zone that is divided is connected to described emission electrode (E), each second zone that is divided and described emission electrode (E) disconnect, and
First spacing (Wx) between the adjacent insulated gate groove (GT) that is provided with each second zone that is divided therebetween in the wherein said borderline region narrows down towards described diode area.
6, semiconductor device according to claim 1,
The degree of depth (d2) of each the insulated gate groove (GT) in the wherein said borderline region equals the degree of depth (d1) of each the insulated gate groove (GT) in the described unit area.
7, semiconductor device according to claim 1,
The degree of depth (d2) of each the insulated gate groove (GT2) in the wherein said borderline region is less than the degree of depth (d1) of each the insulated gate groove (GT) in the described unit area.
8, semiconductor device according to claim 1,
Wherein said diode area comprises that at least one has the degree of depth identical with each insulated gate groove (GT) in the described unit area and the insulated trench (ZT) of cross-sectional structure.
9, semiconductor device according to claim 8,
Wherein at least one insulated trench (ZT) comprises a plurality of insulated trenchs (ZT) that are repeated to arrange.
10, semiconductor device according to claim 1,
Wherein said base layer (32) extends to the described diode area from described transistor area, and
Wherein said diode area comprises a plurality of insulated gate grooves (GT3), each have with described unit area in the identical degree of depth and the cross-sectional structure of each insulated gate groove (GT).
11, semiconductor device according to claim 10,
Wherein said diode area has the identical cross-sectional structure in described unit area on first side with described Semiconductor substrate (31).
12, semiconductor device according to claim 10,
Described a plurality of insulated gate grooves (GT) in described a plurality of insulated gate grooves (GT3) in the wherein said diode area and the described transistor area are connected in parallel.
13, semiconductor device according to claim 10,
Described a plurality of insulated gate grooves (GT3) in the wherein said diode area are shorted to the emission electrode (E) of described transistor area.
14, semiconductor device according to claim 10,
Wherein said transistor area comprises a plurality of first conductivity type emitter regions (37), and each emitter region (37) is formed in the corresponding body region (32b), and
Wherein said diode area has the identical cross-sectional structure in described unit area on first side with described Semiconductor substrate (31) except that described a plurality of first conductivity type emitter regions (37).
15, semiconductor device according to claim 10,
Wherein said diode area comprises the first conductivity type emitter region (37), and this emitter region (37) is formed in the described base layer (32) and adjacent in the described a plurality of insulated gate grooves (GT3) in the described diode area at least one, and
Wherein said base layer (32) is connected to described emission electrode (E) so that described emitter region (37) disconnects with described emission electrode (E).
16, semiconductor device according to claim 1,
Wherein said semiconductor device is used for inverter circuit.
17, according to any described semiconductor device among the claim 1-16,
Wherein said semiconductor device is used for being installed in the equipment on the vehicles.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP157923/2007 | 2007-06-14 | ||
| JP2007157923 | 2007-06-14 | ||
| JP2008128775A JP4605251B2 (en) | 2007-06-14 | 2008-05-15 | Semiconductor device |
| JP128775/2008 | 2008-05-15 |
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| CN101325198A true CN101325198A (en) | 2008-12-17 |
| CN101325198B CN101325198B (en) | 2010-06-30 |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP4605251B2 (en) | 2011-01-05 |
| JP2009021557A (en) | 2009-01-29 |
| CN101325198B (en) | 2010-06-30 |
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