CN101316160A - Multi-Node Simultaneous Sampling and Data Transfer Method - Google Patents

Abstract

Multi-node synchronous sampling control and data transmission method, its steps are as follows: (1) Construct a global synchronization device matching with the upper layer data processing equipment and the process quantity acquisition control device (DAE), the device utilizes an external synchronization source or a local timer Generate a global synchronization signal S1; (2) connect the global synchronization signal to one or more devices called communication devices (DCE), and the communication device generates a synchronization signal S2 for each connected process quantity acquisition control device; (3) Using the absolute time scale and the global sampling counter in the signal S1, the secondary synchronous sampling of the process quantity is realized among multiple communication devices; (4) The acquisition and control device (DAE) responsible for the process quantity acquisition and execution output is in the After receiving the signal S2, the synchronous signal and command data are detected; (5) The acquisition control device dynamically adjusts the starting time of the S2 signal according to Δt _i to realize synchronous sampling of long-distance multi-nodes.

Description

Multi-Node Simultaneous Sampling and Data Transfer Method

1. Technical field

The invention relates to a method for synchronous sampling and real-time data transmission among multiple data acquisition nodes distributed in different places. Especially in the field of power system protection and industrial control where distributed acquisition control and centralized data processing are required, data sampling requires strict synchronization, sampling data requires real-time transmission, and time delay is fixed. Specifically, the present invention is a multi-node synchronous data acquisition and real-time transmission method.

2. Background technology

In the field of power system relay protection and industrial process control, in order to accurately retain the phase information of the signal, or to conduct accurate timing analysis on asynchronous events, it is necessary to collect a certain group of process variables at different locations synchronously and at equal intervals, in order to improve the system Real-time processing capability and asynchronous event response speed require that the sampling data of each process quantity acquisition and control device can be uploaded in real time, and the command setting information of the processing device needs to be sent to the actuator or adjustment mechanism in real time. Some standards such as IEC61850-5 define three levels of sampling value synchronization accuracy: T3, T4 and T5. Among them: T3 level requires 25 μs, which is used for distribution line protection; T4 level requires 4 μs, which is used for transmission line protection; T5 level requires 1 μs, which is used for metering [5]. The equal interval sampling is the basis of the quasi-synchronous sampling algorithm in the subsequent stage [4]. When the measured process quantities can be connected to the same acquisition device, synchronous acquisition is relatively easy to achieve, but when these process quantities are located in different acquisition devices, and these acquisition devices When the devices are not physically distributed together, there is no unified implementation method.

At present, the existing synchronous sampling control methods mainly include the following three methods:

1. Following the IEC61850-9-1 architecture, multiple combiners are synchronized by an accurate clock source, and then the combiner generates a start signal to control the ADC to achieve multi-node sampling [3].

2. The synchronous sampling system based on the IEEE1588 precision time protocol PTP (Precision Time Protocol), through the microsecond-level synchronization of the clock of the terminal equipment using the multicast technology for the distributed control system that satisfies the multipoint communication, and then realizes the sampling synchronization according to the absolute time .

3. GPS synchronization method. The GPS module is used to provide the second pulse for different physical distribution nodes, and the sampling of each node is synchronized with the second pulse output by the GPS module to realize global synchronous sampling.

The disadvantages of the existing synchronous sampling control methods:

1. The IEC61850-9-1 architecture requires an independent synchronization channel, and the second pulse synchronous combiner is generally used. This architecture does not consider the impact of the length of the transmission link, and the direction of data transmission is unidirectional. When master-slave nodes are required Not applicable when exchanging information, and requires high synchronization clock source and local clock.

Let the period of the synchronous clock source be T, and the sampling period of the actual ADC be Ta. In order to realize equal interval sampling, there should be

T=N×T _a where: N is the number of sampling points in period T

f ₀ =1/T=(1/NT _a )=f _a /N where: f _a =1/T _a is the working clock of the local node

Since f ₀ , f _a , and N are integers, the higher the sampling rate N, the more precisely the above formula cannot be equal. Due to the difference in f _a and frequency drift between different nodes, it is actually impossible to achieve synchronous equal interval sampling.

2. The synchronous sampling method based on IEEE1588 requires a network hardware interface and switching equipment supporting the IEEE1588 protocol, which increases additional costs. Moreover, because IEEE802.3 has requirements on Ethernet transmission distance and network transmission delay, it is not suitable for synchronous acquisition and control among multiple nodes that are physically distributed far away. IEEE1588 starts a synchronization process every second. After the clock synchronization fails, re-synchronization needs to repeatedly calculate the relative error Δt of the clocks on both sides, and the synchronization delay is long.

In addition, when the high-speed multi-node acquisition and control device is connected to the same master control node, network conflicts will intensify during heavy loads, affecting real-time data transmission, and it cannot be guaranteed that each sampled data will be transmitted to the data processing terminal under a fixed delay.

3. The GPS synchronization method is affected by the number of satellites captured by GPS, as well as the natural environment and social environment and other factors, and requires corresponding hardware support, additional data transmission channels, and high cost. references:

1. Gao Houlei, Jiang Shifang, He Jiali. Several Sampling Synchronization Methods in Digital Current Differential Protection. Electric Power System Automation, 1996, 20(9).

2. Yang Weina, Bao Weilian. Signal processing of relay protection data transmitted by PCM system. Power system communication, 1992(2)

3. Yin Zhiliang, Liu Wanshun, Yang Qixun, Qin Yingli, A New Method for Synchronization of Merging Units Complying with IEC61850 Standard. Electric Power System Automation. 2004, 28(11).-57-61

4. Dai Xianzhong's quasi-synchronous sampling and its application in non-sinusoidal power measurement, Journal of Instrumentation, November 1984

5.IEC 61850-5.Communication Networks and Systems in Substations, Part 5: Communication Requirements for Functions and Device Models.2003.

6. Yin Zhiliang, Liu Wanshun, Yang Qixun, Qin Yingli. Based on IEEE 1588, realize the new technology of power system automation of substation process bus sampling value synchronization. 2005, 29(13).-60-63

3. Contents of the invention

The purpose of the invention is to propose a method that realizes synchronous sampling control and real-time data transmission on the same pair of full-duplex links, and solves the problem of physical link length and software protocol stack between multiple acquisition control nodes in different physical distributions. the resulting additional delay.

The present invention is realized through such scheme: multi-node synchronous sampling and data transmission method:

(1). Build a global synchronization device (hereinafter referred to as GSE) that matches the upper layer data processing equipment and process quantity acquisition control device. This device can use an external synchronization source or a local timer to generate a global synchronization signal S1, Its period is the sampling period of the process quantity acquisition control device, and the absolute time scale and the global sampling counter are included in the signal through encoding.

(2). Connect the global synchronization signal to one or more (determined by the system scale) devices called communication devices (hereinafter referred to as DCE), which generate a synchronization signal for each connected process layer acquisition control device S2, the period of S2 is exactly the period of the global synchronous signal S1, but the start moment of the signal is related to the link between it and the corresponding acquisition device, that is, it is delayed by Δt _i (i is the acquisition device number, i=1, 2 ,...n). By encoding the signal S2, it carries the control information and synchronization signal sent by the upper layer data processing equipment to the corresponding acquisition control device.

(3). Using the absolute time scale and the global sampling counter in the signal S1, the secondary synchronous sampling of the process quantity is realized among multiple communication devices.

(4). The acquisition control device (hereinafter referred to as DAE), which is responsible for process quantity acquisition and execution output, detects the synchronization signal and command data after receiving the signal S2, and immediately starts the acquisition of the local process quantity and returns it under the control of the synchronization signal The signal S3 to DCE, that is, S3 and S2 are strictly clock-related. By encoding the signal S3, it can carry the sampling data of the previous moment and the application data sent to the upper layer data processing equipment.

(5). Calculate the communication device to the acquisition control device DAE _i (i=1, 2, 3...) according to formula 3-1, formula 3-2 and formula 3-3 when the global signal arrives each time The channel delay amount Δt _i (set the link transmission delay as t _delay and consider the physical link for sending and receiving data to be equal in length), dynamically adjust the start time of the S2 signal according to Δt _i to realize synchronous sampling of long-distance multi-nodes.

t _delay ＝(t _rcv -t _se -T _FH )/2 (Formula 3-1)

Δt=T _dm -(t _rcv -t _se -T _FH )/2=T _dm -t _delay (Formula 3-2)

T _dm ＝max{t _delay0 ，t _delay1 ，...，t _delayn } (Formula 3-3)

In the formula: Δt--channel delay

T _FH -- synchronization frame header width

T _dm -- the maximum link transmission delay of the system, which can be estimated according to the maximum link length

t _se -- the time when a specific channel sends the synchronous waveform, t _rcv -- the time when the returned data is received

Since the sampling data is transmitted back under the control of the sampling synchronization signal, the time delay and transmission bandwidth of the real-time sampling data are stable, and the control command and synchronization signal are carried in the signal through encoding to realize the sampling synchronization on the same pair of links and data transfer.

The data frame sent by the acquisition control device to the communication device according to the present invention is composed of a sampling data field and a user protocol field. The sampling field transmits the last sampling data each time, and the protocol field transmits high-level protocol data units, forming two logical channels. The sampling data is transmitted in real time, and the protocol data is transmitted in non-real time. The same data frame is transmitted twice in a sampling interval, and the link layer controller determines to select one of them according to the frame check code, which simplifies the transmission mechanism and improves the channel error correction capability.

The method of multi-node synchronous sampling control and data transmission is suitable for the power system protection field and industrial control where the collection and control devices need to be arranged in different places, the global data sampling needs to be strictly synchronized, and the time delay of sampling data transmission is fixed, distributed collection, real-time centralized data processing field.

Features of the invention

(1). Using a pair of data links to realize data transmission and synchronous sampling, with low cost and good reliability.

(2). The data transmission is completed in each sampling period, and the time is fixed. There is no need to insert a time stamp, and the sampling data can be directly transmitted, which is convenient for high-level software to perform in-depth analysis.

(3). Automatically calculate the transmission delay of multiple channels and adjust the synchronization signal of each channel to ensure accurate synchronization between multiple nodes.

(4). The sampling data is transmitted twice to improve the channel error correction capability and reduce the overhead of high-level request retransmission

(5). The data field is divided into a real-time data field and a protocol data field to ensure real-time data transmission while providing a logical channel to transmit high-level protocol data.

(6). The synchronization accuracy is not affected by the physical length of the channel, nor is it affected by external conditions, and can reach the nanosecond level.

(7).Using illegal codes to generate synchronization signals, the synchronization point of the sender is the leading edge of the signal, and the synchronization point of the receiver is the trailing edge of the signal to ensure accurate detection of the synchronization signal.

(8). The channel delay algorithm and transmission and error control rules of the present invention are simple and effective, suitable for design and implementation based on FPGA, and improve system performance through parallel processing.

Description of drawings

Figure 1 Multi-node synchronous sampling control system structure diagram

Figure 2 Synchronization signal S1 of the global synchronization device

Figure 3 Communication device synchronization/command signal S2 (S3)

Figure 4 The working sequence diagram of the multi-node synchronous sampling system

Detailed ways

1. Multi-node synchronization system composition

A typical multi-node synchronous sampling and data transmission system is shown in Figure 1:

The system has a three-layer structure from bottom to top. Level 1 is the acquisition control device, which is responsible for process quantity acquisition and control command execution. The process quantity to be measured and the execution/regulation mechanism are connected to the acquisition control device. DAE starts data sampling after receiving the synchronization/command (Syn/Cmd) signal, executes the corresponding command and forwards the sampled data. Level 2 includes a global synchronization device (hereinafter referred to as GSE) and a communication device (hereinafter referred to as DCE), in which the synchronization device is responsible for generating global synchronization signals according to the sampling interval required by the upper layer, and the communication device is responsible for synchronizing each acquisition control device and transparently forwarding data from the upper or lower layer Level 3 is a data processing device (hereinafter referred to as DPE), which is responsible for real-time data processing and issuing control commands. This invention only involves Level 1 and Level 2 in the system.

S ₀ in Fig. 1 is the external synchronous signal, can access the remote synchronous signal through S ₀ , expand the scale of the system, and realize synchronous sampling of multiple systems. S ₁ is the sampling/time scale signal. The synchronization device generates a process quantity sampling start signal that meets the requirements of the upper equipment. The signal also includes the global absolute time scale and sampling counter. S ₂ is the synchronization/command signal sent by the communication device to the acquisition control device, which includes the process quantity sampling start signal and the protocol data unit sent by the upper layer equipment to the acquisition device. S ₃ is the sampling data and protocol data unit sent by the acquisition control device to the communication device, and the signal includes a synchronization pulse. The scale of the local synchronization system can be expanded by expanding the equipment in the dotted box in Figure 1 .

The present invention adopts fixed-length frames, and the transmission delay is fixed. The signal waveforms used for data transmission and synchronous control are formed by synchronous headers and subsequent data fields, and are additionally used for error control frame check codes.

2. Global synchronization signal S ₁

The timing and encoding of the physical layer of the synchronization signal S ₁ output by the synchronization device in Figure 1 is shown in Figure 2. The encoding uses a high level width to represent information, and the width of each symbol is T _b . T _h in the figure is the width of the frame synchronization header, followed by the data segment immediately after the synchronization header, T ₀ is the width of the symbol logic 0, T ₁ is the width of the symbol logic 1, and Ts is the sampling interval. T _b , T ₀ and T ₁ are all functions of T _b . Synchronization device sends synchronous signal with interval Ts, and t _fs is frame starting point, and the receiving side detects two widths continuously and is T _h high level and thinks that frame synchronous signal is detected, and t _syn is the synchronous detection point of the receiving side in the mark figure, There is a symbol-width low level before the frame sync header to ensure sync detection. In the data field of the signal S ₁ , an absolute time scale and an 8-bit sampling counter are included. When the system is connected with multiple communication devices, the global sampling counter is used to mark the sampling data at a specific time, and the second sampling can be performed according to the needs of the data processing device.

3. Synchronous sampling/data transmission signal S ₂ /S ₃

As shown in Figure 2, the frame format of the downlink signal _S2 of the communication device and the uplink signal _S3 of the acquisition device in the present invention are the same, and the timing and encoding of the physical layer are shown in Figure 3. In a sampling interval, the data is continuously transmitted twice. In the figure, t _fs0 is the starting point of the frame of the sender, and t _syn is the detection point of the synchronous signal of the receiver. It starts with two consecutive high-level marker frames with a width of T _synh , followed by a high level mark with a width of T _synh will retransmit the data, and t _fsl is the starting moment of the second transmission. In the figure, t ₀ is the synchronization time, t ₁ is the start time of data retransmission, t ₂ is the start of the next sampling interval, and Ts is a complete sampling interval. The data field of each frame starts after a leading 1, t _dat represents the start time of the data field, T _{spae is} the time width between the marker signal and the leading 1, and T _b is a data bit width. The data field encoding adopts Manchester encoding, so that it can be connected with the differential transceiver.

Since the frame control signal in S ₂ /S ₃ of the present invention does not use Manchester coding, and the width is much larger than the data bit width, the receiver can recover the synchronous signal by means of pulse width detection.

4. Error control and protocol data transmission

As shown in Figure 3, in the present invention, the data field of signal S ₂ /S ₃ (starting from t _dat in Figure 3) is divided into the following three parts, sampling data, protocol data and frame check part, as shown in Table 1 shown.

Table 1 Data link layer frame format of signal S2/S3

Sampling data User Agreement Data frame check (CRC)

The sampling data field of the present invention should be assembled by SGDMA (scatter gather DMA), or be filled by the lowest layer of the protocol stack when starting transmission. Utilizing the user protocol data field can constitute a non-real-time logical channel for transmitting DAE and peer Monitoring information between the upper layers. As shown in Table 2, a protocol data transmission may include multiple sampling intervals.

In the present invention, the bit width ratio of sampling data and protocol data is determined by the application, and the frame check is 16-bit CRC. A complete frame of protocol data may be from protocol data 0 to protocol data n-1 shown in Table 2. A combination of groups, depending on the specific application.

Table 2 Composition of protocol data S2/S3

Since the data collected in real time must be delivered at each sampling interval, the error request retransmission mechanism cannot be used during high-speed sampling, and the error on the serial link can be corrected through the subsequent frame if it is not a scalable error. In the present invention, the same frame of data is transmitted twice at the link layer, and the receiving side selects the correct group according to the frame verification, and if both groups are wrong, it is submitted to the upper layer for determination.

5. Working principle of multi-node synchronous sampling system

The physical layer signal interaction and timing information of the complete system work is shown in Figure 4. Taking two acquisition control devices as an example in Figure 4, the working signal timing between the global synchronization device GSE and the two acquisition control devices and communication devices is given.

In Figure 4, T _s is the sampling period, the waveform Wav0 is the synchronization signal from GSE to DCE, Wav00 is the synchronization/command waveform from the communication device DCE to the acquisition control device DAE0, Wav01 is the synchronization waveform received by DAE0 after transmission delay, and Wav02 is the reception by DCE to the sampled data waveform from DAE0. Wav10 is the synchronization/command waveform from the communication device DCE to the acquisition control device DAE1, Wav11 is the synchronization waveform received by the DAE0 side after transmission delay, and Wav12 is the sampling data waveform received by the DCE side from DAE1. Similarly, if one DCE is connected to multiple acquisition and control devices, the data waveform and transmission process on the physical link are similar to DAE0 and DAE1, and will not be analyzed any more.

6. Realization of channel delay and synchronous sampling

In Fig. 4, at time t ₀ , the synchronization device GSE sends out a sampling synchronization signal S ₁ with a time scale, and the communication device calculates the delays between the synchronization signals to DAE0 and DAE1 and S ₁ based on the link delay determined at the previous time as Δt ₀ and Δt ₁ , and generate their respective synchronization/command signals S ₂ at time t ₁ and t ₂ , see waveforms Wav01 and Wav11. After communication link delay, DAE0 and DAE1 generate local process quantity acquisition start signal at time t ₅ , and send back at the same time For the data at the last sampling moment, see waveforms Wav02 and Wav12. The channel delay is calculated once per sampling interval, and the calculation method is as follows:

As shown in Figure 6 above, the delay amount Δt _i of channel i can be calculated according to formula 3-1, formula 3-2 and formula 3-3, and the acquisition control device connected to channel i, the synchronization command frame at time t _fsi = t ₀ +Δt _i (i=0, 1, 2, ...) is sent out, the data sampling time of acquisition control device i is set to t _iADC , t _delayi is the link transmission delay of channel i, T _FH is the frame header Width, combined Equation 3-1 and Equation 3-2 have:

t _iADC ＝t ₀ +Δt _i +t _delayi +T _FH ＝t ₀ +T _dm +T _FH ＝t ₅ (Formula 3-4)

The result of Equation 3-4 is a constant, so if channel i is selected according to the method above and channel delay is selected, it can ensure that all acquisition control devices start data sampling at the same time t _iADC (=t ₀ +T _dm +T _FH ).

7. Channel error and data integrity monitoring

The data field of the signal S2/S3 between the acquisition device and the communication device of the present invention adopts Manchester encoding, and the decoding part can monitor the signal integrity of each bit, and simultaneously monitor the integrity of the data frame to provide frame fragment detection. Monitor the working condition of the channel by monitoring the data flow on the receiving channel, and send a channel locking signal to the high-level software, so as to adopt different algorithms or control strategies according to the working condition of the channel.

Claims (6)

1, multi-node synchronous sampling control and data transmission method, it is characterized in that the steps are as follows: (1). Build a global synchronization device that matches the upper layer data processing equipment and the process quantity acquisition control device (DAE). This device uses an external synchronization source or a local timer to generate a global synchronization signal S1, and its period is the process quantity acquisition The sampling interval of the control device is encoded so that S1 carries absolute time scale and global sampling counter information; (2). Connect the global synchronization signal to one or more devices called communication devices (DCE), and the communication device generates a synchronization signal S2 for each connected process quantity acquisition and control device, and the cycle of S2 is synchronized with the global The period of the signal S1 is the same, but the starting moment of S2 is related to the link between it and the corresponding acquisition device, that is, it is delayed by Δt _i from S1, i is the number of the acquisition device, i=1, 2,...n; through Coding the signal S2 makes S2 carry the upper layer data processing equipment and send it to the corresponding acquisition control device to control command data information and synchronization signals; (3). Using the absolute time scale and the global sampling counter in the signal S1, the secondary synchronous sampling of the process quantity is realized between multiple communication devices; (4). The acquisition and control device (DAE), which is responsible for process quantity acquisition and execution output, detects the synchronization signal and command data after receiving the signal S2, and immediately starts the acquisition of the local process quantity and returns the data signal under the control of the synchronization signal From S3 to DCE, S3 is encoded to carry the sampling data of the last sampling interval and the application data sent to the upper layer data processing equipment; (5). Recalculate the channel delay Δt i from the communication device to the acquisition control device DAE _i each time the global signal arrives _at the communication device, i=1, 2, 3..., and dynamically adjust S2 according to Δt _i The start-up moment of the signal realizes the synchronous sampling of long-distance multi-nodes. 2. The multi-node synchronous sampling control and data transmission method according to claim 1 is characterized in that: the global synchronous signal S ₁ uses a high level width to represent encoded information, and each symbol width is T _b , which is formed by a width of The leading 0 of Tb and two pulses with continuous high-level width Th constitute the frame synchronization header, followed by an additional data field, the high-level width of logic 0 is T ₀ , the high-level width of logic 1 is T ₁ , T _h , T ₀ and T ₁ are all functions of T _b ; the synchronization device sends a synchronization signal at an interval of Ts, and the receiver detects two consecutive high levels with a width of T _h , which is considered to have detected a frame synchronization signal, and the next high level The falling edge of the pulse whose width is T _h is marked as the synchronous detection point of the receiver; 3. The multi-node synchronous sampling control and data transmission method according to claim 1, characterized in that: the synchronous signal _S2 and the data signal _S3 have the same frame format, consisting of a leading 0 with a width of Tp and two consecutive high A pulse with a level width of T _synh constitutes a frame synchronization head, and the falling edge of a pulse with a width of T _synh after marking is the synchronous detection point of the receiver. 4. The multi-node synchronous sampling control and data transmission method according to claim 1, characterized in that: the data frame sent from the collection control device to the communication device is composed of a sampling data field and a user protocol field, and the sampling data field is transmitted every time For the last sampling data, the user protocol field transmits the upper-layer protocol data unit, which constitutes two logical channels. The sampling data is transmitted in real time, and the protocol data is transmitted in non-real time. 5. The multi-node synchronous sampling control and data transmission method according to claim 3, characterized in that: in the information frame exchanged between the communication device and the collection control device, the same datagram is transmitted twice in a sampling interval, and is determined by Two consecutive high levels with a width of T _synh mark the start of the frame, a low level of T _space and a leading 1 and subsequent data fields constitute the first data packet; a high level mark with a width of T _synh will then To retransmit the data, the link layer controller determines to select one of the data packets according to the frame check code, which simplifies the transmission mechanism and improves the channel error correction capability. 6. The method for multi-node synchronous sampling control and data transmission according to claim 1, characterized in that: the communication device DCE calculates the data sent to the acquisition control device DAE _i according to the link delay determined by the global synchronization signal S1 and the last sampling interval The delay between the synchronization signal and S ₁ is Δt _i , and the synchronization/command signal S ₂ is issued at the time t _fsi =t ₀ +Δt _i (i=0, 1, 2,....). Delayed through the communication link , DAE _i generates a local process quantity sampling start signal at time t _iADC , and at the same time sends back the data at the previous sampling time. The calculation method of the delay Δt _i is as follows: t _delay ＝(t _rcv -t _se -T _FH )/2 Δt=T _dm -(t _rcv -t _se -T _FH )/2=T _dm -t _delay T _dm = max{t _delay0 , t _delay1 , . . . , t _delayn } t _iADC =t ₀ +Δt _i +t _delayi +T _FH =t ₀ +T _dm +T _FH =constant In the formula: Δt--channel delay T _FH --Synchronous frame header width, T _FH ＝t ₃ -t ₁ ＝t ₄ -t ₂ ＝.... T _dm -- the maximum link transmission delay of the system, which can be estimated according to the maximum link length t _se -- the time when a specific channel sends the synchronous waveform, t _rcv -- the time when the returned data is received t _delay -- link transmission delay, the physical link for sending and receiving data is set to be equal in length.

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