CN103905137B - Lock-out pulse jitter suppression method based on FPGA and system - Google Patents

Abstract

The invention discloses a kind of lock-out pulse jitter suppression method based on FPGA and system, by first recording external pulse due in, and it is buffered in Block RAM on FPGA sheet, then prediction next synchronous pulse due in, and trigger generation local synchronization pulse according to this, it is achieved jitter elimination, shortening pull-in time and high jitter suppression can be met simultaneously, improve jitter performance and the stability of regeneration lock-out pulse, it is adaptable to centering low frequency synchronisation signal processes, and the occasion that requirement of real-time is higher.

Description

Lock-out pulse jitter suppression method based on FPGA and system

Technical field

The present invention relates to a kind of lock-out pulse jitter suppression method based on FPGA and system, belong to In data acquisition, communication and technical field of measurement and test.

Background technology

At present, time-sharing multiplex digital communication network extremely relies on synchronizing signal, if local recovery is same There is bigger shake, in some cases it is possible to cause the deterioration of equipment performance to cause in step signal Data sampling is made mistakes, and communications errors occurs.In cascaded communication system, synchronization jitter can make Signal after regeneration produces a position modulation, and it not only makes regeneration decision instant signal-to-noise ratio degradation, But also in the signal reflected after regeneration, pass to next repeater, shake is past along relaying chain Lower accumulation, thus limit communication distance, the existence of timing jitter so that receiver synchronizes system System can not be accurately tracked by and capture the timing information receiving signal.So, in order to reduce system The bit error rate, be necessary for using various effective way to suppress the generation of timing jitter.

In Industry Control and field of electric power automation, for the thing of the various asynchronous generation of synchronous recording Part or semaphore, need the data acquisition unit of different physical distribution is carried out synchro measure, and The shake of lock-out pulse can cause accurate measurement error to increase, and synchro measure loses reference significance. Even if additionally, reference synchronization source sends synchronization frame to by synchronizer at equal intervals, because crystal is old Change and the reason such as shake and link transmission also can introduce randomized jitter, still need to by synchronizer side Take measures to eliminate shake.

The multiple method that the problem brought for solving above-mentioned synchronization jitter has occurred, mainly shows As follows:

1) pulses generation and the stability of transmission circuit are improved, in order to reduce pulse width and cycle Change, the pulse generating circuit of source must use high stability crystal, wants to produce tool simultaneously There is the pulse train relatively stablizing bandwidth and cycle, ensure that lock-out pulse is from source to destination end simultaneously Transmission jitter；

2) by VCO and the method for software calibration, with the voltage-controlled crystal (oscillator) (VCO) of high stable for this locality Frequency source, by measuring the cycle of external sync pulse, carries out Kalman filtering by circular error After be converted to the input value of DAC, adjust the output frequency of local crystal oscillator, thus obtain one The all good frequency marking of long-term and short-term stability, is used as the frequency in rear class sync pulse regeneration loop Rate produces local synchronization pulse；

3) digital phase-locked loop, utilizes the phase between phase detectors detection input pulse and output pulse Potential difference also carries out accumulation peace by loop filter and slides into and control numerical control and vibrate phase contrast Device realizes jitter elimination.

Although the suppressing method of above-mentioned synchronization jitter, can effectively eliminate in external synchronization signal A part of delay variation, but be respectively arranged with shortcoming, method 1) sender when must use high stable Base, ensures the low jitter of transmitting procedure simultaneously, and difficulty is bigger；Method 2) need VCO and The complicated circuits such as DAC, relatively costly and include that matrix inversion is transported based on Kalman filtering algorithm Calculating and matrix connects the iterative process such as multiplication, computing is complex, it is difficult in FPGA platform Realize；Method 3) use phaselocked loop scheme in otherwise use simple monocycle scheme, cause Cannot realize arriving between short pull-in time and narrower loop bandwidth optimum simultaneously, or make The dicyclo using complexity adds the scheme of VCXO makes whole cost and complexity rise under reliability Fall, and, all phaselocked loops the most all introduce negative feedback loop, when causing loop-locking Between elongated, affect real-time.

Therefore, a kind of method finding effective anti-synchronization jitter, is asking of current urgent need solution Topic.

Summary of the invention

In order to overcome the deficiency and defect that prior art exists, the present invention provide based on FPGA Lock-out pulse jitter suppression method and system, by first recording external pulse due in, and It is buffered in Block RAM on FPGA sheet, then prediction next synchronous pulse due in, and Trigger this new earth pulse according to this, it is achieved jitter elimination, meet simultaneously and shorten pull-in time and height Jitter suppression, has a good application prospect.

The present invention is achieved by the steps of:

Step (1), detects the rising edge of outer lock-out pulse by marginal detector, and upper Rise along the value recording current free-running operation intervalometer when arriving, this value is stabbed t as current time_n, BlockRAM on the sheet of write FPGA；

Step (2), after external synchronization signal rising edge, the timestamp that will record in BlockRAM Take out tectonic sequence { t_n}；

Step (3), chooses { t_nT₀、t₁、t₂、…、t_nN+1 observation data, structure altogether Make difference sequence { Δ t_nSo that Δ t_n=t_n-t_n-1, utilize { Δ t_nAverage estimate input synchronize The interval of pulse

Step (4), chooses sequence { t_nT₁、t₂、…、t_nN observation data construct base altogether Quasi-sequence { t_{s_n}So that t_{s_1}=t₁=t_{m_1}+ε₁、Wherein, t_{m_1}For corresponding t₁Lock-out pulse reference instant time outside, ε₁…ε_nFor t_{s_1}…t_{s_n}Relative to t_{m_1}With Machine is shaken, and with { t_{s_n}Estimation of Mean go out the reference instant of main equipment lock-out pulse

Step (5), builds Linear Estimation equationAccording to the most estimated synchronization Pulse spacingWith outer lock-out pulse reference instantPredict new lock-out pulse due in

Step (6), willDeduct and write the output of output comparator after needing side-play amount and deposit Device；

Step (7), intervalometer and the output of output comparator constantly relatively local free-running operation are posted The value of storage, once the two is consistent, triggers sync pulse regenerator broadening output local synchronization arteries and veins Punching.

Aforesaid lock-out pulse jitter suppression method based on FPGA, it is characterised in that: step (3) Choose { t_nT₀、t₁、t₂、…、t_nN+1 observation data, build difference sequence { Δ t altogether_n, And utilize formula (1) to estimate the interval of incoming sync pulse

${\hat{T}}_s=\frac{1}{n}\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\mathrm{\Δ}{t}_i=\frac{1}{n}[(t_1-t_0)+(t_2-t_1)+...+(t_n-t_{n-1})]=\frac{(t_n-t_0)}{n}---\left(1\right).$

Aforesaid lock-out pulse jitter suppression method based on FPGA, it is characterised in that: step (4) according to sequence { t_{s_n}Average, utilize formula (2) estimation main equipment lock-out pulse send out The raw moment

Run the system of above-mentioned lock-out pulse jitter suppression method based on FPGA, its feature Be: be included in fpga chip build with lower component,

Marginal detector, is used for detecting the rising edge triggered time stamp record simultaneously of outer lock-out pulse；

Timestamp record and parameter calculator, be used for recording outer lock-out pulse due in and estimating The interval of outer lock-out pulseReference instant with outer lock-out pulse

BlockRAM, is positioned at RAM resource on FPGA sheet, is used for storing time stamp data；

Local free-running operation intervalometer, is used for producing timestamp and participating in output triggering pulse shaping；

Synchronize predictor, by the interval of the incoming sync pulse estimatedWith main equipment lock-out pulse There is the momentPredict new lock-out pulse due inAnd carry out phase shift as required；

Output comparator, by constantly comparingWith local free-running operation intervalometer, when the two Time consistent, output synchronizes to trigger pulse；

Sync pulse regenerator, broadening output local synchronization pulse under the triggering of output comparator；

The input input outer synchronous signal of described marginal detector, the output of marginal detector End is connected with timestamp record and parameter calculator, described timestamp record and parameter calculator Be connected with BlockRAM, local free-running operation intervalometer respectively, described timestamp record and The parameter output of parameter calculator is connected with synchronization predictor, output comparator and synchronization in turn Impulse regenerator, described local free-running operation intervalometer is also connected with output comparator, described The output local synchronization pulse of sync pulse regenerator broadening.

The invention has the beneficial effects as follows:

1. simple in construction, does not has feedback circuit；

2. jitter suppression algorithm is realized by pure hardware, fast to the disturbance response time；

Have estimated the local clock drift relative to reference clock and the impact of deviation the most simultaneously；

4. tracking velocity is fast, both can synchronize after incoming sync pulse quantity exceedes data window Locking；

5. utilizing open loop dynamic prediction method, system is the most all stable；

6. the lock-out pulse shake the least (< 10ns) of regeneration.

Accompanying drawing explanation

Fig. 1 is that lock-out pulse arrives the oscillogram synchronizing three kinds of situations that recipient occurs.

Fig. 2 is the flow chart of the lock-out pulse jitter suppression method based on FPGA of the present invention.

Fig. 3 is the system block diagram of the lock-out pulse jitter suppression system based on FPGA of the present invention.

Detailed description of the invention

Below in conjunction with Figure of description, the invention will be further described.Following example are only For technical scheme is clearly described, and can not limit the present invention's with this Protection domain.

As it is shown on figure 3, the lock-out pulse jitter suppression system of the present invention, all of FPGA Resources on Chip build, including marginal detector, timestamp record and parameter calculator, synchronization Along predictor, BlockRAM, local free-running operation intervalometer, output comparator and lock-out pulse Regenerator component,

Marginal detector, is used for detecting the rising edge triggered time stamp record simultaneously of outer lock-out pulse；

Timestamp record and parameter calculator, be used for recording outer lock-out pulse due in and estimating The interval of outer lock-out pulseReference instant with outer lock-out pulse

BlockRAM, is positioned at RAM resource on FPGA sheet, is used for storing time stamp data；

Local free-running operation intervalometer, is used for producing timestamp and participating in output triggering pulse shaping；

Synchronize predictor, by the interval of the incoming sync pulse estimatedWith main equipment lock-out pulse There is the momentPredict new lock-out pulse due inAnd carry out phase shift as required；

Output comparator, by constantly comparingWith local free-running operation intervalometer, when the two Time consistent, output synchronizes to trigger pulse；

Sync pulse regenerator, broadening output local synchronization pulse under the triggering of output comparator,

Marginal detector input input outer synchronous signal, the outfan of marginal detector with Timestamp record and parameter calculator are connected, timestamp record and parameter calculator respectively with BlockRAM, local free-running operation intervalometer are connected, timestamp record and parameter calculator Parameter output is connected with synchronization predictor, output comparator and sync pulse regenerator in turn, Local free-running operation intervalometer is also connected with output comparator, and sync pulse regenerator broadening is defeated Go out local synchronization pulse.

Lock-out pulse jitter suppression method of the present invention, realizes based on following temporal model, As it is shown in figure 1, (a) represents reference synchronization pulse in figure, (b), (c), (d) demonstrate synchronization Pulse arrives and synchronizes three kinds of situations that recipient occurs, the phase place that wherein (b) represents is advanced, (c) Representing delayed phase, (d) then represents that sync interval changes, it is assumed that lock-out pulse produces Equipment (hereinafter referred to as main equipment) is to be spaced (T_s) send lock-out pulse, corresponding moment t_{m_0}、t_{m_1}、 t_{m_2}、…、t_{m_n}、t_{m_n+1}、…、t_{m_n+k-1}..., synchronizing signal synchronized recipient (with Lower abbreviation is from equipment) recover after respectively corresponding moment t₀、t₁、t₂、…、t_n、t_n+1、…、t_n+k-1, Then lock-out pulse arrives (b), (c), (d) that may show as enumerating when equipment side such as Fig. 1 A kind of or the mixing of three kinds in three kinds of situations,

Generally assume that main equipment and comprise a randomized jitter and constant offset between equipment, Owing to fixing synchronization difference is easier to measure and compensate, so current invention assumes that master-slave equipment Between constant offset be 0 to have no effect on Time-Series analysis, temporal model can be with following simplification Expression formula represents:

t₀=t_{m_0}+ε₀,

t₁=t_{m_1}+ε₁=t_{m_0}+T_s+ε₁,

t₂=t_{m_2}+ε₂=t_{m_1}+T_s+ε₂....

t_n=t_{m_n}+ε_n=t_{m_1}+(n-1)T_s+ε_n....

t_n+k=t_{m_n+k}+ε_n+k=t_{m_1}+(n+k-1)T_s+ε_n+k....

Obviously ε₀, ε₁..., ε₂..., ε_n..., ε_n+k... it is a stochastic variable, sequence Row { t_nIncrease linearly over time, further, by continuous slippery sequence { t_nData window, The synchronization point from equipment is new can also reduce effectively to use up-to-date observation data to estimate The impact that the drift of principal and subordinate both sides' crystal brings.

The acquisition of timestamp is by building an edge sense circuit on the FPGA of equipment Intervalometer realization with a free-running operation, whenever synchronizing, edge detecting circuit detection is outer to be synchronized During one rising edge of signal, read the count value of local timer the most immediately as current time Stamp, and it is written into the BlockRAM of inside, it is derived from one group of time stamp data, is designated as: t₀、t₁、t₂、…、t_n、t_n+1、…、t_n+k-1, after external synchronization signal rising edge, by BlockRAM The timestamp of middle record takes out tectonic sequence { t_n}；

Sequence { t_nAlways linear increase on the basis of certain synchronization point of corresponding main equipment, Build difference sequence { Δ t further_nAnd consensus sequence { t_{s_n},

If Δ t_k=t_k-t_k-1, then difference sequence { Δ t_nBe expressed as follows；

Δt₁=t₁-t₀=T_s+(ε₁-ε₀),

Δt₂=t₂-t₁=T_s+(ε₂-ε₁),

Δt₃=t₃-t₂=T_s+(ε₃-ε₂) ...

Δt_n=t_n-t_n-1=T_s+(ε_n-ε_n-1) ...

Set again t_{s_k}=t_k-kT_s, then consensus sequence { t_{s_n}It is expressed as follows:

t_{s_1}=t₁=t_{m_1}+ε₁,

t_{s_2}=t₂-T_s=t_{m_1}+ε₂...

t_{s_n}=t_n-(n-1)T_s=t_{m_1}+ε_n...

Wherein, t_{m_1}For corresponding t₁Lock-out pulse reference instant time outside, ε₁…ε_nFor t_{s_1}…t_{s_n}Relatively In t_{m_1}Randomized jitter, it is clear that difference sequence { Δ t_nBe average be T_sRandom sequence, and benchmark Sequence { t_{s_n}Be then average be t_{m_1}Random sequence, therefore available sequences { t_{s_n}Average replace The moment is there is for main equipment lock-out pulseEstimation, and with sequence { Δ t_nAverage substitute right The interval of incoming sync pulseEstimation, obtain according to formula (1), (2),

${\hat{T}}_s=\frac{1}{n}\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}{t}_i=\frac{1}{n}[(t_1-t_0)+(t_2-t_1)+...+(t_n-t_{n-1})]=\frac{(t_n-t_0)}{n}---\left(1\right)$

By choosing { t_nT₀、t₁、t₂、…、t_nN+1 observation data, build sequence altogether {Δt_nEstimate sync intervalChoose wherein from t₁、t₂、…、t_nN observation data construct altogether Sequence { t_{s_n}Estimate main equipment lock-out pulse datum markBuild Linear Estimation equationAccording to the most estimated lock-out pulse intervalWith outer lock-out pulse reference instantPredict new lock-out pulse due in(can be calculating if desired for phase shiftSubtract again Go a desired phase-shift value)；WillThe output register of write output comparator.

Further, output comparator is by ceaselessly comparing output register and local timer Current count value, when the two is consistent comparator trigger pulse, sync pulse regeneration circuit handle Local synchronization pulse is exported after triggering the further broadening of pulse.Outside same owing to the most directly using Pace pulse, but utilize local clock pulses to predict by the method for Linear Estimation and recover to synchronize Signal, so the synchronizing signal shake of regeneration is the least, time delay is adjustable.

The present invention is by constructing two sequence { Δ t_nAnd { t_{s_n}Simplify smoothing processing algorithm, But some must be paid attention to below when implementing:

(1). for avoiding transmitting procedure being made mistakes and makeing mistakes along when recovering from equipment lock-out pulse, perform The point that interval is the most abnormal should be rejected before smoothing algorithm；

(2). when the length of data window can directly affect system start-up smooth effect and from equipment export The tracking time.The method that can be considered as changing data window length when realizing, if setting BlockRAM The storage depth capacity of design is W, and currently valid timestamp quantity is k, then construct difference Length n of sequence can consider to determine in the following method:

$n=\left\{\begin{array}{cc}k& k<W\\ W& k>=W\end{array}\right.$

(3). the bit wide as the intervalometer of local time stamp should be deep with the BlockRAM storage of design Degree and main equipment lock-out pulse be spaced and local crystal frequency relevant, it is achieved time at least ensure record During W timestamp, intervalometer occurs without zero backrush phenomenon.

The ultimate principle of the present invention, principal character and advantage have more than been shown and described.The skill of the industry Art personnel it should be appreciated that the present invention is not restricted to the described embodiments, above-described embodiment and explanation The principle that the present invention is simply described described in book, before without departing from spirit and scope of the invention Putting, the present invention also has various changes and modifications, and these changes and improvements both fall within requirement and protect In the scope of the invention protected.Claimed scope by appending claims and etc. Effect thing defines.

Claims (4)

1. a lock-out pulse jitter suppression method based on FPGA, it is characterised in that: include with Lower step,

Step (1), detects the rising edge of outer lock-out pulse by marginal detector, and upper Rise along the value recording current free-running operation intervalometer when arriving, this value is stabbed t as current time_n, BlockRAM on the sheet of write FPGA；

Step (2), after external synchronization signal rising edge, the timestamp that will record in BlockRAM Take out tectonic sequence { t_n}；

Step (3), chooses { t_nT₀、t₁、t₂、…、t_nN+1 observation data, structure altogether Make difference sequence { Δ t_nSo that Δ t_n=t_n-t_n-1, utilize { Δ t_nAverage estimate input synchronize The interval of pulse

Step (4), chooses sequence { t_nT₁、t₂、…、t_nN observation data construct base altogether Quasi-sequence { t_{s_n}So that t_{s_1}=t₁=t_{m_1}+ε₁、Wherein, t_{m_1}For corresponding t₁Lock-out pulse reference instant time outside, ε₁…ε_nFor t_{s_1}…t_{s_n}Relative to t_{m_1}With Machine is shaken, and with { t_{s_n}Estimation of Mean go out the reference instant of main equipment lock-out pulse

Step (5), builds Linear Estimation equationAccording to the most estimated synchronization Pulse spacingWith outer lock-out pulse reference instantPredict new lock-out pulse due in

Step (6), willThe output writing output comparator after deducting the amount needing to offset is posted Storage；

Step (7), intervalometer and the output of output comparator constantly relatively local free-running operation are posted The value of storage, once the two is consistent, triggers sync pulse regenerator broadening output local synchronization arteries and veins Punching.

Lock-out pulse jitter suppression method based on FPGA the most according to claim 1, its feature It is: step (3) chooses { t_nT₀、t₁、t₂、…、t_nN+1 observation data, structure altogether Build difference sequence { Δ t_n, and utilize formula (1) to estimate the interval of incoming sync pulse

${\hat{T}}_s=\frac{1}{n}\underset{i=1}{\overset{n}{\&Sigma;}}{\mathrm{\&Delta;t}}_i=\frac{1}{n}\&lsqb;(t_1-t_0)+(t_2-t_1)+...+(t_n-t_{n-1})\&rsqb;=\frac{(t_n-t_0)}{n}---\left(1\right).$

Lock-out pulse jitter suppression method based on FPGA the most according to claim 1, it is special Levy and be: step (4) is according to sequence { t_{s_n}Average, utilize that formula (2) estimation is main to be set There is the moment in standby lock-out pulse

4. the system of operation lock-out pulse jitter suppression method based on FPGA described in claim 1, It is characterized in that: be included in fpga chip build with lower component,

Marginal detector, is used for detecting the rising edge triggered time stamp record simultaneously of outer lock-out pulse；

Timestamp record and parameter calculator, be used for recording outer lock-out pulse due in and estimating The interval of outer lock-out pulseReference instant with outer lock-out pulse

BlockRAM, is positioned at RAM resource on FPGA sheet, is used for storing time stamp data；

Local free-running operation intervalometer, is used for producing timestamp and participating in output triggering pulse shaping；

Synchronize predictor, by the interval of the incoming sync pulse estimatedWith main equipment lock-out pulse There is the momentPredict new lock-out pulse due inAnd carry out phase shift as required；

Output comparator, by constantly comparingWith local free-running operation intervalometer, when the two Time consistent, output synchronizes to trigger pulse；

Sync pulse regenerator, broadening output local synchronization pulse under the triggering of output comparator；

The input input outer synchronous signal of described marginal detector, the output of marginal detector End is connected with timestamp record and parameter calculator, described timestamp record and parameter calculator Be connected with BlockRAM, local free-running operation intervalometer respectively, described timestamp record and The parameter output of parameter calculator is connected with synchronization predictor, output comparator and synchronization in turn Impulse regenerator, described local free-running operation intervalometer is also connected with output comparator, described The output local synchronization pulse of sync pulse regenerator broadening.