CN100530892C - Method for sampling, controlling and transmitting data synchronously - Google Patents
Method for sampling, controlling and transmitting data synchronously Download PDFInfo
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- CN100530892C CN100530892C CNB2007100224360A CN200710022436A CN100530892C CN 100530892 C CN100530892 C CN 100530892C CN B2007100224360 A CNB2007100224360 A CN B2007100224360A CN 200710022436 A CN200710022436 A CN 200710022436A CN 100530892 C CN100530892 C CN 100530892C
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The method comprises: using FPGA or CPLD to control the A/D sampling; setting up synchronous sampling control signals; the synchronous sampling signals are outputted from the channel decoder; the sampling signals are attached with the synchronous control signals by the channel encoder, and then are sent to the decode at opposite side to realize the restore of synchronous signals and the data decode. For a system with a master/slave structure, the master machine side periodically makes sampling, and the slave machine side is controlled by the master machine side and returns the sampling data; the data sampling and the channel encode approach of data transmission use synchronous and two-way transmission, and the transmission pulse of the channel encoder has the output synchronous signals; the slave machine uses said signals to start the data sampling and the data transmission.
Description
One. technical field
The present invention relates to the synchronous sampling method of data volume; especially the synchronized sampling control and data transmission method and relevant relay protecting method and device that the electric power system data amount is decoded; more specifically, the present invention relates to control and data transmission method based on the synchronized sampling of FPGA (CPLD).
Two. background technology
Various observing and controlling exchange the synchronized sampling of data volume in the electric power system at present with the protective device universal demand, and this is all significant for relay protection of power system, fault judgement, system stability analysis etc.And along with power system development, more and more higher to the requirement of system monitoring, an urgent demand can realize exchanging the strange land synchronized sampling of data volume.In addition, the transmission line Current Differential Protection develops into the full digital protection that utilizes microprocessor and digital communication at present from traditional guide wire mode.The digital current differential protection is to utilize the instantaneous sampling value of circuit two ends electric current to carry out differential comparison.For making the protection correct operation, synchronized sampling or sample-synchronous processing must be carried out in the circuit two ends, and this is a key problem in technology of realizing digital current differential protection.
Present existing synchronized sampling control method mainly comprises following five kinds of methods:
1. sampled data revised law.The both sides protection is regardless of the principal and subordinate when adopting this method, and the status is identical.The protection of every side all under crystal oscillator control separately with identical sample rate independent sample.Each frame sends data and comprises time tag, current sampling data and other information, and current sampling data is the electric current phasor of corresponding a certain sampling instant through Fourier transform.Receive under the equal prerequisite of data channel time-delay in the hypothesis both sides, adopt " isosceles trapezoid algorithm " to calculate communication channel delay t
d, and then obtain sampling deviation angle, both sides θ.Protection is taken advantage of twiddle factor e with the offside phasor that receives
J θ, get synchronously sampled data after obtaining revising.
2. method is adjusted in sampling instant.Both sides protect an end gauage to be decided to be main end (reference edge), and the other end is defined as from end (end synchronously), and main end is freely sampled.The master holds the photos and sending messages frame, will order after receiving from end with delay time and return to main end, and the master holds calculating communication channel delay t
d, adjust sampling instant according to the communication channel delay td that main end calculates from end.The sampling instant of main end is relatively independent, from the sampling instant adjustment of end according to main end, can keep the synchronized sampling of both sides degree of precision.
3. clock correction method.Both sides protect an end gauage to be decided to be main end (reference edge), and the other end is defined as from end (end synchronously), and main end is freely sampled.From end photos and sending messages frame, after receiving, master's end will order to return to from end with delay time, and from the relative error Δ t of end calculating both sides clock, it is zero clock being proofreaied and correct up to Δ t according to certain ratio from end, and the both sides clock enters the synchronous operation state.
4.GPS same footwork.Information when GPS is subjected to by GPS with footwork, the both sides synchronized sampling can reach quite high precision (2 μ s).But be subjected to the restriction of factors such as natural environment and social environment, and need the relevant hardware support.With reference to the same footwork of phasor (expect the file source arranged).Utilize circuit model to calculate two phasors of the same amount of representative, utilize the phase difference of these two phasors to realize synchronized sampling then.
The weak point of present existing synchronized sampling control method:
1. method consistent based on the two-way road of passage adjusted in sampled data revised law and sampling instant; for the two-way inconsistent situation of passage; the communication channel delay that calculates has error, and sensitivity reduces when making protection at troubles inside the sample space, may cause malfunction when external area error takes place.
2. after there is synchronization failure in the clock correction method, need the relative error Δ t of repeated calculation both sides clock once more synchronously, synchronizing relay is longer, influences the protective reaction time.
3. sampled data revised law, sampling instant adjustment method and clock correction method all are based on the modification method of software, even the sampling precision height, synchronization accuracy is still lower, generally in the ms level.
4. sampled data revised law, sampling instant adjustment method and clock correction method need additional period information to calculate communication channel delay when sending current sampling data, have also taken a large amount of channel resources simultaneously.
5.GPS be subjected to the restriction of factors such as natural environment and social environment with footwork, and need the relevant hardware support.Cost is higher.Synchronization accuracy is in μ s level.
6. be subjected to the influence of transmission line parameter and electrical quantities measurement error with reference to phasor with footwork, its precision can not be guaranteed.
Three. summary of the invention
The objective of the invention is: the synchronized sampling control and the data transmission method that propose a kind of data volume; especially the synchronized sampling control of electric power system data amount and data transmission method and relevant relay protecting method and device, and synchronized sampling control and the data transmission method realized based on FPGA (CPLD).A kind of synchronized sampling control method and high-speed data transmission passage of nanosecond especially are provided.
The object of the present invention is achieved like this: the synchronized sampling control and the data transmission method of data volume, by FPGA or CPLD control A/D sampling, and the synchronized sampling control signal is exported by channel decoder, sampled signal is delivered to the offside decoder after by channel encoder appended synchronization control signal, realizes that synchronizing signal recovers and data decode; It is to utilize the instantaneous sampling value of circuit two ends electric current to carry out differential comparison that the present invention can be used for the digital current differential protection.
Synchronized sampling control of the present invention and data transmission method, especially for the system of primary and secondary structure, the host computer side timing sampling is controlled by host computer side and returns sampled data from pusher side; The channel coding method of data sampling and transfer of data adopts synchronously and the data double-way transmission, and the channel encoder log-on data transmission pulse by main frame is provided with the output synchronizing signal in the pulse of channel encoder transfer of data; Slave uses this signal enabling data sampling and transfer of data; Promptly start the slave sampling at moment Ts, in all the other periods transmission data.In particular for method to the decoding of electric power system data amount.
The output synchronizing signal is continuous two width t
h(as=3/4T) signal that begins of expression frame synchronization, and in territory subsequently, transmit application layer data.
Wherein continuous two width t
h(as=3/4T) represent the signal that frame synchronization begins, width is t
0Logical zero is represented in the pulse of (=1/4T), and wherein width is t
1Logical one is represented in the pulse of (=1/4T); t
h--synchronizing signal t
f--synchronization frame width t
0--logical zero coding t
1--logical one coding, T--symbol width T
s--synchronization point
Slave is being received code signal, therefrom recovers synchronizing signal DSYN and command information, and in the rising edge startup ADC of DSYN sampling, the back starts encoder transmission last a sampled data constantly simultaneously.
Construct interrupt control unit by FPGA or CPLD, the interrupt source of controller comprises that decoder interrupts and ADC interrupts, and can shield respectively; After wherein ADC interrupts occurring in ADC EOC and data and has been read into the ADC controller; Decoder interrupts occurring in the dual port RAM that decoder deposits the previous frame data in decoder and receives after the new synchronizing signal.
Characteristics of the present invention:
1, utilize a pair of optical fiber to realize transfer of data and synchronized sampling, cost is low, good reliability.
2, message transmission rate height is finished a data transfer in the sampling period, and is fixing constantly, need not to insert markers, can directly transmit sampled data, is convenient to high layer software and carries out depth analysis.
3, automatic calculating channel transmission delay, synchronization accuracy is not influenced by channel physical length, not influenced by external condition.
4, employing realizes that based on the hardware of FPGA multi-part parallel running real-time is good.
5, the IP core that is constituted based on VHDL hardware description is transplanted to other platforms easily.
6, the synchronized sampling control method of nanosecond and high-speed data transmission passage.
Description of drawings
Fig. 1 is the system block diagram of synchronized sampling control of the present invention
Fig. 2 is that the present invention carries out the sample channel encoding scheme
Fig. 3 is the present invention and the MCU system connection diagram that the present invention is based on FPGA
Embodiment
1, system is a primary and secondary structure, and the host computer side timing sampling is controlled by host computer side and returns sampled data from pusher side.ADC_SYN is a master ADC enabling signal among the figure, and ESYN is a channel encoder log-on data transmission pulse.DSYN is a channel decoder output synchronizing signal.Slave postpones signal enabling ADC host computer using ESYN and DSYN signal calculated.LOCK is that decoder receives efficient coding data and locking.
2, signal encoding and decoding
Invention is adopted and is carried out sample-synchronous and transfer of data as Fig. 2 channel coding schemes:
Among Fig. 2 chnnel coding figure
t
h--synchronizing signal t
f--synchronization frame width t
0--logical zero coding t
1--the logical one coding
T--symbol width T
s--synchronization point
The high level of coding comprises information, continuous two width t
hThe expression of (=3/4T) frame synchronization begins, and transmits application layer data in territory subsequently, and wherein width is t
0Logical zero is represented in the pulse of (=1/4T), and wherein width is t
1Logical one is represented in the pulse of (=1/4T).
3, synchronized sampling implementation method
As main frame, under the control of sample clock generator, start encoder constantly at Ts and send the order comprise synchronizing information and configuration data frame to channel, host A DC controller postpones Δ t and starts the ADC sampling with compensate for channel delay and software delays in the back constantly at Ts.
Slave therefrom recovers synchronizing signal DSYN and command information receiving code signal shown in Figure 2, and in the rising edge startup ADC of DSYN sampling, the back starts encoder transmission last a sampled data constantly simultaneously.
4, interruption controls realizes
The present invention constructs interrupt control unit by FPGA, and the interrupt source of controller comprises that decoder interrupts and ADC interrupts, and can shield respectively.After wherein ADC interrupts occurring in ADC EOC and data and has been read into the ADC controller.Decoder interrupts occurring in the dual port RAM that decoder deposits the previous frame data in decoder and receives after the new synchronizing signal.
During concrete enforcement, be connected by Fig. 3 with the MCU system based on the present invention of FPGA:
During as main frame, MCU issues control command and configuration parameter by channel encoder, reads local adc data when ADC interrupts, and reads the offside slave and send sampled data and postpone two sampling intervals in decoder interrupts, and delivers to high layer software and handles.
5, channel latency is calculated
The present invention's hypothesis bidirectional transmission path in transmission course postpones the same, promptly
Δ 2t=t is up+and t is descending, gets Δ t=(t up+t is descending)/2
When the host computer side encoder starts, utilize ESYN to start timer, utilize decoder DSYN end of output channel timer, the count value of timer is channel latency 2 Δ t.
6, channel conditions monitors
The present invention monitors that by decoder component the data code flow on the receive channel comes the monitoring channel working condition, send Lock signal indication channel locks to master controller when channel is good, be convenient to high layer software and take algorithms of different or control strategy according to the channel working condition.
7, FPGA or CPLD can be various FPGA (Field Programmable Gate Array) control chips, also comprise the AD chip that can realize this function.
Claims (6)
1, synchronized sampling control and data transmission method, by FPGA or CPLD control A/D sampling, be provided with the synchronized sampling control signal, the synchronized sampling control signal is exported by channel decoder, sampled signal is delivered to the channel decoder of offside after by channel encoder appended synchronization signal, realizes that synchronizing signal recovers and data decode; It is characterized in that adopting the system of primary and secondary structure, the host computer side timing sampling is controlled by host computer side and returns sampled data from pusher side; The channel coding method of data sampling and transfer of data adopts synchronously and the data double-way transmission, and the channel encoder log-on data transmission pulse by main frame is provided with synchronizing signal in the pulse of channel encoder transfer of data; Slave uses sampling of synchronizing signal log-on data and transfer of data; Promptly start the slave sampling, in all the other period transmission data at synchronization point Ts.
2, synchronized sampling control according to claim 1 and data transmission method is characterized in that synchronizing signal is continuous two width t
hThe signal that expression frame synchronization begins, width is t
0Logical zero is represented in pulse, and wherein width is t
1Logical one is represented in pulse; t
h--synchronizing signal t
f--synchronization frame width t
0--logical zero coding t
1--logical one coding, T--symbol width T
s--synchronization point; And in territory subsequently, transmit application layer data.
3, synchronized sampling control according to claim 1 and data transmission method, it is characterized in that slave is at the code signal of receiving the transmission of main frame channel encoder, therefrom recover synchronizing signal and command information, and in the rising edge startup ADC of synchronizing signal sampling, the back starts channel encoder transmission last a sampled data constantly simultaneously.
4, synchronized sampling control according to claim 1 and data transmission method is characterized in that constructing interrupt control unit by FPGA or CPLD, and the interrupt source of interrupt control unit comprises that decoder interrupts and ADC interrupts, and can shield respectively; After wherein ADC interrupts occurring in ADC EOC and data and has been read into the ADC controller; Decoder interrupts occurring in the dual port RAM that channel decoder deposits the previous frame data in channel decoder and receives after the new synchronizing signal; Be provided with LOCK signal indication channel decoder and receive efficient coding data and locking.
5, synchronized sampling control according to claim 1 and data transmission method, it is characterized in that main frame uses synchronizing signal startup ADC and utilizes ESYN and the delay of synchronizing signal calculating channel: wherein ESYN is channel encoder log-on data transmission pulse; As bidirectional transmission path in the transmission course postpones, get Δ t=(t up+t is descending)/2
When the host computer side channel encoder starts, utilize ESYN to start timer, utilize the synchronizing signal end of output channel timer of channel decoder, the count value of timer is channel latency 2 Δ t.
6, synchronized sampling control according to claim 1 and data transmission method is characterized in that utilizing programming device to realize synchronized sampling and transmission method:
1) host computer side starts ADC controlling of sampling logic and comprehensive channel delay by sample clock generator,
2) the ESYN signal of host computer using channel encoder and channel decoder synchronizing signal calculating channel postpone, and ESYN is a channel encoder log-on data transmission pulse,
3) utilize the channel decoder synchronizing signal to start ADC control from pusher side,
4) slave transfers timing sampling automatically to after channel decoder does not have input.
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101262380B (en) * | 2008-04-17 | 2011-04-06 | 中兴通讯股份有限公司 | A device and method for FPGA simulation |
| CN101316160B (en) * | 2008-06-11 | 2010-12-15 | 南京磐能电力科技股份有限公司 | Multi-node synchronization sampling and data transmission method |
| RU2524383C1 (en) * | 2010-11-09 | 2014-07-27 | Абб Рисерч Лтд. | Synchronisation method for differential current protection |
| CN102647271B (en) * | 2012-03-22 | 2014-12-03 | 国电南瑞科技股份有限公司 | Self-adaption fine-adjusting method for protection interrupt time interval |
| CN104852464B (en) * | 2014-02-19 | 2018-01-23 | 台达电子企业管理（上海）有限公司 | The transmitting device and method of synchronizing information and the power electronic equipment with the device |
| CN105656591B (en) * | 2015-12-30 | 2018-09-11 | 杭州娃哈哈精密机械有限公司 | The method of data collection synchronous when serial encoder in servo-drive system communicates |
| CN106603452B (en) * | 2017-02-23 | 2019-12-10 | 武汉米风通信技术有限公司 | Timing sampling and frequency offset correction method based on multichannel communication receiving system |
| CN112771736A (en) * | 2018-09-26 | 2021-05-07 | Asml荷兰有限公司 | Apparatus and method for providing high precision delay in lithography system |
| CN111291011B (en) * | 2020-02-19 | 2023-10-20 | 北京百度网讯科技有限公司 | File synchronization method and device, electronic equipment and readable storage medium |
| CN111934537B (en) * | 2020-08-21 | 2023-07-21 | 湖北师范大学 | Anti-interference method for driving signals of cascade converter |
| CN114745512A (en) * | 2022-03-25 | 2022-07-12 | 天远三维（天津）科技有限公司 | Image acquisition method, apparatus, medium, and system |
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