CN112771736A - Apparatus and method for providing high precision delay in lithography system - Google Patents
Apparatus and method for providing high precision delay in lithography system Download PDFInfo
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- H—ELECTRICITY
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- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S3/00—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
- H01S3/09—Processes or apparatus for excitation, e.g. pumping
- H01S3/097—Processes or apparatus for excitation, e.g. pumping by gas discharge of a gas laser
- H01S3/09702—Details of the driver electronics and electric discharge circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05G—X-RAY TECHNIQUE
- H05G2/00—Apparatus or processes specially adapted for producing X-rays, not involving X-ray tubes, e.g. involving generation of a plasma
- H05G2/001—X-ray radiation generated from plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S3/00—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
- H01S3/10—Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating
- H01S3/13—Stabilisation of laser output parameters, e.g. frequency or amplitude
- H01S3/131—Stabilisation of laser output parameters, e.g. frequency or amplitude by controlling the active medium, e.g. by controlling the processes or apparatus for excitation
- H01S3/134—Stabilisation of laser output parameters, e.g. frequency or amplitude by controlling the active medium, e.g. by controlling the processes or apparatus for excitation in gas lasers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S3/00—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
- H01S3/14—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range characterised by the material used as the active medium
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- H01S3/225—Gases the active gas being polyatomic, i.e. containing two or more atoms comprising an excimer or exciplex
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05G—X-RAY TECHNIQUE
- H05G2/00—Apparatus or processes specially adapted for producing X-rays, not involving X-ray tubes, e.g. involving generation of a plasma
- H05G2/001—X-ray radiation generated from plasma
- H05G2/003—X-ray radiation generated from plasma being produced from a liquid or gas
- H05G2/005—X-ray radiation generated from plasma being produced from a liquid or gas containing a metal as principal radiation generating component
Abstract
Methods and apparatus for controlling pulses in a laser system include controlling the relative timing of trigger pulses in a multi-cavity laser system to control the delay of respective firings of multiple cavities, including the use of a combination of field programmable gate arrays and programmable delay circuits.
Description
Cross Reference to Related Applications
This application claims priority from us application 62/740,191 filed on day 10 and 2 in 2018 and us application 62/736,738 filed on day 26 in 2018, the contents of each of which are incorporated herein by reference in their entirety.
Technical Field
Aspects of the present disclosure relate to control of laser-generated light sources, such as are used in integrated circuit lithographic fabrication processes.
Background
A system for generating laser radiation (deep ultraviolet (DUV) wavelength) at frequencies useful for semiconductor lithography involves the use of a Master Oscillator Power Amplifier (MOPA) dual gas discharge chamber configuration. For laser dose stability, it is necessary to manage the relative timing of the pulses (shots) in the Master Oscillator (MO) portion of the MOPA relative to the pulses (shots) in the Power Amplifier (PA) portion of the MOPA. A similar master oscillator seed may also be used that provides other amplifier configurations such as a power oscillator ("PO") for the laser system. However, for the sake of brevity, unless explicitly indicated otherwise, the term MOPA or the terms MO and PA, respectively, will be construed to mean any such multi-cavity laser system, e.g. a two-cavity laser system, e.g. comprising an oscillator seed pulse generating part, which optimizes the beam parameter quality, followed by amplification of the seed pulse by an amplifier part receiving any kind of seed pulse, which serves as an amplification function and is adjusted for the amplification process, so that the specific beam quality parameter(s) optimized in the master oscillator part are more or less preserved.
Extreme ultraviolet ("EUV") light, such as electromagnetic radiation having a wavelength of about 50nm or less (sometimes also referred to as soft X-rays), and including light having a wavelength of about 13.5nm, is used in lithographic processes to produce extremely small features on substrates such as silicon wafers. The term "light" is used herein and elsewhere herein, even though it is understood that the radiation described using this term may not be in the visible portion of the spectrum. A method for generating EUV light includes converting a target material from a liquid state to a plasma state. The target material preferably comprises at least one element, such as xenon, lithium or tin, and has one or more emission lines in the EUV range. In one such method, often referred to as laser produced plasma ("LPP"), a desired plasma may be produced by irradiating a target material having a desired line emitting element with a laser beam. For dose stability, it is also necessary to manage the relative timing of the pulses in the EUV system.
It is desirable to provide an alternative to existing devices or methods for managing relative pulse timing in such systems.
Disclosure of Invention
The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of the invention. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.
According to one aspect of an embodiment, disclosed herein is a laser system comprising: a field programmable gate array configured to generate a first digital signal that transitions from a first logic level to a second logic level over a plurality of clock cycles and configured to generate a second digital signal that is a logical inverse of the first digital signal; a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay to generate a delayed first digital signal; a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay; a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate a pulse if and only if both the first digital signal and the delayed second digital signal are at a second logic level.
According to an aspect of an embodiment, there is also disclosed herein a laser system comprising a module configured to supply a first pulse having a first duration and a second pulse having a second duration, wherein a start of the first pulse and a start of the second pulse are separated in time by a delay interval, the module comprising: a field programmable gate array configured to generate a first digital signal that transitions from a first logic level to a second logic level at time t1 over a plurality of clock cycles, a second digital signal that is a logical inversion of the first digital signal, a third digital signal that transitions from the first logic level to the second logic level at time t2 later than time t1 over a plurality of clock cycles, and a fourth digital signal that is a logical inversion of the third digital signal; a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first time delay to generate a delayed first digital signal; a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay; a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate a first pulse if and only if both the first digital signal and the delayed second digital signal are at a second logic level; a third programmable delay circuit arranged to receive the third digital signal and configured to delay propagation of the third digital signal by a third delay to generate a delayed third digital signal; a fourth programmable delay circuit arranged to receive the fourth digital signal and configured to delay propagation of the fourth digital signal by a fourth delay to generate a delayed fourth digital signal, the fourth delay being greater than the third delay; and a second logic circuit arranged to receive the delayed third digital signal and the delayed fourth digital signal and configured to generate the second pulse after the first pulse has stopped if and only if both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.
The laser system may be a system for generating deep ultraviolet radiation, and the laser system further comprises: a first trigger circuit arranged to receive a first pulse and for causing a first chamber of a laser to fire in response to the first pulse; and a second trigger circuit arranged to receive the second pulse and for causing a second chamber of the laser to fire in response to the second pulse.
The laser system may be a system for generating extreme ultraviolet radiation, and the laser system further comprises: a first trigger circuit arranged to receive the first pulse and for causing the first laser pulse to fire in response to the first pulse; and a second trigger circuit arranged to receive the second pulse and for causing the second laser pulse to fire in response to the second pulse.
The laser system may include: a first laser chamber arranged to receive a first laser chamber excitation pulse based on a first pulse; and a second laser chamber arranged to receive a second laser chamber excitation pulse based on the second pulse.
According to an aspect of an embodiment, there is also disclosed herein a method of generating a trigger pulse for a laser system, the method comprising: generating a first digital signal that transitions from a first logic level to a second logic level over a plurality of clock cycles, and generating a second digital signal that is a logical inverse of the first digital signal; delaying the propagation of the first digital signal by a first delay to generate a delayed first digital signal; delaying the propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay; and generating a pulse if and only if both the first digital signal and the delayed second digital signal are at the second logic level.
According to an aspect of an embodiment, there is also disclosed herein a method of generating a trigger pulse for a laser system, the method comprising: generating a first digital signal that transitions from a first logic level to a second logic level at time t1 over a plurality of clock cycles and a second digital signal that is a logical inverse of the first digital signal; delaying the propagation of the first digital signal by a first delay to generate a delayed first digital signal; delaying the propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay; and generating the first pulse if and only if both the first digital signal and the delayed second digital signal are at the second logic level; generating a third digital signal that transitions from the first logic level to the second logic level at a time t2 later than t1 over a plurality of clock cycles, and a logically inverted fourth digital signal of the holy third digital signal; delaying the propagation of the third digital signal by a third delay to generate a delayed third digital signal; delaying the propagation of the fourth digital signal by a fourth delay to generate a delayed fourth digital signal, the fourth delay being greater than the third delay; and generating a second pulse after the first pulse stops if and only if both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.
The method may further comprise the steps of: a power diverter supplying a first pulse as a trigger to a first chamber of the multi-chamber laser, and a power diverter supplying a second pulse as a trigger to a second chamber of the multi-chamber laser.
The steps of generating the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal may be performed by a field programmable gate array.
The method may further comprise the steps of: the first pulse is supplied as a trigger to excite the first pulse at the target material, and the second pulse is supplied as a trigger to excite the second pulse at the target material. The first pulse may be a pre-pulse and the second pulse may be a main pulse.
The step of delaying the first digital signal may be performed by a first programmable delay circuit.
The step of delaying the second digital signal may be performed by a second programmable delay circuit.
The step of delaying the third digital signal may be performed by a third programmable delay circuit.
The step of delaying the fourth digital signal may be performed by a fourth programmable delay circuit.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the present invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Other embodiments will be apparent to those skilled in the relevant art(s) based on the teachings contained herein.
Drawings
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art(s) to make and use the invention.
FIG. 1 shows a schematic view, not to scale, of the general broad concept of a lithography system according to an aspect of the disclosed solution.
Fig. 2 shows a schematic view, not to scale, of the overall generalized concept of an illumination system for generating deep ultraviolet radiation according to an aspect of the disclosed solution.
Fig. 3 shows a schematic view, not to scale, of the overall generalized concept of an illumination system for generating extreme ultraviolet radiation according to an aspect of the disclosed solution.
Fig. 4 is a functional block diagram of circuitry for generating delayed pulses.
Fig. 5 is a functional block diagram of circuitry for generating delayed pulses in accordance with an aspect of an embodiment.
Fig. 6 is a timing diagram illustrating signal levels and timing for an example of a mode of operation of the circuitry of fig. 4 in accordance with an aspect of an embodiment.
The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements.
Detailed Description
Various embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it may be apparent in some or all examples that any of the embodiments described below may be practiced without employing the specific design details described below. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments. The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of the embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments.
Reference in the described embodiment(s) and specification to "one embodiment," "an embodiment," "one example embodiment," etc., indicates that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include Read Only Memory (ROM); random Access Memory (RAM); a magnetic disk storage medium; an optical storage medium; a flash memory device; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact result from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc.
Before describing such embodiments in more detail, it is instructive to present an example environment in which embodiments of the present invention may be implemented. Although the following examples pertain to DUV systems, one of ordinary skill in the art will appreciate that the subject matter disclosed herein may also be applied to other laser systems, such as, for example, systems for generating EUV radiation.
Referring to FIG. 1, the lithography system 100 includes an illumination system 105. As described more fully below, the illumination system 105 includes a light source that generates and directs a pulsed light beam 110 to a lithographic exposure apparatus or scanner 115, which lithographic exposure apparatus or scanner 115 patterns microelectronic features on a wafer 120. The wafer 120 is placed on a wafer stage 125, the wafer stage 125 being configured to hold the wafer 120 and being connected to a positioner configured to accurately position the wafer 120 according to certain parameters.
In the example of FIG. 1, the lithography system 100 uses a beam 110 having a wavelength in the Deep Ultraviolet (DUV) range (e.g., having a wavelength of 248 nanometers (nm) or 193 nm). The size of the microelectronic features patterned on the wafer 120 depends on the wavelength of the beam 110, with lower wavelengths resulting in smaller minimum feature sizes. When the wavelength of the optical beam 110 is 248nm or 193nm, the minimum dimension of the microelectronic features may be, for example, 50nm or less. The bandwidth of the light beam 110 may be the actual instantaneous bandwidth of its spectrum (or emission spectrum) that contains information about how the light energy of the light beam 110 is distributed over different wavelengths. The scanner 115 comprises an optical arrangement with, for example, one or more condenser lenses, a mask and an objective lens arrangement. The mask may be moved in one or more directions, such as along the optical axis of the beam 110 or in a plane perpendicular to the optical axis. The objective lens arrangement comprises a projection lens and enables image transfer from the mask to the photoresist on the wafer 120 to occur. The illumination system 105 adjusts the range of angles at which the beam 110 is incident on the mask. The illumination system 105 also homogenizes (homogenizes) the intensity distribution of the beam 110 across the mask.
The scanner 115 may include, among other features, a lithography controller 130, air conditioning equipment, and power supplies for various electrical components. The lithography controller 130 controls how layers are printed on the wafer 120. The lithography controller 130 includes a memory that stores information such as process recipes. The process recipe or recipe determines the length of exposure time on the wafer 120, the mask used, and other factors that affect the exposure. During photolithography, multiple pulses of the beam 110 irradiate the same area of the wafer 120 to constitute an irradiation dose.
The lithography system 100 also preferably includes a control system 135. Generally, the control system 135 includes one or more of digital electronic circuitry, computer hardware, firmware, and software. The control system 135 also includes memory, which may be read-only memory and/or random access memory. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and a CD-ROM disk.
The control system 135 may also include one or more input devices (such as a keyboard, touch screen, microphone, mouse, handheld input device, etc.) and one or more output devices (such as a speaker or monitor). The control system 135 also includes one or more programmable processors and one or more computer program products tangibly embodied in a machine-readable storage device for execution by the one or more programmable processors. One or more programmable processors can each execute a program of instructions to perform desired functions by operating on input data and generating appropriate output. Generally, a processor receives instructions and data from a memory. Any of the foregoing may be supplemented by, or incorporated in, specially-designed ASICs (application-specific integrated circuits). The control system 135 may be centralized or may be distributed, partially or entirely, throughout the lithography system 100.
Referring to fig. 2, the exemplary illumination system 105 is a pulsed multi-chamber laser source that generates a pulsed laser beam as beam 110. Fig. 2 depicts one particular assembly of components and optical paths strictly for the purpose of facilitating the description of the broad principles of the present invention, and it will be readily apparent to those of ordinary skill in the art that the principles of the present invention may be advantageously applied to lasers having other components and configurations.
FIG. 2 schematically illustrates, in block diagram form, a gas discharge laser system in accordance with an embodiment of certain aspects of the disclosed technology. The gas discharge laser system may include, for example, a solid-state or gas discharge seed laser system 140, a power amplification ("PA") stage, such as a power loop amplifier ("PRA") stage 145, relay optics 150, and a laser system output subsystem 160. Seed system 140 may include, for example, a master oscillator ("MO") chamber 165 in which a discharge between, for example, electrodes (not shown) may cause a laser gas discharge in the laser gas to produce an opposing population of high energy molecules (e.g., including Ar, Kr, or Xe) to produce relatively broad radiation that may be line narrowed to a relatively narrow bandwidth and selected center wavelength in a line narrowing module ("LNM") 170, as is known in the art.
The amplification stage 145 may comprise, for example, a laser chamber 200, which may also be an oscillator, e.g. formed by seed beam injection and out-coupling optics (not shown), which may be incorporated into the PRA WEB 210 and may be redirected back through the gain medium in the chamber 200 by the beam reverser 220. The PRA WEB 210 may incorporate a partially reflective input/output coupler (not shown) and a maximum mirror (e.g., near 193nm for an ArF system) and one or more prisms for a nominal operating wavelength.
A bandwidth analysis module ("BAM") 230 at the output of the amplification stage 145 may receive the pulsed output laser beam from the amplification stage and pick up a portion of the beam for metrology purposes, such as for measuring output bandwidth and pulse energy. The pulsed laser output beam then passes through an optical pulse stretcher ("OPuS") 240 and an output combining automatic shutter metering module ("CASMM") 250, which may also be the location of the pulse energy meter. One purpose of OPuS 240 may be, for example, to convert a single output laser pulse into a pulse train. The secondary pulses generated by the original single output pulse may be delayed with respect to each other. By distributing the original laser pulse energy into the secondary pulse train, the effective pulse length of the laser can be extended while the peak pulse intensity is reduced. Thus, OPuS 240 may receive the laser beam from PRA WEB 210 via BAM 230 and direct the output of OPuS 240 to CASMM 250.
The MO and PA delay commands may be used to indicate to the TEM 310 how long after a reference trigger (e.g., trigger T from the customer interface) the corresponding trigger is issued to the corresponding pulse power system 315. There may be one pulsed power system for each of the MO and PA or PRA.
In an EUV light source, EUV may be generated by: a target profile is produced from the flying metal droplet via a laser pre-pulse and subsequently heated to a plasma state with a second laser pulse. The pre-pulse laser hits the droplets to modify the distribution of the target material, and the main pulse laser hits the target to heat it to the EUV emitting plasma. In some systems, the pre-pulse and the main heating pulse are provided by the same laser system, and in other systems, there are two separate lasers. In some cases, the reflection of the main pulse from the formed target is used as a diagnostic of the formed target or the target location. For efficient and debris-minimized operation of the light source, it is important to "aim" the flying droplets to within a few microns.
Figure 3 is a non-to-scale schematic of an EUV system 260 using both a pre-pulse and a main pulse. The EUV system 260 includes, among other features, a radiation source 265 capable of generating a pre-pulse 267 followed by a main pulse 268. The pre-pulse 267 and the main pulse 268 propagate into a chamber 285, the chamber 285 including a collector mirror 287 at which the pre-pulse 267 and the main pulse 268 strike an amount of target material 290 at an irradiation location 295. In the example shown, the target material 290 is initially in the form of a stream of droplets released by a target material dispenser 292, which target material dispenser 292 is a drop generator in this example. The target material 290 may be ionized in this form by the main pulse. Alternatively, the target material 290 may be pre-treated to ionize it with, for example, a pre-pulse that may alter the geometric distribution of the target material 290. Thus, it may be necessary to both accurately hit the target material 290 with the pre-pulse 267 to ensure that the target material 290 is in the desired form (disk, cloud, etc.), and accurately hit the target with the main pulse to promote efficient generation of EUV radiation. All this takes place under the control of the control circuit.
Several systems have been used in the past to accurately strike the target material with a pre-pulse or main pulse, including using reflected light from the operating pulse or using a second laser or light source to illuminate the droplet. For example, U.S. patent No. 7,372,056 entitled "LPP EUV Plasma Material Target Delivery System," issued on 13.5.2008, discloses a drop detection radiation Source and a radiation detector that detects drop detection radiation reflected from a drop of a Target Material, which is incorporated herein in its entirety.
FIG. 4 is a functional block diagram of circuitry that may be used to control the relative timing of the firing of pulses, e.g., MO 165 and PRA 200 chambers in a DUV system or pre-and main pulses in an EUV system. Shown in fig. 4 is a Fire Control Circuit (FCC)300 that may send MO and PA delay commands from a power and timing controller 305 to a timing and power module (TEM) 310. The TEM 310 may further send MO and PA commutator triggers to the pulse power system 315 to initiate discharge of a charging capacitor (not shown) through solid state switching elements (not shown) in the pulse power system 315. Since electrical energy is supplied to a respective pair of electrodes through the lasing gas medium between the electrodes in each of the respective MOs and PA, the respective triggering produces a resulting gas discharge. In an EUV system, a module such as a TEM, for example, may be used to control the relative timing of the pre-pulse and main pulse firings.
The primary function of the TEM 310 is to generate high precision delayed pulses. A TEM such as TEM 310 may be used in DUV and EUV systems. The principles disclosed herein are useful for both DUV and EUV systems. In a DUV system, the TEM generates two pulses, one for the Master Oscillator (MO) and one for the Power Amplifier (PA). The existing specifications for these two pulses are:
1-pulse duration for MO and PA 500ns
2-maximum delay from reference trigger to MO commutator trigger 27us
3-maximum delay from reference trigger to PA commutator trigger 27us
4-delay resolution <250ps for MO and PA triggering
5-delay jitter <250ps for MO and PA triggering
According to one aspect of an embodiment, circuitry including a Field Programmable Gate Array (FPGA) in combination with a Programmable Delay Chip (PDC) is used to generate the necessary high precision delay. These devices, which are used separately from each other, have limitations. For example, FPGAs are generally not capable of producing sub-nanosecond logic. The first tap of the PDC has a fixed propagation delay and the delay range is also very small. However, combining these two techniques may overcome these limitations.
FIG. 5 shows an example of a circuit that combines FPGA 400 with PDCs 410, 415, 420, and 425. In more detail, FPGA 400 receives the pulse data command and inputs trigger a. As a result, circuitry 440 within FPGA 400 generates four signals b1, b2, b3, and b4 under control of oscillator 445. The first signal b1 is applied to the programmable delay circuit 410, and the programmable delay circuit 410 delays the propagation of the first signal b 1. The second signal b2 is inverted by the inverter 450 and supplied to the programmable delay circuit 415, and the programmable delay circuit 415 delays the propagation of the second signal b2 by a second delay that is greater in magnitude than the first delay. The outputs of programmable delay circuit 410 AND programmable delay circuit 415 are applied to logic circuit 430, which logic circuit 430 may be, for example, an AND (AND) gate. The resulting signal P1 is used, for example, as a trigger for one chamber of a multi-chamber laser.
The third signal b3 is applied to the programmable delay circuit 420, and the programmable delay circuit 420 delays the propagation of the third signal b 3. The fourth signal b4 is inverted by inverter 450 and supplied to programmable delay circuit 425, and programmable delay circuit 425 delays the propagation of fourth signal b4 by a delay that is greater than the magnitude of the delay imposed on the third signal by programmable delay circuit 420. The outputs of programmable delay circuit 420 and programmable delay circuit 425 are applied to logic circuit 435, which logic circuit 435 may be, for example, an and gate. The resulting signal P2 is used, for example, as a trigger for the second chamber of a multi-chamber laser.
The programmable delay circuits 410, 415, 420, and 425 are programmed by a programming module 460, which programming module 460 may be part of the FPGA 400, for example.
An example of an FPGA suitable for use as FPGA 400 is the Xilinx Kintex 7 FPGA (speed class-3). The FPGA is limited to a maximum clock frequency of 800MHz (1.25 ns). Is suitable for use as PDAn example of a PDC of C410, 415, 420, and 425 is the ON semiconductor programmable delay chip MC100EP196BMNG, the total available delay of which is at
In increments of 10 ps.
In the arrangement of fig. 5, FPGA 400 is used to generate coarse delays (which also enables microsecond and millisecond delays). The PDCs 410, 415, 420, and 425 are used to generate fine (10ps increments) delays. In the above example, a Phase Locked Loop (PLL) internal to the FPGA 400 is used to generate a 400MHz clock (2.5ns period), which 2.5ns period matches the delay to the first tap of the PDCs 410, 415, 420 and 425, thus making it possible to have a continuous range of delays. In this case, the coarse delay resolution is 2.5ns and the fine delay resolution is 10ps, calculated as follows:
fig. 6 shows the creation of two 1ns wide pulses with a 1ns spacing. For clarity of the plot, one nanosecond is used as the basis for FIG. 5, but it will be apparent to those of ordinary skill in the art that the same relative timing may be used in the circuit shown in FIG. 4 to generate picosecond resolution timing. As shown in fig. 5, the top signal labeled "1 ns period" is a clock signal. The next signal traveling down in the figure is labeled "b 1" and is the first signal described above. As can be seen, the signal b1 goes from the first logic level to the second logic level on the rising edge of the clock and then transitions from the second logic level to the first logic level after a number of clock cycles.
Is marked as
The next signal down of (a) is the logical inverse of signal b 1. The next signal down, labeled "b 1_ Delayed _2 ns", is signal b1 Delayed by two clock cycles. Is marked as
The next signal down is a signal delayed by three clock cycles
The next signal down, labeled "Pulse 1_1 ns", is "b 1_ Delayed _2 ns" and
the result of performing an AND operation. This results in a pulse lasting one clock cycle.
The next signal traveling down in the figure is labeled b3 and is the third signal described above. As can be seen, the signal b3 goes from the first logic level to the second logic level on the rising edge of the clock and then transitions from the second logic level to the first logic level after a number of clock cycles.
Is marked as
The next signal down of (a) is the logical inverse of signal b 4. The next signal down, labeled "b 3_ Delayed _2 ns", is signal b3 Delayed by two clock cycles. Is marked as
The next signal down is a signal delayed by three clock cycles
The next signal down, labeled "Pulse 2_1 ns", is "b 3_ Delayed _2 ns" and
the result of performing an AND operation. This results in a pulse lasting oneA clock period, the pulse being delayed by one clock period from the first pulse. The relative timing of the transitions in signal b1 and signal b3 determines the amount of delay between pulse 1 and pulse 2.
Jitter in digital systems is caused by instability of the oscillator electronics. Therefore, when using an FPGA, it should be avoided to use any PPL/DCM/MMCM inside the FPGA that might otherwise experience jitter in the range of about 50-100 ps. Depending on design requirements, an oscillator with appropriate frequency stability may be selected. An example of such an oscillator is Abracon LLC ASGTX-D-400.000MHZ-1, with a maximum jitter of 1.8 ps. Both analog and digital techniques suffer from jitter due to thermal noise and external disturbances of power and ground.
The above description includes examples of various embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the described embodiments are intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim. Furthermore, although elements of the described aspects and/or embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated. Additionally, all or a portion of any aspect and/or embodiment may be utilized with all or a portion of any other aspect and/or embodiment, unless stated otherwise.
Other aspects of the invention are set forth in the following numbered clauses.
1. A laser system, comprising:
a field programmable gate array configured to generate a first digital signal that transitions from a first logic level to a second logic level over a plurality of clock cycles and configured to generate a second digital signal that is a logical inverse of the first digital signal;
a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay to generate a delayed first digital signal;
a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay; and
a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate a pulse if and only if both the first digital signal and the delayed second digital signal are at a second logic level.
2. A laser system, comprising:
a module configured to supply a first pulse having a first duration and a second pulse having a second duration, wherein a start of the first pulse and a start of the second pulse are separated in time by a delay interval, the module comprising
A field programmable gate array configured to generate, over a plurality of clock cycles, a first digital signal that transitions from a first logic level to a second logic level at time t1, a second digital signal that is a logical inverse of the first digital signal, a third digital signal that transitions from the first logic level to the second logic level at time t2 later than time t1, and a fourth digital signal that is a logical inverse of the third digital signal;
a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay to generate a delayed first digital signal,
a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay,
a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate a first pulse if and only if both the first digital signal and the delayed second digital signal are at a second logic level,
a third programmable delay circuit arranged to receive the third digital signal and configured to delay propagation of the third digital signal by a third delay to generate a delayed third digital signal,
a fourth programmable delay circuit arranged to receive the fourth digital signal and configured to delay propagation of the fourth digital signal by a fourth delay to generate a delayed fourth digital signal, the fourth delay being greater than the third delay, an
A second logic circuit arranged to receive the delayed third digital signal and the delayed fourth digital signal and configured to generate a second pulse after the first pulse has stopped if and only if both the delayed third digital signal and the delayed fourth digital signal are at a second logic level.
3. The laser system according to clause 2, wherein the laser system is a system for generating deep ultraviolet radiation, and the laser system further comprises
A first trigger circuit arranged to receive the first pulse and for causing a first chamber of the laser to fire in response to the first pulse, an
A second trigger circuit arranged to receive the second pulse and for causing a second chamber of the laser to fire in response to the second pulse.
4. The laser system according to clause 2, wherein the laser system is a system for generating extreme ultraviolet radiation, and the laser system further comprises
A first trigger circuit arranged to receive the first pulse and for causing the first laser pulse to fire in response to the first pulse, an
A second trigger circuit arranged to receive the second pulse and for causing the second laser pulse to fire in response to the second pulse.
5. The laser system of clause 2, further comprising
A first laser chamber arranged to receive a first laser chamber excitation pulse based on the first pulse, an
A second laser chamber arranged to receive a second laser chamber excitation pulse based on the second pulse.
6. A method of generating a trigger pulse for a laser system, the method comprising:
generating a first digital signal that transitions from a first logic level to a second logic level over a plurality of clock cycles and generating a second digital signal that is a logical inverse of the first digital signal;
delaying the propagation of the first digital signal by a first delay to generate a delayed first digital signal;
delaying the propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay; and
the pulse is generated if and only if both the first digital signal and the delayed second digital signal are at the second logic level.
7. A method of generating a trigger pulse for a laser system, the method comprising:
generating a first digital signal that transitions from a first logic level to a second logic level at time t1 over a plurality of clock cycles and generating a second digital signal that is a logical inverse of the first digital signal;
delaying the propagation of the first digital signal by a first delay to generate a delayed first digital signal;
delaying the propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay;
generating a first pulse if and only if both the first digital signal and the delayed second digital signal are at a second logic level;
generating a third digital signal that transitions from the first logic level to the second logic level at a time t2 later than t1 over a plurality of clock cycles, and generating a fourth digital signal that is a logical inverse of the third digital signal,
delaying the propagation of the third digital signal by a third delay to generate a delayed third digital signal,
delaying the propagation of the fourth digital signal by a fourth delay to generate a delayed fourth digital signal, the fourth delay being greater than the third delay, an
The second pulse is generated after the first pulse stops if and only if both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.
8. The method of clause 7, further comprising:
supplying a first pulse as a trigger to a power commutator of a first chamber of the multi-chamber laser; and
a second pulse is supplied as a trigger to a power commutator of a second chamber of the multi-chamber laser.
9. The method of clause 7, wherein the steps of generating the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal are performed by a field programmable gate array.
10. The method of clause 7, further comprising the steps of:
supplying a first pulse as a trigger to excite the first pulse at the target material, and
a second pulse is supplied as a trigger to excite the second pulse at the target material.
11. The method of clause 7, wherein the first pulse is a pre-pulse and the second pulse is a main pulse.
12. The method of clause 7, wherein the step of delaying the first digital signal is performed by a first programmable delay circuit.
13. The method of clause 7, wherein the step of delaying the second digital signal is performed by a second programmable delay circuit.
14. The method of clause 7, wherein the step of delaying the third digital signal is performed by a third programmable delay circuit.
15. The method of clause 7, wherein the step of delaying the fourth digital signal is performed by a fourth programmable delay circuit.
Claims (15)
1. A laser system, comprising:
a field programmable gate array configured to generate a first digital signal that transitions from a first logic level to a second logic level over a plurality of clock cycles and configured to generate a second digital signal that is a logical inverse of the first digital signal;
a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay to generate a delayed first digital signal;
a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay; and
a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate a pulse if and only if both the first digital signal and the delayed second digital signal are at the second logic level.
2. A laser system, comprising:
a module configured to supply a first pulse having a first duration and a second pulse having a second duration, wherein a start of the first pulse and a start of the second pulse are separated in time by a delay interval, the module comprising
A field programmable gate array configured to generate a first digital signal that transitions from a first logic level to a second logic level at time t1 over a plurality of clock cycles, a second digital signal that is a logical inversion of the first digital signal, a third digital signal that transitions from a first logic level to a second logic level at time t2 later than time t1 over a plurality of clock cycles, and a fourth digital signal that is a logical inversion of the third digital signal;
a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay to generate a delayed first digital signal,
a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay,
a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate the first pulse if and only if both the first digital signal and the delayed second digital signal are at the second logic level,
a third programmable delay circuit arranged to receive the third digital signal and configured to delay propagation of the third digital signal by a third delay to generate a delayed third digital signal,
a fourth programmable delay circuit arranged to receive the fourth digital signal and configured to delay propagation of the fourth digital signal by a fourth delay to generate a delayed fourth digital signal, the fourth delay being greater than the third delay, an
A second logic circuit arranged to receive the delayed third digital signal and the delayed fourth digital signal and configured to generate the second pulse after a stop of the first pulse if and only if both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.
3. The laser system according to claim 2, wherein the laser system is a system for generating deep ultraviolet radiation, and the laser system further comprises
A first trigger circuit arranged to receive the first pulse and for causing a first chamber of the laser to be excited in response to the first pulse, an
A second trigger circuit arranged to receive the second pulse and to cause a second chamber of the laser to fire in response to the second pulse.
4. The laser system of claim 2, wherein the laser system is a system for generating extreme ultraviolet radiation, and further comprising
A first trigger circuit arranged to receive the first pulse and for causing a first laser pulse to fire in response to the first pulse, an
A second trigger circuit arranged to receive the second pulse and to cause a second laser pulse to fire in response to the second pulse.
5. The laser system of claim 2, further comprising
A first laser chamber arranged to receive a first laser chamber excitation pulse based on the first pulse, an
A second laser chamber arranged to receive a second laser chamber excitation pulse based on the second pulse.
6. A method of generating a trigger pulse for a laser system, the method comprising:
generating a first digital signal that transitions from a first logic level to a second logic level over a plurality of clock cycles and generating a second digital signal that is a logical inverse of the first digital signal;
delaying propagation of the first digital signal by a first delay to generate a delayed first digital signal;
delaying propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay; and
generating a pulse if and only if both the first digital signal and the delayed second digital signal are at the second logic level.
7. A method of generating a trigger pulse for a laser system, the method comprising:
generating a first digital signal that transitions from a first logic level to a second logic level at time t1 over a plurality of clock cycles and generating a second digital signal that is a logical inverse of the first digital signal;
delaying propagation of the first digital signal by a first delay to generate a delayed first digital signal;
delaying propagation of the second digital signal by a second delay to generate a delayed second digital signal, the second delay being greater than the first delay;
generating the first pulse if and only if both the first digital signal and the delayed second digital signal are at the second logic level;
generating a third digital signal that transitions from the first logic level to the second logic level at a time t2 later than t1 over a plurality of clock cycles and generating a fourth digital signal that is a logical inverse of the third digital signal,
delaying propagation of the third digital signal by a third delay to generate a delayed third digital signal,
delaying propagation of the fourth digital signal by a fourth delay to generate a delayed fourth digital signal, the fourth delay being greater than the third delay, an
Generating the second pulse after the stopping of the first pulse if and only if both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.
8. The method of claim 7, further comprising:
supplying the first pulse as a trigger to a power commutator of a first chamber of a multi-chamber laser; and
supplying the second pulse as a trigger to a power diverter of a second chamber of the multi-chamber laser.
9. The method of claim 7, wherein the steps of generating the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal are performed by a field programmable gate array.
10. The method of claim 7, further comprising the steps of:
supplying the first pulse as a trigger to excite the first pulse at the target material, an
Supplying the second pulse as a trigger to excite a second pulse at the target material.
11. The method of claim 7, wherein the first pulse is a pre-pulse and the second pulse is a main pulse.
12. The method of claim 7, wherein the step of delaying the first digital signal is performed by a first programmable delay circuit.
13. The method of claim 7, wherein the step of delaying the second digital signal is performed by a second programmable delay circuit.
14. The method of claim 7, wherein the step of delaying the third digital signal is performed by a third programmable delay circuit.
15. The method of claim 7, wherein the step of delaying the fourth digital signal is performed by a fourth programmable delay circuit.
Applications Claiming Priority (5)
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| US201862736738P | 2018-09-26 | 2018-09-26 | |
| US62/736,738 | 2018-09-26 | ||
| US201862740191P | 2018-10-02 | 2018-10-02 | |
| US62/740,191 | 2018-10-02 | ||
| PCT/EP2019/071533 WO2020064194A1 (en) | 2018-09-26 | 2019-08-12 | Apparatus for and method of providing high precision delays in a lithography system |
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| CN112771736A true CN112771736A (en) | 2021-05-07 |
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| CN201980063240.7A Pending CN112771736A (en) | 2018-09-26 | 2019-08-12 | Apparatus and method for providing high precision delay in lithography system |
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| JP (1) | JP7394843B2 (en) |
| CN (1) | CN112771736A (en) |
| NL (1) | NL2023632A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113359396A (en) * | 2021-05-31 | 2021-09-07 | 安徽国芯智能装备有限公司 | High-speed photoetching method based on synchronous control of light source and pattern generator |
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| TW202037022A (en) | 2020-10-01 |
| TWI819071B (en) | 2023-10-21 |
| WO2020064194A1 (en) | 2020-04-02 |
| NL2023632A (en) | 2020-05-01 |
| JP7394843B2 (en) | 2023-12-08 |
| JP2022502690A (en) | 2022-01-11 |
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