CN101290921A - Package base with wafer covered with thin membrane preventing deformation of thin membrane - Google Patents
Package base with wafer covered with thin membrane preventing deformation of thin membrane Download PDFInfo
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- CN101290921A CN101290921A CNA2007100902689A CN200710090268A CN101290921A CN 101290921 A CN101290921 A CN 101290921A CN A2007100902689 A CNA2007100902689 A CN A2007100902689A CN 200710090268 A CN200710090268 A CN 200710090268A CN 101290921 A CN101290921 A CN 101290921A
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- 239000012528 membrane Substances 0.000 title claims description 150
- 238000003466 welding Methods 0.000 claims abstract description 43
- 238000005728 strengthening Methods 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 7
- LENZDBCJOHFCAS-UHFFFAOYSA-N tris Chemical compound OCC(N)(CO)CO LENZDBCJOHFCAS-UHFFFAOYSA-N 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 19
- 239000010409 thin film Substances 0.000 abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 9
- 230000008569 process Effects 0.000 abstract description 7
- 239000010408 film Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000008093 supporting effect Effects 0.000 abstract description 2
- 230000002349 favourable effect Effects 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 description 14
- 238000010276 construction Methods 0.000 description 12
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 238000012545 processing Methods 0.000 description 9
- 238000007731 hot pressing Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
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- 238000005516 engineering process Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
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- 230000003319 supportive effect Effects 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
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- 230000000750 progressive effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention relates to a thin-film flip-chip package substrate for preventing deformation of a film, mainly comprising a flexible dielectric layer, a plurality of pins, an anti-welding layer which locally covers the pins, and a reinforced layer. The pins are arranged on an upper surface of the flexible dielectric layer, wherein, the inner ends of the pins are extended into a wafer coverage area of the flexible dielectric layer; and the reinforced layer is formed on a lower surface of the flexible dielectric layer and can be correspondingly arranged on the wafer coverage area. The strength of the thin-film flip-chip package substrate can be reinforced in virtue of the structure and deformations such as collapse or warping and so on due to heating during the connecting process of a wafer can be avoided. In different embodiments, the reinforced layer is correspondingly arranged outside the wafer coverage area. The thin-film flip-chip package substrate can reinforce the supporting property of the wafer coverage area of the thin-film flip-chip package substrate, can avoid collapse deformation of the thin-film flip-chip package substrate during the connecting process of the wafer, and can be favorable for the assembling and manufacturing process of connection of external pins due to capability of reducing warping deformation.
Description
Technical field
The present invention relates to a kind of flexible base plate of integrated circuit encapsulation, particularly relate to a kind of supportive that can strengthen the wafer area of coverage of package base with wafer covered with thin membrane, can avoid this package base with wafer covered with thin membrane generation collapse-deformation when wafer engages, in addition also can be by alleviating buckling deformation, and can help the package base with wafer covered with thin membrane that prevents deformation of thin membrane (SUBSTRATE OFCHIP-ON-FILM PACKAGE FOR PREVENTING FILM DEFORMATION) of the assembling processing procedure that outer pin engages.
Background technology
In numerous integrated circuit encapsulated types, thin-film flip-chip packaging construction (COF) is to utilize the projection wafer to be bonded on the package base with wafer covered with thin membrane and sealing.The projection of wafer and the joint method of the interior pin on the package base with wafer covered with thin membrane also have multiple technologies at present, and for example the hot pressing eutectic engages (Eutecticbonding), non-conductive adhesive engages (NCP bonding) and engages (ACF bonding) or the like with the anisotropy conducting film.When wafer engages employing hot pressing eutectic joint, can reach preferable welding conductive effect.In addition, the interior pin that can continue to use existing coil type carrying encapsulation (TCP) engages (ILB) equipment, one hot pressing syncephalon is to pressurize earlier and be heated to package base with wafer covered with thin membrane, be crimped to the projection of wafer again, right this mode can cause package base with wafer covered with thin membrane to be heated producing subsiding (collapse) or warpage distortion such as (warpage), make subsequent handling gluing difficulty, acceptance rate reduces; The quality that more can influence packaging structure engages (Outer Lead Bonding, assembling processing procedure OLB) with follow-up outer pin.
Seeing also shown in Figure 1ly, is the schematic cross-section of existing known package base with wafer covered with thin membrane.A kind of existing known package base with wafer covered with thin membrane 100 comprises a pliability dielectric layer 110, a plurality of pin 120 and a welding resisting layer 130.This pliability dielectric layer 110 has a upper surface 111 and a lower surface 112, and these upper surface 111 definition have a wafer area of coverage.Those pins 120 are arranged at this upper surface 111 of this pliability dielectric layer 110.This welding resisting layer 130 is to form this upper surface 111 that is arranged at this pliability dielectric layer 110, and local those pins 120 that cover.One perforate 131 of this welding resisting layer 130 is to be slightly larger than this wafer area of coverage, with the inner 121 that appears those pins 120, for plurality of bump 211 joints of a wafer 210.
Seeing also shown in Figure 2ly, is the schematic cross-section of existing known package base with wafer covered with thin membrane generation collapse-deformation when engaging with wafer.In the process that wafer engages, one wafer 210 is to pick and place on a heatable microscope carrier 10, and with a hot pressing syncephalon 20 these package base with wafer covered with thin membrane 100 of compressing, be engaged to the plurality of bump 211 of this wafer 210 with the inner 121 with those pins 120, this package base with wafer covered with thin membrane 100 can cause collapse-deformation because of being heated, make the gap between this package base with wafer covered with thin membrane 100 and this wafer 210 can produce uncontrolled irregular variation, even this package base with wafer covered with thin membrane 100 can direct subsides touch this wafer 210.
Therefore, seeing also shown in Figure 3ly, is the schematic cross-section that existing known package base with wafer covered with thin membrane is applied to a thin-film flip-chip packaging construction.In follow-up sealing operation, the adhesive body 220 that one spot printing forms can't fill up the gap of this wafer 210 and this package base with wafer covered with thin membrane 100 by capillarity, so can produce the bubble 221 of filler disappearance at the collapse-deformation place, make this adhesive body 220 at high temperature be easy to generate the fracture phenomena that pops.
In addition, seeing also shown in Figure 4ly, is the side schematic view that existing known package base with wafer covered with thin membrane is applied to the generation buckling deformation of a thin-film flip-chip packaging construction.Utilize existing known package base with wafer covered with thin membrane 100 can be packaged into thin-film flip-chip packaging construction (COF package), the heat treated that suffers in processing procedure will make the both sides of this package base with wafer covered with thin membrane 100 outside this wafer 210 produce buckling deformation, and then (Outer Lead Bonding, assembling processing procedure OLB) is difficult to carry out smoothly to cause follow-up outer pin joint.
This shows that above-mentioned existing package base with wafer covered with thin membrane obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane of new structure, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned existing package base with wafer covered with thin membrane exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane of new structure, can improve general existing package base with wafer covered with thin membrane, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the defective that existing package base with wafer covered with thin membrane exists, and provide a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane of new structure, technical problem to be solved is to make it can strengthen the supportive of the wafer area of coverage of this package base with wafer covered with thin membrane, can avoid the distortion that this package base with wafer covered with thin membrane generation is subsided when wafer engages, be very suitable for practicality.
Another object of the present invention is to, a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane of new structure is provided, technical problem to be solved is to make it can alleviate the distortion of warpage, be beneficial to outer pin and engage (Outer Lead Bonding, OLB) assembling processing procedure, thus be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane that the present invention proposes, it comprises: a pliability dielectric layer, and it has a upper surface and a lower surface, and wherein this upper surface is that definition has a wafer area of coverage; A plurality of pins, it is arranged at this upper surface of this pliability dielectric layer, and wherein the inner of those pins more extends in this wafer area of coverage; One welding resisting layer, this upper surface that it is formed at this pliability dielectric layer covers those pins with the part; And a strengthening layer, it is formed at this lower surface of this pliability dielectric layer, and correspondence is arranged at this wafer area of coverage.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The aforesaid package base with wafer covered with thin membrane that prevents deformation of thin membrane, wherein said strengthening layer are to be identical material with this welding resisting layer.
The aforesaid package base with wafer covered with thin membrane that prevents deformation of thin membrane, wherein said welding resisting layer has rectangular without exception perforate, and it is corresponding to this wafer area of coverage.
The aforesaid package base with wafer covered with thin membrane that prevents deformation of thin membrane, the area coverage of wherein said strengthening layer are this perforates greater than this welding resisting layer.
The aforesaid package base with wafer covered with thin membrane that prevents deformation of thin membrane, wherein said strengthening layer is made up of a plurality of finishing strips.
The aforesaid package base with wafer covered with thin membrane that prevents deformation of thin membrane, wherein said those finishing strips be roughly parallel to this welding resisting layer perforate than minor face.
The object of the invention to solve the technical problems also adopts following technical scheme to realize.According to a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane that the present invention proposes, it comprises: a pliability dielectric layer, and it has a upper surface and a lower surface, and wherein this upper surface is that definition has a wafer area of coverage; A plurality of pins, it is this upper surface that is arranged at this pliability dielectric layer, wherein the inner of those pins more extends in this wafer area of coverage; One welding resisting layer, this upper surface that it is formed at this pliability dielectric layer covers those pins with the part; And a strengthening layer, it is formed at this lower surface of this pliability dielectric layer, and the corresponding zone that is arranged at beyond this wafer area of coverage.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The aforesaid package base with wafer covered with thin membrane that prevents deformation of thin membrane, wherein said strengthening layer has a perforate, and it is corresponding and is a bit larger tham this wafer area of coverage.
The aforesaid package base with wafer covered with thin membrane that prevents deformation of thin membrane, wherein said strengthening layer has a plurality of finishing strips, and it is the outer end of corresponding those pins.
The aforesaid package base with wafer covered with thin membrane that prevents deformation of thin membrane, wherein said strengthening layer are to be covered in this lower surface of this pliability dielectric layer corresponding to the remaining surface beyond this wafer area of coverage.
The present invention compared with prior art has tangible advantage and beneficial effect.As known from the above, for achieving the above object,, mainly comprise a pliability dielectric layer, a plurality of pin, a welding resisting layer and a strengthening layer (stiffenerlayer) according to a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane of the present invention.This pliability dielectric layer has a upper surface and a lower surface, and wherein this upper surface definition has a wafer area of coverage.Those pins are arranged at this upper surface of this pliability dielectric layer, and wherein the inner of those pins more extends in this wafer area of coverage.This welding resisting layer is formed at this upper surface of this pliability dielectric layer, covers those pins with the part.This strengthening layer is formed at this lower surface of this pliability dielectric layer, and correspondence is arranged at this wafer area of coverage.In different embodiment, this strengthening layer can corresponding be arranged at the zone beyond this wafer area of coverage.
In aforesaid package base with wafer covered with thin membrane, this strengthening layer can be identical material with this welding resisting layer.This welding resisting layer can have rectangular without exception perforate, and it is corresponding to this wafer area of coverage.The area coverage of strengthening layer can be greater than this perforate of this welding resisting layer.This strengthening layer can be made up of a plurality of finishing strips.Those finishing strips be roughly parallel to this welding resisting layer perforate than minor face.
By technique scheme, the present invention prevents that the package base with wafer covered with thin membrane of deformation of thin membrane has following advantage and beneficial effect at least:
1, the present invention can strengthen the supportive of the wafer area of coverage of this package base with wafer covered with thin membrane, can avoid the distortion that this package base with wafer covered with thin membrane generation is subsided when wafer engages, and is very suitable for practicality.
2 moreover, the present invention can alleviate the distortion of warpage, and can help outer pin engage (OuterLead Bonding, assembling processing procedure OLB), thereby be suitable for practicality more.
In sum, the present invention prevents the package base with wafer covered with thin membrane of deformation of thin membrane, can strengthen the intensity of this package base with wafer covered with thin membrane, subsides or distortion such as warpage and can avoid being heated in wafer bonding process and produce.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and more existing package base with wafer covered with thin membrane has the outstanding effect of enhancement, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the schematic cross-section that has known package base with wafer covered with thin membrane now.
Fig. 2 has the schematic cross-section that produces collapse-deformation when known package base with wafer covered with thin membrane engages with wafer now.
Fig. 3 is the schematic cross-section that existing known package base with wafer covered with thin membrane is applied to a thin-film flip-chip packaging construction.
Fig. 4 is the side schematic view that existing known package base with wafer covered with thin membrane is applied to the generation buckling deformation of a thin-film flip-chip packaging construction.
Fig. 5 is according to first specific embodiment of the present invention, a kind of schematic cross-section that prevents the package base with wafer covered with thin membrane of deformation of thin membrane.
Fig. 6 is according to first specific embodiment of the present invention, the bottom surface partial schematic diagram of this package base with wafer covered with thin membrane.
Fig. 7 is according to first specific embodiment of the present invention, the schematic cross-section when this package base with wafer covered with thin membrane engages with wafer.
Fig. 8 is according to first specific embodiment of the present invention, uses the schematic cross-section of a kind of thin-film flip-chip packaging construction of this package base with wafer covered with thin membrane.
Fig. 9 is that another kind prevents the bottom surface partial schematic diagram of the package base with wafer covered with thin membrane of deformation of thin membrane according to second specific embodiment of the present invention.
Figure 10 is according to second specific embodiment of the present invention, and this package base with wafer covered with thin membrane is along the generalized section of 10-10 hatching among Fig. 9.
Figure 11 is that another kind prevents the schematic bottom view of the package base with wafer covered with thin membrane of deformation of thin membrane according to the 3rd specific embodiment of the present invention.
Figure 12 is that another kind prevents the schematic bottom view of the package base with wafer covered with thin membrane of deformation of thin membrane according to the 4th specific embodiment of the present invention.
10: microscope carrier 20: the hot pressing syncephalon
100: package base with wafer covered with thin membrane 110: the pliability dielectric layer
111: upper surface 112: lower surface
120: pin 121: the inner
130: welding resisting layer 131: perforate
210: wafer 211: projection
220: adhesive body 221: bubble
300: package base with wafer covered with thin membrane 310: the pliability dielectric layer
311: upper surface 312: lower surface
313: the wafer area of coverage 320: pin
321: inner 330: welding resisting layer
331: perforate 340: strengthening layer
410: wafer 411: projection
420: adhesive body 500: package base with wafer covered with thin membrane
510: pliability dielectric layer 511: upper surface
512: lower surface 513: the wafer area of coverage
520: pin 521: the inner
530: welding resisting layer 531: perforate
540: strengthening layer 541: finishing strips
600: package base with wafer covered with thin membrane 610: the pliability dielectric layer
611: the wafer area of coverage 612: sprocket hole
613: perforate 620: pin
621: inner 622: the outer end
630: strengthening layer 631: finishing strips
700: package base with wafer covered with thin membrane 710: the pliability dielectric layer
711: the wafer area of coverage 712: sprocket hole
720: strengthening layer 721: perforate
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of the package base with wafer covered with thin membrane that prevents deformation of thin membrane, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
By the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to get one more deeply and concrete understanding to the present invention, yet appended graphic only provide with reference to the usefulness of explanation, be not to be used for the present invention is limited.
See also Fig. 5, shown in Figure 6, Fig. 5 is according to the present invention's first specific embodiment, and a kind of schematic cross-section that prevents the package base with wafer covered with thin membrane of deformation of thin membrane, Fig. 6 are the bottom surface partial schematic diagrams of this package base with wafer covered with thin membrane.According to first specific embodiment of the present invention, disclosed a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane.As shown in Figure 5, this package base with wafer covered with thin membrane 300 mainly comprises a pliability dielectric layer 310, a plurality of pin 320, a welding resisting layer 330 and a strengthening layer 340.
Above-mentioned pliability dielectric layer 310 has a upper surface 311 and a lower surface 312, and wherein, these upper surface 311 definition have a wafer area of coverage 313 (as shown in Figure 6).The size of this wafer area of coverage 313 is essence sizes corresponding to a wafer.The material of common this pliability dielectric layer 310 can be pi, and (polyimide PI), and has good flexibility.Before encapsulation, a plurality of substrates can be integrally formed at a winding, for coil type transmission carrying out membrane of flip chip packaging operation.
Those above-mentioned pins 320 are arranged at the upper surface 311 of this pliability dielectric layer 310, and wherein the inner 321 of those pins 320 more extends in this wafer area of coverage 313, and manifests dewiness.Usually the material of those pins 320 is to be copper, and should considerably approach so that suitable flexibility to be provided.
Above-mentioned welding resisting layer 330 is the upper surfaces 311 that are formed at this pliability dielectric layer 310, covers those pins 320 with the part, can prevent that those pins 320 are because of exposing contaminated short circuit.This welding resisting layer 330 has a perforate 331, and it is corresponding to this wafer area of coverage 313, with the inner 321 that appears those pins 320.Usually the perforate 331 of this welding resisting layer 330 is to be a bit larger tham this wafer area of coverage 313.
Please cooperate and consult strengthening layer shown in Figure 6, above-mentioned 340, be this lower surface 312 that is formed at this pliability dielectric layer 310, and correspondence is arranged at this wafer area of coverage 313.In the present embodiment, this strengthening layer 340 is made up of the plurality of patterns block.The shape of this strengthening layer 340 can be in order to compensate this perforate 331 of this welding resisting layer 330, to strengthen the intensity of this package base with wafer covered with thin membrane 300, so the wafer area of coverage 313 of this package base with wafer covered with thin membrane 300 that can keep from heat in wafer bonding process produces distortion.Please consult shown in Figure 6ly again, the area coverage of this strengthening layer 340 can be greater than this perforate 331 of this welding resisting layer 330.Preferably, this strengthening layer 340 can be identical material with this welding resisting layer 330, so this strengthening layer 340 can utilize same processing procedure (manufacturing process) to form with this welding resisting layer 330, and the complexity that cost and processing procedure are set of unlikely increase element.
Seeing also shown in Figure 7ly, is according to first specific embodiment of the present invention, the schematic cross-section when this package base with wafer covered with thin membrane engages with wafer.In interior pin engaging process, one wafer, 410 desirable being placed on the microscope carrier 10, one hot pressing syncephalon 20 can apply this lower surface 312 of this pliability dielectric layer 310 of pressure force and this package base with wafer covered with thin membrane 300 of heating, makes the inners 321 of those pins 320 be bonded to the plurality of bump 411 of this wafer 410.And this strengthening layer 340 is these lower surfaces 312 that are formed at this pliability dielectric layer 310.When these 20 pressurizations of hot pressing syncephalon and this lower surface 312 that calorifies this pliability dielectric layer 310, this strengthening layer 340 can be strengthened the intensity of this package base with wafer covered with thin membrane 300 at this wafer area of coverage 313, and this package base with wafer covered with thin membrane 300 that can keep from heat produces the metaboly that subsides.In follow-up sealing step, see also shown in Figure 8, be according to first specific embodiment of the present invention, use the schematic cross-section of a kind of thin-film flip-chip packaging construction of this package base with wafer covered with thin membrane, one adhesive body 420 can be filled between this wafer 410 and this package base with wafer covered with thin membrane 300, makes its inside can not produce the problem of bubble.
According to first specific embodiment of the present invention, this package base with wafer covered with thin membrane 300 can further be applied to a thin-film flip-chip packaging construction.See also shown in Figure 8ly, a kind of thin-film flip-chip packaging construction mainly comprises an aforesaid package base with wafer covered with thin membrane 300 and a wafer 410.
This wafer 410 is arranged at this wafer area of coverage 313 of this substrate 300, and is electrically connected to those pins 320.In the present embodiment, this wafer 410 is provided with plurality of bump 411, and it is engaged to the inner 321 of those pins 320.This thin-film flip-chip packaging construction also can include an adhesive body 420 in addition, for example a kind of spot printing colloid that before curing, has high fluidity, it is formed between this wafer 410 and this substrate 300, to seal the exposed inner 321 of those projections 411 and those pins 320, can prevent signal short circuit and burning.
See also Fig. 9, shown in Figure 10, Fig. 9 is that another kind prevents the bottom surface partial schematic diagram of the package base with wafer covered with thin membrane of deformation of thin membrane according to second specific embodiment of the present invention, and this package base with wafer covered with thin membrane of Figure 10 is along the generalized section of 10-10 hatching among Fig. 9.According to second specific embodiment of the present invention, disclosed the another kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane.This package base with wafer covered with thin membrane 500 mainly comprises a pliability dielectric layer 510, a plurality of pin 520, a welding resisting layer 530 and a strengthening layer 540.
Above-mentioned pliability dielectric layer 510 has a upper surface 511 and a lower surface 512, and wherein these upper surface 511 definition have a wafer area of coverage 513.Those pins 520 are arranged at this upper surface 511 of this pliability dielectric layer 510, and wherein the inner 521 of those pins 520 more extends in this wafer area of coverage 513 (as shown in Figure 9).
Above-mentioned welding resisting layer 530 is formed at this upper surface 511 of this pliability dielectric layer 510, covers those pins 520 with the part, can prevent that those pins 520 are because of exposing contaminated short circuit.This welding resisting layer 530 can have a perforate 531, and it is corresponding and be a bit larger tham this wafer area of coverage 513.
Above-mentioned strengthening layer 540 are these lower surfaces 512 that are formed at this pliability dielectric layer 510, and correspondence is arranged at this wafer area of coverage 513.Please consult shown in Figure 9ly again, in the present embodiment, this strengthening layer 540 can be made up of a plurality of finishing strips 541.The perforate 531 of this welding resisting layer 530 can be for generally rectangular, those finishing strips 541 be roughly parallel to this welding resisting layer 530 perforate 531 than minor face.
Therefore, the wafer area of coverage 513 of 540 pairs of these package base with wafer covered with thin membrane 500 of this strengthening layer provides the supporting role of more strengthening, and makes the wafer area of coverage 513 of this package base with wafer covered with thin membrane 500 be not easy to produce the metaboly that subsides in wafer bonding process.In addition, in manufacture procedure of adhesive, can so that adhesive body insert equably between wafer and this package base with wafer covered with thin membrane 500, can the gassing phenomenon.
Seeing also shown in Figure 11ly, is according to the 3rd specific embodiment of the present invention, and another kind prevents the schematic bottom view of the package base with wafer covered with thin membrane of deformation of thin membrane.According to the 3rd specific embodiment of the present invention, disclosed the another kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane, can reduce the distortion that thin-film flip-chip packaging construction (COF package) produces warpage.This package base with wafer covered with thin membrane 600 mainly comprises a pliability dielectric layer 610, a plurality of pin 620 and a strengthening layer 630.
Above-mentioned pliability dielectric layer 610, its upper surface definition has a wafer area of coverage 611, as the wafer setting area.This pliability dielectric layer 610 can form the sprocket hole 612 that is provided with a plurality of equidistant arrangements at two transmission equipment sides and the position outside encapsulation unit.
Those above-mentioned pins 620 are arranged at this upper surface of this pliability dielectric layer 610, so illustrate with dotted line.Wherein, each pin 620 has a inner 621 (or claiming interior pin) and an outer end 622 (or claiming outer pin).Those the inners 621 more extend in this wafer area of coverage 611 and are exposed at the opening of a welding resisting layer outward, for the projection (not drawing among the figure) that engages a wafer.One welding resisting layer is formed at the upper surface of this pliability dielectric layer 610, covers those pins 620 with the part.
Above-mentioned strengthening layer 630, it is a lower surface that is formed at this pliability dielectric layer 610, and corresponding this wafer area of coverage 611 zone in addition that is arranged at, when using this package base with wafer covered with thin membrane to be packaged into the membrane of flip chip encapsulating products, can be in order to alleviate the buckling deformation that this pliability dielectric layer 610 produces.More specifically explanation, this strengthening layer 630 are to have a perforate 613, and it is corresponding and is a bit larger tham this wafer area of coverage 611.In the present embodiment, this strengthening layer 630 is to be moulding shape.Preferably, this strengthening layer 630 can have a plurality of finishing strips 631, and it is the outer end 622 of corresponding those pins 620, and the buckling deformation that can alleviate two outer engagement sides of this pliability dielectric layer 610 can be avoided influencing follow-up outer pin and engage (OLB) processing procedure.
Seeing also shown in Figure 12ly, is according to the 4th specific embodiment of the present invention, and another kind prevents the schematic bottom view of the package base with wafer covered with thin membrane of deformation of thin membrane.According to the 4th specific embodiment of the present invention, disclosed the another kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane, can reduce the distortion of warpage.This package base with wafer covered with thin membrane 700 mainly comprises a pliability dielectric layer 710, a plurality of pin (not drawing among the figure) and a strengthening layer 720.
Above-mentioned pliability dielectric layer 710, the definition of one upper surface has a wafer area of coverage 711.This pliability dielectric layer 710 can form the sprocket hole 712 that is provided with a plurality of equidistant arrangements at two transmission equipment sides and the position outside encapsulation unit.The upper surface of this pliability dielectric layer 710 is that those pins and a welding resisting layer are set.
Above-mentioned strengthening layer 720 is formed at a lower surface of this pliability dielectric layer 710, and the corresponding zone that is arranged at beyond this wafer area of coverage 711.By this, can reduce the buckling deformation phenomenon of this pliability dielectric layer 710.In the present embodiment, this strengthening layer 720 has a perforate 721, corresponding to this wafer area of coverage 711, all the other lower surfaces at an encapsulation unit are then occupied by this strengthening layer 720, so this strengthening layer 720 is to be covered in the lower surface of this pliability dielectric layer 710 corresponding to the remaining surface beyond this wafer area of coverage 711.This strengthening layer 720 can be an anti-welding material.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (10)
1, a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane is characterized in that it comprises:
One pliability dielectric layer, it has a upper surface and a lower surface, and wherein this upper surface is that definition has a wafer area of coverage;
A plurality of pins, it is arranged at this upper surface of this pliability dielectric layer, and wherein the inner of those pins more extends in this wafer area of coverage;
One welding resisting layer, this upper surface that it is formed at this pliability dielectric layer covers those pins with the part; And
One strengthening layer, it is formed at this lower surface of this pliability dielectric layer, and correspondence is arranged at this wafer area of coverage.
2, the package base with wafer covered with thin membrane that prevents deformation of thin membrane according to claim 1 is characterized in that wherein said strengthening layer and this welding resisting layer are to be identical material.
3, the package base with wafer covered with thin membrane that prevents deformation of thin membrane according to claim 1 is characterized in that wherein said welding resisting layer has rectangular without exception perforate, and it is corresponding to this wafer area of coverage.
4, the package base with wafer covered with thin membrane that prevents deformation of thin membrane according to claim 3, the area coverage that it is characterized in that wherein said strengthening layer are this perforates greater than this welding resisting layer.
5, the package base with wafer covered with thin membrane that prevents deformation of thin membrane according to claim 1 is characterized in that wherein said strengthening layer is made up of a plurality of finishing strips.
6, the package base with wafer covered with thin membrane that prevents deformation of thin membrane according to claim 5, it is characterized in that wherein said those finishing strips be roughly parallel to this welding resisting layer perforate than minor face.
7, a kind of package base with wafer covered with thin membrane that prevents deformation of thin membrane is characterized in that it comprises:
One pliability dielectric layer, it has a upper surface and a lower surface, and wherein this upper surface is that definition has a wafer area of coverage;
A plurality of pins, it is this upper surface that is arranged at this pliability dielectric layer, wherein the inner of those pins more extends in this wafer area of coverage;
One welding resisting layer, this upper surface that it is formed at this pliability dielectric layer covers those pins with the part; And
One strengthening layer, it is formed at this lower surface of this pliability dielectric layer, and corresponding this wafer area of coverage zone in addition that is arranged at.
8, the package base with wafer covered with thin membrane that prevents deformation of thin membrane according to claim 7 is characterized in that wherein said strengthening layer has a perforate, and it is corresponding and is a bit larger tham this wafer area of coverage.
9, the package base with wafer covered with thin membrane that prevents deformation of thin membrane according to claim 7 is characterized in that wherein said strengthening layer has a plurality of finishing strips, and it is the outer end of corresponding those pins.
10, the package base with wafer covered with thin membrane that prevents deformation of thin membrane according to claim 7 is characterized in that wherein said strengthening layer is to be covered in this lower surface of this pliability dielectric layer corresponding to the remaining surface beyond this wafer area of coverage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100902689A CN101290921A (en) | 2007-04-17 | 2007-04-17 | Package base with wafer covered with thin membrane preventing deformation of thin membrane |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100902689A CN101290921A (en) | 2007-04-17 | 2007-04-17 | Package base with wafer covered with thin membrane preventing deformation of thin membrane |
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| Publication Number | Publication Date |
|---|---|
| CN101290921A true CN101290921A (en) | 2008-10-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100902689A Pending CN101290921A (en) | 2007-04-17 | 2007-04-17 | Package base with wafer covered with thin membrane preventing deformation of thin membrane |
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| CN (1) | CN101290921A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103837946A (en) * | 2012-11-20 | 2014-06-04 | 富士通株式会社 | Optical module and fabrication method |
| CN106920779A (en) * | 2017-03-09 | 2017-07-04 | 三星半导体(中国)研究开发有限公司 | The combining structure of flexible semiconductor packaging part and its transportation resources |
| CN107492525A (en) * | 2016-06-10 | 2017-12-19 | 三星显示有限公司 | Chip package and include the display device of chip package on the film on film |
| CN112992843A (en) * | 2019-12-12 | 2021-06-18 | 南茂科技股份有限公司 | Thin film flip chip packaging structure and manufacturing method thereof |
| WO2023004790A1 (en) * | 2021-07-30 | 2023-02-02 | 华为技术有限公司 | Optical chip and manufacturing method therefor, and electronic device |
-
2007
- 2007-04-17 CN CNA2007100902689A patent/CN101290921A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103837946A (en) * | 2012-11-20 | 2014-06-04 | 富士通株式会社 | Optical module and fabrication method |
| CN103837946B (en) * | 2012-11-20 | 2015-11-18 | 富士通株式会社 | Optical module and manufacture method |
| CN107492525A (en) * | 2016-06-10 | 2017-12-19 | 三星显示有限公司 | Chip package and include the display device of chip package on the film on film |
| CN106920779A (en) * | 2017-03-09 | 2017-07-04 | 三星半导体(中国)研究开发有限公司 | The combining structure of flexible semiconductor packaging part and its transportation resources |
| US10453671B2 (en) | 2017-03-09 | 2019-10-22 | Samsung Electronics Co., Ltd. | Combined structure of flexible semiconductor device package and method of transporting the flexible semiconductor device |
| CN112992843A (en) * | 2019-12-12 | 2021-06-18 | 南茂科技股份有限公司 | Thin film flip chip packaging structure and manufacturing method thereof |
| CN112992843B (en) * | 2019-12-12 | 2022-09-13 | 南茂科技股份有限公司 | Thin film flip chip packaging structure and manufacturing method thereof |
| WO2023004790A1 (en) * | 2021-07-30 | 2023-02-02 | 华为技术有限公司 | Optical chip and manufacturing method therefor, and electronic device |
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