CN201229937Y - Flip chip encapsulation construction having non-array projection - Google Patents
Flip chip encapsulation construction having non-array projection Download PDFInfo
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- CN201229937Y CN201229937Y CN 200820127602 CN200820127602U CN201229937Y CN 201229937 Y CN201229937 Y CN 201229937Y CN 200820127602 CN200820127602 CN 200820127602 CN 200820127602 U CN200820127602 U CN 200820127602U CN 201229937 Y CN201229937 Y CN 201229937Y
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- packaging structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The utility model relates to a flip-chip packaging structure with non-array bumps, which mainly comprises a substrate with joint pads, a chip arranged on the substrate, spacing adhesion pieces and a seal adhesive used for sealing the chip. In the embodiment, the spacing adhesion piece comprises a spacing ball and adhesive; the bumps of the chip is arranged in non-array and is jointed to the joint pads; the spacing adhesion pieces are arranged between the substrate and the chip and are used to support the periphery of the active surface of the chip, thereby the chip can parallel the substrate so as to avoid the oblique problem of the chip during flip-chip welding and sealing and improve the quality of the flip-chip sealing structure.
Description
Technical field
The utility model is particularly to a kind of flip chip packaging structure with non-array projection relevant for a kind of semiconductor device.
Background technology
At present, can divide into upside-down mounting welding (Flip Chip Bond) and wire bond (Wire Bond) two big classes in semiconductor package inside in the past by chip to the electric connection mode of substrate.Wire bond be with the chip active surface up the form of (away from substrate) be arranged at substrate, and make chip be electrically connected to substrate by bonding wire, chip can be to be non-array configurations for the electrode (or being called weld pad) of wire bonds, for example is positioned at the neighboring area or the middle section of chip active surface.The employed chip of known window-type ball grid array (wBGA) encapsulating structure just has the electrode that is positioned at chip active surface central authorities.On the other hand, upside-down mounting welding is at the chip active surface projection to be set in advance, is arranged at substrate with the form of chip active surface upset (towards substrate), and is electrically connected to substrate by projection.Because projection provides a kind of short electrical connection path between chip and the substrate, can make in the chip integrated circuit of high workload frequency more have the transmission quality of good high-frequency signal.Therefore, the upside-down mounting welding is the inevitable development trend of advanced semiconductor devices, and the chip that operating frequency is more and more high can not be subject to the encapsulation bottleneck of wire length and can try to achieve processing speed and higher usefulness faster.
In the flip chip bonding termination process, projection must be array configurations, and good supporting causes the chip tilt problem otherwise chip can't obtain evenly.Therefore, even the electrical functionality of chip is identical, memory for example, but different according to the purposes of wire bond and upside-down mounting welding, chip just can be different.In other words, the chip of known wire bond can't carry out the upside-down mounting welding, and the chip of common known upside-down mounting welding need weigh distributed lines (RDL) technology in addition, also can be for metal bearing (UBM pad) under the projection that projection is set to produce array configurations.Yet in the transfer process of wire bond to upside-down mounting welding, the chip that the someone attempts continuing to use known wire bond is made as the encapsulation form of upside-down mounting welding, promptly has the flip chip packaging structure of non-array projection, so that chip has shared property.If can adopt the chip of wire bond, the time that then can omit heavy distributed lines (RDL) technology with material cost, shorten the research and development of products time, have the potentiality of reduction manufacturing cost.
See also shown in Figure 1ly, a kind of known flip chip packaging structure 100 with non-array projection comprises chip 120, adhesive body 150 and two or more external terminals 170 of substrate 110, wire bond.This substrate 110 has upper surface 111, lower surface 112 and two or more are formed on the joint sheet 113 of this upper surface 111.This chip 120 is arranged at this upper surface 111 of this substrate 110 and has the tie lines projection (Stud Bump) 122 that two or more routings form, this projection 122 is non-array configurations and is engaged to this joint sheet 113 in stud bump welding (SBB, Stud Bump Bonding) mode.For example working as this chip 120 was the application that is applicable to the window-type ball grid array encapsulation originally, 122 middle sections that are positioned at this chip 120 of this projection.These adhesive body 150 pressing molds are formed on this upper surface 111 of this substrate 110 and seal this chip 120.This external terminal 170 is arranged at this lower surface 112 of this substrate 110.See also shown in Figure 2ly, the manufacture method of this flip chip packaging structure 100 comprises following steps: step 1 provides substrate; Step 2, the upside-down mounting welding; Step 3, sealing; And step 4, external terminal is set.In step 2, these chip 120 no strong points only are engaged to this joint sheet 113 of this substrate 110 with this projection 122 of these chip 120 middle sections, the depth of parallelism and the gap of uncontrollable this chip 120 and this substrate 110.In the step 3 of " sealing ", the mould flowing pressure that forms this adhesive body 150 impacts this chip 120 and the situation (as shown in Figure 1) that is easy to take place swing up and down as seesaw, cause this chip 120 to tilt to press the circuit or the fracture of the solder joint of this projection 122 of touching this substrate 110, and then influence electrically connect quality.And in step 3, this chip 120 that lacks perimeter support power also is subjected to the influence of mould stream easily and produces inclination.This external terminal 170 then is to be provided with in step 4.
The utility model content
In view of this, main purpose of the present utility model is to provide a kind of flip chip packaging structure with non-array projection, the depth of parallelism and gap between energy control chip and the substrate, and avoid chip to tilt and the fracture of projection solder joint.
The purpose of this utility model and solve its technical problem and realize by the following technical solutions.According to a kind of flip chip packaging structure of the present utility model, mainly comprise substrate, chip, two or more interval sticker part and adhesive bodies with non-array projection.This substrate has upper surface and lower surface, and this upper surface is formed with two or more joint sheets.This chip is arranged at this upper surface of this substrate, and the active surface of this chip is provided with two or more projections, and wherein this projection is non-array setting and is engaged to this joint sheet.This interval sticker part is arranged at this upper surface of this substrate and is located between this substrate and this chip with Jie, in order to the periphery of this active surface of supporting this chip.This adhesive body is formed at this upper surface of this substrate and seals this chip.
The purpose of this utility model and solve its technical problem also can be applied to the following technical measures to achieve further.
In aforementioned flip chip packaging structure, this interval sticker part can by two or more separating balls and more than two sections or two sections the adhesion glue formed, this adhesion glue is arranged at this upper surface of this substrate and adheres to this separating ball.
In aforementioned flip chip packaging structure, this substrate can have two or more circuits, and it is formed at this upper surface of this substrate, and this separating ball can directly not press to this circuit.
In aforementioned flip chip packaging structure, can comprise underfill in addition, fill up gap between this substrate and this chip to seal this projection.
In aforementioned flip chip packaging structure, this underfill can cover this active surface of this circuit and this chip of adhering.
In aforementioned flip chip packaging structure, this projection can be the tie lines projection, this this chip of separating ball inadhesion, only in order to control the depth of parallelism and the gap between this chip and this substrate, when this chip is engaged to this substrate in stud bump welding (SBB) mode, this chip shakes slip in the plane parallel with its active surface.
In aforementioned flip chip packaging structure, this interval sticker part can be electrical insulating property viscose glue body.
In aforementioned flip chip packaging structure, this adhesive body can cover this circuit.
In aforementioned flip chip packaging structure, this interval sticker part can have the soft surface characteristic.
In aforementioned flip chip packaging structure, this interval sticker part can away from and do not contact this projection.
In aforementioned flip chip packaging structure, can comprise two or more external terminals in addition, it is arranged at this lower surface of this substrate.
In aforementioned flip chip packaging structure, this chip can be the medium-high frequency memory chip of striding the encapsulation form, and it is selected from second generation Double Date Rate Synchronous Dynamic Random Access Memory (DDR2 DRAM) chip of 533MHz to 1600MHz.
As can be seen from the above technical solutions, the flip chip packaging structure with non-array projection of the present utility model has following advantage and effect:
One, utilizes the support force that the position can provide the chip periphery that is provided with of separating ball or interval sticker part, make in the process of upside-down mounting welding or/and sealing and do not have the problem that chip tilts.Therefore, the chip of wire bond has shared property, can continue to use and is packaged into the flip chip packaging structure with non-array projection.
Two, by gluing on substrate or the at interval soft surface characteristic of sticker part of separating ball that connects of adhesion, to guarantee support effect.So only the depth of parallelism and the gap between control chip and the substrate makes chip can do the upside-down mounting welding that stud bump welding (SBB) mode is carried out in the concussion slip of XY plane, has the quality of the flip chip packaging structure of non-array projection with raising.
Three, utilize the interval sticker part to have the characteristic of electrical insulating property, can avoid causing electrical short circuit phenomenon.
Four,, can avoid circuit to be squeezed and impaired because separating ball does not directly press down the circuit of substrate.
Five, insert the flip-chip gap by underfill or adhesive body,, make substrate not need to form in addition welding resisting layer, so as to reducing manufacturing cost to cover circuit and to have the effect of protection circuit.
Description of drawings
Fig. 1 is known schematic cross-section with flip chip packaging structure of non-array projection;
Fig. 2 is known manufacture method flow diagram with flip chip packaging structure of non-array projection;
Fig. 3 is a kind of schematic diagram with flip chip packaging structure of non-array projection according to first specific embodiment of the present utility model;
Fig. 4 is the assembly schematic diagram of this flip chip packaging structure in manufacturing process according to first specific embodiment of the present utility model;
Fig. 5 has the schematic diagram of the flip chip packaging structure of non-array projection for the another kind according to second specific embodiment of the present utility model;
Fig. 6 is the manufacturing flow chart according to this flip chip packaging structure of second specific embodiment of the present utility model.
Description of reference numerals
S2 gap, S1 gap
1 provides substrate 2 upside-down mountings welding
3 sealings 4 are provided with external terminal
10 dispensing needle heads, 20 dispensing needle heads
30 dispensing needle heads, 100 flip chip packaging structures
110 substrates, 111 upper surfaces
112 lower surfaces, 113 joint sheets
120 chips, 122 projections
150 adhesive bodies, 170 external terminals
200 flip chip packaging structures, 210 substrates
211 upper surfaces, 212 lower surfaces
213 joint sheets, 214 circuits
220 chips, 221 active surfaces
222 projections, 230 separating balls
240 adhesion glue, 250 adhesive bodies
260 underfills, 270 external terminals
300 flip chip packaging structures, 310 substrates
311 upper surfaces, 312 lower surfaces
313 joint sheets, 314 circuits
320 chips, 321 active surfaces
322 projections 340 are sticker part at interval
350 adhesive bodies, 370 external terminals
Embodiment
According to first specific embodiment of the present utility model, a kind of flip chip packaging structure with non-array projection is illustrated in the schematic diagram of Fig. 3.Fig. 4 is the assembly schematic diagram of this flip chip packaging structure in manufacturing process.
This flip chip packaging structure 200 mainly comprises substrate 210, chip 220, two or more interval sticker part and adhesive bodies 250.This at interval sticker part formed by two or more separating balls 230 and the glue 240 of adhering more than two sections or two sections.This substrate 210 has upper surface 211 and lower surface 212, and this upper surface 211 is formed with two or more joint sheets 213.This substrate 210 can be printed circuit board (PCB), ceramic substrate or glass substrate.In the present embodiment, this joint sheet 213 can straight line or the arrangement mode of many parallel lines be arranged at the middle section (shown in the A figure among Fig. 4) of this upper surface 211.
See also shown in Figure 3ly, this chip 220 is arranged at this upper surface 211 of this substrate 210.This chip 220 can be memory chip, and more particularly, this chip 220 can be second generation Double Date Rate (DDR2) memory chip or third generation Double Date Rate (DDR3) memory chip.And the active surface 221 of this chip 220 is provided with two or more projections 222, and wherein this projection 222 is non-array setting and is engaged to this joint sheet 213." non-array setting " refers to not to be arrange according to the matrix-style that the N line number multiply by the M columns, and wherein N and M are the positive integers greater than two, and the projection setting area is much smaller than this active surface 221 of this chip 220, at least should be below 1/2nd.In other words, this projection 222 is not by the dispersion adjustment of reshuffling circuit (RDL) technology, and concentrates on a certain zone of chip active surface.In the present embodiment, this projection 222 can be positioned at the middle section of this active surface 221 and can be linear array, wherein this projection 222 and this joint sheet 213 mutual corresponding (shown in the B figure among Fig. 4).This projection 222 can be the composite projection of golden projection, copper bump or other conductive material.In the present embodiment, this projection 222 is the tie lines projection (StudBump) of routing formation, and is engaged to this joint sheet 213 in stud bump welding (SBB) mode.More particularly, stud bump welding (SBB) makes between this projection 222 and this joint sheet 213 generation ultrasonic oscillation rub formed golden gold bonding or other metal bonding.Wherein, ultrasonic oscillation is that (promptly being the plane parallel with chip active surface 221) does back and forth little fast moving on the XY plane, to reach the low-temperature metal bonding.And preferably, reciprocal little moving direction should be vertical with the linear array direction of this projection 222, engages to avoid this projection 222 to produce short circuit in the ultrasonic oscillation process.A concrete effect in the utility model is to utilize the marriage relation of this separating ball 230 and this adhesion glue 240 to control the depth of parallelism and gap between this chip 220 and this substrate 210, can reach the upside-down mounting welding of stud bump welding (SBB) mode again to keep the chip support effect, the reasons are as follows two sections described.
See also shown in Figure 3ly, this separating ball 230 is arranged at this upper surface 211 of this substrate 210, is located between this substrate 210 and this chip 220 with Jie, and this separating ball 230 supports the periphery of this active surface 221 of these chips 220.By such combination, in the upside-down mounting welding step, the active surface 221 of this chip 220 by these separating ball 230 adhesions, can not done the slip of XY planar ultrasonic wave concussion.Specifically, this separating ball 230 is away from the periphery of this active surface 221 of this projection 222 of this chip 220 and contiguous this chip 220, so that slidably support effect of preferable chip to be provided.More particularly, the sphere diameter of this separating ball 230 can be not more than the height of this projection 222 of this chip 220, to guarantee the bonding between this chip 220 and this substrate 210.See also shown in Figure 3ly, the sphere diameter of this separating ball 230 approximates the vertical range of this active surface 221 of this chip 220 to this upper surface 211 of this substrate 210 greatly in order to define the gap S1 between this substrate 210 and this chip 220.Wherein, this separating ball 230 should have identical sphere diameter.
See also shown in Figure 3ly, this adhesion glue 240 is arranged at this upper surface 211 of this substrate 210 and adheres to this separating ball 230.Therefore, this adhesion glue 240 produces displacement in order to this separating ball 230 is limited in this upper surface 211 of this substrate 210 to avoid this separating ball 230.In the present embodiment, this active surface 221 of not bonding this chip 220 of this adhesion glue 240.The curing of this adhesion glue 240 makes this separating ball 230 can firmly be arranged on this substrate 210, and the curing of the glue 240 of should adhering can be carried out after the upside-down mounting welding step, so that this separating ball 230 can be in order to define above-mentioned upside-down mounting welded gaps S1, and, even this adhesion glue 240 attaches this active surface 221 to this chip 220, this chip 220 of still can not adhering before uncured is so that this chip 220 can be made the ultrasonic oscillation on XY plane in the upside-down mounting welding step.Preferably, this adhesion glue 240 is away from this joint sheet 213 of this substrate 210, to avoid polluting this joint sheet 213.In the present embodiment, the material of this adhesion glue 240 can be epoxy resin (Epoxy).
In the present embodiment, see also shown in Figure 3ly, this substrate 210 can have two or more circuit 214, and it is formed at this upper surface 211 of this substrate 210.Preferably, shown in the A figure among Fig. 4, this separating ball 230 can directly not press to this circuit 214, and is impaired so can avoid stress that this circuit 214 is squeezed, and then the electrical quality of transmission of influence.In the present embodiment, see also shown in Figure 3ly, this circuit 214 can be same line layer with this joint sheet 213.In the present embodiment, this circuit 214 can be bare wire design, can not covered by welding resisting layer, and this is because this chip 220 has the good depth of parallelism and flip chip bonding seam crack accurately under the support of this separating ball 230 and between this substrate 210.
See also shown in Figure 3ly, this adhesive body 250 is formed at this upper surface 211 of this substrate 210 and seals this chip 220, suitable packaging protection is provided and can prevents dust pollution.This adhesive body 250 can be pressing mold or claims that the technology of transfer formation (Transfer Molding) is formed.
In the present embodiment, see also shown in Figure 3, this flip chip packaging structure 200 can comprise underfill 260 in addition, and it fills up gap S1 between this substrate 210 and this chip 220 to seal this projection 222, makes its fracture to avoid stress concentration at specific projection 222 places.This underfill 260 can cover the active surface 221 of this circuit 214 and the chip 220 of adhering.Specifically, these underfill 260 salable glue 240 of should adhering, wherein this underfill 260 also covers the local side to this chip 220, helps to fix this chip 220 to avoid this chip 220 displacements.Because this gap S1 can precisely be controlled at a fixed value, thus utilize this underfill 260 of capillarity can successfully fill up this gap S1, can built-in bubble.
In the present embodiment, see also shown in Figure 3, this flip chip packaging structure 200 can comprise two or more external terminals 270 in addition, it is arranged at this lower surface 212 of this substrate 210, but to be provided as input and/or output so that these flip chip packaging structure 200 surface engagement to external device, for example printed circuit board (PCB) (not drawing among the figure).This external terminal 270 can be soldered ball, tin cream, metal contact pad or contact pin.
Therefore, the position being set preferable support effect can be provided for the periphery of this chip 220 by this separating ball 230 and this adhesion glue 240, make when upside-down mounting is welded, can make this chip 220 reach balance and can not produce and swing up and down, and when sealing, can avoid this chip 220 influenced by the mould flowing pressure and produce inclination, so this flip chip packaging structure 200 does not have the problem that chip tilts, and more can guarantee the electric connection quality between this chip 220 and this substrate 210.And these adhesion glue 240 bonding these separating balls 230 are so can prevent to cause the problem that can't effectively support this chip 220 because of this separating ball 230 produces displacement.Can utilize this underfill 260 to make this chip 220 can more firmly be arranged on this substrate 210 in addition, be subjected to the influence of mould flowing pressure to produce, more can avoid stress to concentrate the problem that causes the fracture of projection 222 solder joints to avoid this chip 220.In addition, this underfill 260 covers this circuit 214, just can reach the effect of this circuit 214 of protection, so this substrate 210 does not need to form in addition welding resisting layer, to save manufacturing cost.
The utility model further specifies the manufacture method of the flip chip packaging structure 200 of aforementioned non-array projection, is illustrated in the assembly schematic diagram in the manufacturing process of Fig. 4.
At first, see also shown in the A figure among Fig. 4, this substrate 210 is provided, it has this joint sheet 213, utilizes dispensing technology to be coated in this upper surface 211 by dispensing needle head 10 glue 240 partial points of should adhering, and covers on this circuit 214 with the part.And at this upper surface 211 of this substrate 210 and this separating ball 230 is set in the applying area of this adhesion glue 240, wherein this separating ball 230 does not directly press to this circuit 214 and this separating ball 230 away from this joint sheet 213.This adhesion glue 240 adheres to this separating ball 230, in order to avoid this separating ball 230 displacements.
Then, carry out the upside-down mounting welding step.See also shown in the B figure among Fig. 4, this chip 220 is arranged on this substrate 210 in the mode of this active surface 221 towards this upper surface 211, and this projection 222 that makes this chip 220 is engaged to this joint sheet 213 (as shown in Figure 3), to reach the electrical interconnects of this chip 220 and this substrate 210.Wherein, this projection 222 can be the tie lines projection, and the juncture of this projection 222 and this joint sheet 213 can be stud bump welding (SBB, Stud Bump Bonding).In the flip chip bonding termination process, provide Z axle (vertically) support force of these chip 220 peripheries by this separating ball 230, produce (as shown in Figure 3) to avoid this chip 220, but do not limit of the slippage of this chip 220 at XY plane (horizontal plane).
Then see also shown in the C figure among Fig. 4,260 of this underfills that utilize dispensing needle head 20 will have high fluidity are coated in this upper surface 211 of this substrate 210.This underfill 260 is scrawled earlier at the side of this chip 220 or L shaped dual-side, and fills up gap S1 between this chip 220 and this substrate 210 with capillarity, to seal this projection 222 (as shown in Figure 3).
See also below shown in the D figure among Fig. 4, this underfill 260 of baking-curing is so that this underfill 260 fills up the gap S1 (as shown in Figure 3) between this substrate 210 and this chip 220.See also shown in the D figure among Fig. 4, this underfill 260 can cover the local side to this chip 220, just can fix this chip 220 on this substrate 210 after this underfill 260 solidifies.Wherein, after the upside-down mounting welding step, the curing of this adhesion glue 240 can be carried out simultaneously with the curing of this underfill 260, perhaps can be before these underfill 260 spot printings form.
Afterwards, see also shown in the E figure among Fig. 4, this adhesive body 250 is formed on this substrate 210,, do not polluted (as shown in Figure 3) by extraneous dust and aqueous vapor so as to protecting this chip 220 to seal this chip 220 with stamping method.At last, see also shown in the F figure among Fig. 4, this external terminal 270 this lower surface 212 in this substrate 210 is set, wherein this external terminal 270 is an arrayed.In the present embodiment, this external terminal 270 comprises soldered ball.
Therefore, the utility model can increase the shared property of the chip 220 of wire bond, particularly originally be applicable to the wire bond chip of window-type ball grid array, can continue to use and be packaged into flip chip packaging structure 200, do not have the problem that chip tilts and the projection solder joint ruptures with non-array projection.The chip of wire bond does not need to reshuffle metal bearing under circuit (RDL) technology and the projection (UBM pad), and same class chip has the convenience that technology is adjusted.At second generation Double Date Rate Synchronous Dynamic Random Access Memory (DDR2 DRAM, Double-Data-Rate Two Synchronous Dynamic Random Access Memory) in the concrete application of semiconductor packages, the wafer that comprises two or more chips does not need to be made as in advance wire bond or upside-down mounting Type of Welding, but can test earlier to determine the operand store frequency of chip, and after the wafer cutting, but classify according to the operand store frequency.But computing is become the window-type ball grid array encapsulating structure in the DDR2 of 553MHz, 667MHz, 800MHz memory chip package; But computing is become the flip chip packaging structure with non-array projection of the present utility model in the DDR2 of 1066MHz, 1333MHz, 1600MHz memory chip package.The application process of DDR3 memory chip also is same as described above.Therefore, the memory frequency chip of different classification sections can selectivity be packaged into suitable encapsulation form, do not have the chip that low memory frequency chip but is made for the array projection, cause to be encapsulated as the encapsulating structure of window-type ball grid array encapsulating structure or lower frequency computing; Do not have high memory frequency chip yet and still be the chip of wire bond, cause to be packaged into window-type ball grid array encapsulating structure, reduce inapplicable number of chips and the effect that increases process flexibility so the value on the dark tool industry also obviously has in the low frequency computing.
According to second specific embodiment of the present utility model, the flip chip packaging structure that another kind has a non-array projection is illustrated in the schematic diagram of Fig. 5.This flip chip packaging structure 300 mainly comprises substrate 310, chip 320, two or more interval sticker part 340 and adhesive bodies 350.This substrate 310 has upper surface 311 and lower surface 312, and this upper surface 311 is provided with two or more joint sheets 313.In the present embodiment, this joint sheet 313 can be positioned at the middle section of this upper surface 311.See also shown in Figure 5ly, this chip 320 is arranged at this upper surface 311 of this substrate 310, and the active surface 321 of this chip 320 is provided with two or more projections 322, and wherein this projection 322 is for non-array setting and be engaged to this joint sheet 313.In the present embodiment, this projection 322 can be golden projection, for example, and the tie lines projection that routing forms.This projection 322 to the joint method of this joint sheet 313 can utilize stud bump welding (SBB) or tin cream welding.This chip 320 can be memory chip, refers in particular to a kind of medium-high frequency memory chip of striding the encapsulation form, for example by second generation Double Date Rate Synchronous Dynamic Random Access Memory (DDR2 DRAM) chip of 533MHz to 1600MHz.
Please consult shown in Figure 5ly again, this interval sticker part 340 is arranged at this upper surface 311 of this substrate 310 and is located between this substrate 310 and this chip 320 with Jie, this at interval sticker part 340 adhere to the periphery of this active surface 321 of these chips 320.This interval sticker part 340 can away from and do not contact this projection 322.This interval sticker part 340 can be the electrical insulating property resin, to avoid causing electrical short circuit phenomenon.In the present embodiment, this interval sticker part 340 can be two sides adhesive tape or B rank adhesion blob of viscose, thus this active surface 321 that can bonding this chip 320 and this upper surface 311 of this substrate 310, so that this chip 320 is fixedly arranged on this substrate 310.Preferably, this interval sticker part 340 has the soft surface characteristic.That is to say that this interval sticker part 340 is low modulus in order to the material that adheres to this chip 320, the ultrasonic oscillation that makes this chip 220 can do XY plane (horizontal plane) when the upside-down mounting welding step slides or fine setting.
See also shown in Figure 5ly, this adhesive body 350 is formed at this upper surface 311 of this substrate 310 and seals this chip 320, and this adhesive body 350 fills up gap S2 between this substrate 310 and this chip 320 to seal this projection 322.In the present embodiment, this substrate 310 can have two or more circuit 314, and it is formed at this upper surface 311 of this substrate 310.Preferably, this adhesive body 350 can cover this circuit 314, is polluted to avoid this circuit 314, so this substrate 310 does not need to form in addition welding resisting layer so as to reducing manufacturing cost.Please consult shown in Figure 5ly again, this flip chip packaging structure 300 can comprise two or more external terminals 370 in addition, and this lower surface 312 that it is arranged at this substrate 310 engages for outer surface.
Therefore, by this interval sticker part 340, in the process of upside-down mounting welding or/and sealing, this interval sticker part 340 is provided the support force of these chip 320 peripheries, avoids this chip 320 to produce the problem of inclination and the 322 generation solder joint fractures of this projection whereby.
The manufacture method that the utility model further specifies the flip chip packaging structure of aforementioned non-array projection is illustrated in the flow chart of Fig. 6.
At first, see also shown in the A figure among Fig. 6, this substrate 310 with this joint sheet 313 is provided, and utilizes dispensing technology will these interval sticker part 340 partial points to be coated in this upper surface 311 of this substrate 310 by dispensing needle head 30, wherein at interval sticker part 340 away from this joint sheet 313.Sticker part 340 can local this circuit 314 that covers this substrate 310 at interval for this.Since this at interval sticker part 340 be electrical insulating property, so even this circuit 314 can not cause electrical problem of short-circuit for bare wire yet.
Then, see also shown in the B figure among Fig. 6, carry out the upside-down mounting welding step, this active surface 321 with this chip 320 is arranged on this substrate 310 towards the mode of this substrate 310, and this projection 322 that makes this chip 320 is engaged to this corresponding joint sheet 313 (as shown in Figure 5), to reach the electrical interconnects of this chip 320 and this substrate 310.In flip-chip process, the periphery of this chip 320 can be by this interval sticker part 340 power that is supported, so do not have the problem (as shown in Figure 5) that chip tilts.
Then, see also shown in the C figure among Fig. 6, toast this interval sticker part 340,, and provide the peripheral preferable support and the fixed effect of this chip 320 in the follow-up mould envelope technology so that this interval sticker part 340 solidifies with this substrate 310 and this chip 320 of adhering.
Afterwards, see also shown in the D figure among Fig. 6, be formed on this adhesive body 350 on this substrate 310 and fill up gap S2 between this substrate 310 and this chip 320 with stamping method, to seal this chip 320 and this projection 322 (as shown in Figure 5).At last, see also shown in the E figure among Fig. 6, this external terminal 370 is arranged at this lower surface 312 of this substrate 310.
The above, it only is preferred embodiment of the present utility model, be not that the utility model is done any pro forma restriction, though the utility model discloses as above with preferred embodiment, yet be not that any those of ordinary skill in the art are not in breaking away from claims scope of the present utility model in order to qualification the utility model, any simple modification of being done, equivalence change and modify, and all are covered by in the technical scope of the present utility model.
Claims (12)
1, a kind of flip chip packaging structure with non-array projection is characterized in that, comprises:
Substrate has upper surface and lower surface, and this upper surface is provided with two or more joint sheets;
Chip is arranged at this upper surface of this substrate, and the active surface of this chip is provided with two or more projections, and wherein this projection is non-array setting and is engaged to this joint sheet;
Two or more are arranged at this upper surface of this substrate and are situated between and be located between this substrate and this chip in order to the interval sticker part of the active surface periphery of supporting chip; And
Adhesive body is formed at this upper surface of this substrate and seals this chip.
2, the flip chip packaging structure with non-array projection according to claim 1, it is characterized in that, described interval sticker part by two or more separating balls and more than two sections or two sections the adhesion glue formed, this adhesion glue is arranged at the described upper surface of described substrate and adheres to this separating ball.
3, the flip chip packaging structure with non-array projection according to claim 2, it is characterized in that, described substrate has two or more circuit, and it is formed at the described upper surface of described substrate, and described separating ball does not directly press to this circuit.
4, the flip chip packaging structure with non-array projection according to claim 1 is characterized in that, described flip chip packaging structure comprises underfill in addition, and it fills up the gap between described substrate and the described chip and seals described projection.
5, the flip chip packaging structure with non-array projection according to claim 3, it is characterized in that, described flip chip packaging structure comprises underfill in addition, it fills up the gap between described substrate and the described chip and seals described projection, and described underfill covers the described active surface of the described circuit and the described chip of adhering.
6, the flip chip packaging structure with non-array projection according to claim 2, it is characterized in that, described projection is the tie lines projection, this chip of separating ball inadhesion in the depth of parallelism between described control chip and the substrate and gap, when described chip is engaged to described substrate with the stud bump welding manner, described chip shakes slip in the plane parallel with its active surface.
7, the flip chip packaging structure with non-array projection according to claim 1 is characterized in that, described interval sticker part is an electrical insulating property viscose glue body.
8, according to claim 1 or 7 described flip chip packaging structures with non-array projection, it is characterized in that described substrate has two or more circuit, described adhesive body covers described circuit.
9, the flip chip packaging structure with non-array projection according to claim 7 is characterized in that, described interval sticker part is the interval sticker part of soft surface.
10, the flip chip packaging structure with non-array projection according to claim 1 is characterized in that, described interval sticker part away from and do not contact described projection.
11, the flip chip packaging structure with non-array projection according to claim 1 is characterized in that, described flip chip packaging structure comprises two or more external terminals in addition, and it is arranged at the described lower surface of described substrate.
12, the flip chip packaging structure with non-array projection according to claim 1, it is characterized in that, described chip is the medium-high frequency memory chip of striding the encapsulation form, and it is selected from the second generation Double Date Rate Synchronous Dynamic Random Access Memory chip of 533MHz to 1600MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200820127602 CN201229937Y (en) | 2008-07-15 | 2008-07-15 | Flip chip encapsulation construction having non-array projection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200820127602 CN201229937Y (en) | 2008-07-15 | 2008-07-15 | Flip chip encapsulation construction having non-array projection |
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| Publication Number | Publication Date |
|---|---|
| CN201229937Y true CN201229937Y (en) | 2009-04-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200820127602 Expired - Fee Related CN201229937Y (en) | 2008-07-15 | 2008-07-15 | Flip chip encapsulation construction having non-array projection |
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| CN (1) | CN201229937Y (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237283A (en) * | 2010-04-27 | 2011-11-09 | 华东科技股份有限公司 | Flip-chip bonding method and flip-chip bonding construction of non-array bumps |
| CN102290394A (en) * | 2010-06-15 | 2011-12-21 | 南茂科技股份有限公司 | Heat radiating electronic package structure and method of manufacturing the same |
| CN104517931A (en) * | 2014-07-11 | 2015-04-15 | 株洲南车时代电气股份有限公司 | Structure and method for increasing power electronic packaging weld layer uniformity |
| CN109560068A (en) * | 2017-09-25 | 2019-04-02 | 力成科技股份有限公司 | Encapsulating structure and chip structure |
-
2008
- 2008-07-15 CN CN 200820127602 patent/CN201229937Y/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237283A (en) * | 2010-04-27 | 2011-11-09 | 华东科技股份有限公司 | Flip-chip bonding method and flip-chip bonding construction of non-array bumps |
| CN102237283B (en) * | 2010-04-27 | 2013-06-12 | 华东科技股份有限公司 | Flip-chip bonding method and flip-chip bonding construction of non-array bumps |
| CN102290394A (en) * | 2010-06-15 | 2011-12-21 | 南茂科技股份有限公司 | Heat radiating electronic package structure and method of manufacturing the same |
| CN102290394B (en) * | 2010-06-15 | 2014-05-07 | 南茂科技股份有限公司 | Heat radiating electronic package structure and method of manufacturing the same |
| CN104517931A (en) * | 2014-07-11 | 2015-04-15 | 株洲南车时代电气股份有限公司 | Structure and method for increasing power electronic packaging weld layer uniformity |
| CN104517931B (en) * | 2014-07-11 | 2016-06-01 | 株洲南车时代电气股份有限公司 | Improve structure and the method thereof of welding layer homogeneity in power electronics package |
| CN109560068A (en) * | 2017-09-25 | 2019-04-02 | 力成科技股份有限公司 | Encapsulating structure and chip structure |
| US10607860B2 (en) | 2017-09-25 | 2020-03-31 | Powertech Technology Inc. | Package structure and chip structure |
| CN109560068B (en) * | 2017-09-25 | 2020-05-19 | 力成科技股份有限公司 | Packaging structure and chip structure |
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