CN100449744C - Integrated circuit packaging structure with pin on the chip and its chip supporting member - Google Patents
Integrated circuit packaging structure with pin on the chip and its chip supporting member Download PDFInfo
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- CN100449744C CN100449744C CNB2005100933921A CN200510093392A CN100449744C CN 100449744 C CN100449744 C CN 100449744C CN B2005100933921 A CNB2005100933921 A CN B2005100933921A CN 200510093392 A CN200510093392 A CN 200510093392A CN 100449744 C CN100449744 C CN 100449744C
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- 238000004806 packaging method and process Methods 0.000 title description 13
- 238000012856 packing Methods 0.000 claims abstract description 47
- 239000000853 adhesive Substances 0.000 claims abstract description 31
- 230000001070 adhesive effect Effects 0.000 claims abstract description 31
- 239000002390 adhesive tape Substances 0.000 claims description 110
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 230000009977 dual effect Effects 0.000 abstract 2
- 239000002313 adhesive film Substances 0.000 abstract 1
- 238000004880 explosion Methods 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 1
- 241000218202 Coptis Species 0.000 description 15
- 235000002991 Coptis groenlandica Nutrition 0.000 description 15
- 238000005538 encapsulation Methods 0.000 description 13
- 230000009286 beneficial effect Effects 0.000 description 6
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- 238000013461 design Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000002950 deficient Effects 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 210000000481 breast Anatomy 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 210000002683 foot Anatomy 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Abstract
The invention relates to an integrated circuit packing structure whose pin is above the chip, and relative chip carrier. Wherein, it comprises a chip, dual cams, a wire support with dual pins, at least one adhesive crystal band and a packing adhesive; said band is special conductive adhesive film is bar shape, to adhesive and electrically connect the pin of wire support and the chip; therefore, it can avoid wire impact and gold wire explosion caused by traditional connection, and avoid dispersing solder (or cam) on the wire support, to improve the package yield.
Description
Technical field
The present invention relates to a kind of IC circuit packing structure, particularly relates to a kind of can the solution and breasts the tape and reveal pin IC circuit packing structure and the chip bearing member thereof on chip of the pin of gold thread at (LOC) on the chip.
Background technology
At present in integrated circuit (IC) encapsulation, with LOC (Lead-On-Chip, pin is on chip) lead frame (is wafer as the IC chip, below all be called chip) carrying, chipless rim in the lead frame (die pad) design, directly make the bonding and electric connection chip of pin of lead frame, advantage with low-cost package, and can meet the encapsulation of general high frequency chip, usually DDR 400 following memory body chips still can adopt the LOC lead frame to encapsulate, and chip is to be pasted on the pin of LOC lead frame and to electrically connect with gold thread.Utilize above-mentioned packaged type can obtain TSOP (Thin Small OutlinePackage, thin-type small-size encapsulation) or the packaging structure of TQFP (Thin Quad Flat Package, slim quad flat package).Along with the raising of the speed and the complexity of chip, existing traditional TSOP or TQFP encapsulation be the overstocked shortcoming of breasting the tape (wire-sweeping) and revealing gold thread that then is easy to generate if gold thread distributes.In addition, also can be because of the thickness of gold thread and apart from the restriction on causing electrically, high-frequency signals postpones and the problem of interference as producing.
Seeing also shown in Figure 1ly, is a kind of IC circuit packing structure of existing known use LOC lead frame.This IC circuit packing structure 1 mainly includes the pin 20 of a chip 10 and a LOC lead frame.Be to be pasted with a plurality of sticking brilliant adhesive tapes 30 earlier below the pin 20 of this LOC lead frame, existing known sticking brilliant adhesive tape 30 is the PI (polyimide for tool two sides viscosity, polyimides) adhesive tape, and utilizing those to glue an active surface 11 of brilliant adhesive tape 30 adhering chips 10, this chip 10 disposes a plurality of weld pads 12 on active surface 11.Gold thread 40 with routing formation connects the top of those weld pads 12 to those pins 20 again, this chip 10 is constituted with those pins 20 electrically connect, and form an adhesive body 50, to seal the inner of this chip 10, those gold threads 40 and those pins 20.But in the process of encapsulation, the injecting glue pressure (filling pressure) that pressing mold forms adhesive body 50 can make those gold threads 40 produce skew, breasts the tape and the defective of revealing gold thread and cause producing causing.
The TaiWan, China patent announcement has disclosed a kind of " semiconductor chip crystal-coated package structure " for No. 567598, and it is that configuration is provided with a plurality of projections on the weld pad of a chip, and utilizes the mode of chip bonding, and those projections are connected to the lead foot of a lead frame.Because those projections are for soldered ball (solder ball), have a reflow step when chip bonding, to be soldered to those lead foots.But those projections can melt under reflow temperature, and then diffusion and polluting at other position of those lead foots, cause chip to fall in (collapse) and projection ruptures easily.
This shows that above-mentioned existing integrated circuits packaging structure obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem that IC circuit packing structure exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that above-mentioned existing integrated circuits packaging structure exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of found a kind of novel pin on chip IC circuit packing structure and and chip bearing member, can improve general existing integrated circuits packaging structure, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
Main purpose of the present invention is, overcome the defective that the existing integrated circuits packaging structure exists, and provide a kind of novel IC circuit packing structure of pin on chip, technical problem to be solved is to make it can solve existing known breasting the tape and the shortcoming of revealing gold thread, and scolder (or projection) spreads on the lead frame pin can avoid existing known projection reflow the time, make the Chip Packaging acceptance rate improve, thereby the industry that is suitable for is more used.
Another object of the present invention is to, overcome the defective that the existing integrated circuits packaging structure exists, and provide a kind of novel IC circuit packing structure of pin on chip, technical problem to be solved is to make it be pasted with one first sticking brilliant adhesive tape and one second sticking brilliant adhesive tape on a plurality of pins of a lead frame, be beneficial to an adhesive body and fill up this first sticking brilliant adhesive tape and this second space of gluing between the brilliant adhesive tape, and can reduce the generation of bubble, thereby be suitable for practicality more.
A further object of the present invention is, a kind of IC circuit packing structure is provided, technical problem to be solved is to make it reach the multi-chip package type attitude, when carrying out face-to-face chip bonding up and down, lead frame can replace known projection reflow step, and can avoid scolder (or projection) on the lead frame pin, to spread, thereby the Chip Packaging acceptance rate is improved, thereby the industry that is suitable for is more used.
An also purpose of the present invention is, a kind of chip bearing member is provided, technical problem to be solved is it can be save have known routing bonding wire now and can avoid diffusion or the chip of reflow projection on lead frame to fall in (collapse), thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to the IC circuit packing structure of a kind of pin on chip that the present invention proposes, it comprises: a chip, and it has an active surface and a plurality of weld pad on this active surface; A plurality of projections, it is arranged on those weld pads of this chip; One lead frame, it has a plurality of pins; At least one first sticking brilliant adhesive tape, it is attached at those pins, with this active surface of bonding this chip; And an adhesive body, it seals the part of this first sticking brilliant adhesive tape and those pins; Wherein, this first sticking brilliant adhesive tape is the anisotropic conductive film (ACF strip) for generally being strip, and those projections are that this first sticking brilliant adhesive tape is sunk in embedding, by this first sticking brilliant adhesive tape anisotropy conduction to those corresponding pins.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The integrated circuit encapsulation structure of aforesaid pin on chip, also include one second sticking brilliant adhesive tape, it is also for generally being the anisotropic conductive film (ACF) of strip, this second sticking brilliant adhesive tape is to be attached at those pins and to be parallel to this first sticking brilliant adhesive tape, and this adhesive body is the space of filling up between this first sticking brilliant adhesive tape and this second sticking brilliant adhesive tape.
The integrated circuit encapsulation structure of aforesaid pin on chip, wherein said projection has a flat top surface, and the melting point metal of those projections is the curing temperatures that are higher than this first sticking brilliant adhesive tape.
The integrated circuit encapsulation structure of aforesaid pin on chip, wherein said lead frame is the LOC lead frame that lacks chip bearing (die pad), and this first sticking brilliant adhesive tape is vertically to connecting those pins.
The object of the invention to solve the technical problems also adopts following technical scheme to realize.According to a kind of IC circuit packing structure that the present invention proposes, it comprises: a plurality of projection chips, each projection chip have an active surface and a plurality of projection that is arranged on this active surface; One lead frame, it has a plurality of pins; A plurality of sticking brilliant adhesive tapes, it is attached at a upper surface and a lower surface of those pins of this lead frame, with the active surface of bonding those projection chips; And an adhesive body, it is the part of those sticking brilliant adhesive tapes of sealing and those pins; Wherein, those sticking brilliant adhesive tapes are the anisotropic conductive films (ACF strip) for generally being strip, and those projections are that those sticking brilliant adhesive tapes are sunk in embedding, by those extremely corresponding pins of those sticking brilliant adhesive tape anisotropy conductions.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid IC circuit packing structure, wherein said sticking brilliant adhesive tape is to be arranged in parallel.
Aforesaid IC circuit packing structure, it also includes at least one routing chip, and it is back-to-back one of them the back side of those projection chips that is arranged at.
Aforesaid IC circuit packing structure, wherein said projection has a flat top surface, and the melting point metal of those projections is the curing temperatures that are higher than those sticking brilliant adhesive tapes.
Aforesaid IC circuit packing structure, wherein said sticking brilliant adhesive tape are vertically to connecting those pins.
In addition, in order to achieve the above object, the present invention also provides a kind of chip bearing member, and it comprises: one lacks the LOC lead frame of chip bearing (die pad), and it has the pin of a plurality of metal materials; And at least one sticking brilliant adhesive tape, it is attached at those pins, and in order to the active surface of a bonding chip, and this sticking brilliant adhesive tape is the anisotropic conductive film (ACF strip) for generally being strip.
The present invention compared with prior art has tangible advantage and beneficial effect.Via as can be known above-mentioned, according to the IC circuit packing structure of a kind of pin on chip that the present invention proposes, it comprises that mainly a chip, a plurality of projection, have the lead frame of a plurality of pins, at least one first a sticking brilliant adhesive tape and the adhesive body.This chip has an active surface and a plurality of weld pad on this active surface.Those projections are arranged on those weld pads of this chip.This first sticking brilliant adhesive tape is those pins that are attached at this lead frame, with this active surface of bonding this chip.This adhesive body seals the part of this sticking brilliant adhesive tape and those pins.Wherein, this first sticking brilliant adhesive tape is the anisotropic conductive film (ACF strip) for generally being strip, and those projections are that this first sticking brilliant adhesive tape is sunk in embedding, by this first sticking brilliant adhesive tape anisotropy conduction to those corresponding pins.
By technique scheme, IC circuit packing structure and the chip bearing member thereof of pin of the present invention on chip has following advantage at least:
The IC circuit packing structure of pin of the present invention on chip, it is to attach to be provided with a sticking brilliant adhesive tape on a plurality of pins of a lead frame, it is for generally being the anisotropic conductive film (ACF strip) of strip, and a plurality of projections on the chip are that this sticking brilliant adhesive tape is sunk in embedding, conduct electricity the active surface of this chip upper protruding block by this sticking brilliant adhesive tape anisotropy to those pins and bonding this chip, and can solve existing known breasting the tape and the shortcoming of revealing gold thread, and scolder (or projection) spreads on the lead frame pin can avoid existing known projection reflow the time, make the Chip Packaging acceptance rate improve, thereby the industry that is suitable for is more used.
The IC circuit packing structure of pin of the present invention on chip, be on a plurality of pins of a lead frame, to be pasted with one first sticking brilliant adhesive tape and one second sticking brilliant adhesive tape, it is the anisotropic conductive film that generally is strip, and be parallel to each other, be beneficial to an adhesive body and fill up this first sticking brilliant adhesive tape and this second space of gluing between the brilliant adhesive tape, and can reduce the generation of bubble, thereby be suitable for practicality more.
IC circuit packing structure of the present invention is a plurality of pins that mainly comprise a plurality of projection chips, a lead frame, a plurality of sticking brilliant adhesive tape and an adhesive body.Wherein, those sticking brilliant adhesive tapes are the anisotropic conductive films (ACF strip) for generally being strip, those projections are that those sticking brilliant adhesive tapes are sunk in embedding, and by those sticking brilliant adhesive tape anisotropy conductions those pins to correspondence, reach the multi-chip package type attitude, so it is known when lead frame carries out face-to-face chip bonding up and down, can replace known projection reflow step, and can avoid scolder (or projection) on the lead frame pin, to spread, thereby the Chip Packaging acceptance rate is improved, thereby the industry that is suitable for is more used.
Chip bearing member of the present invention, be on the metal material pin of a LOC lead frame, to be pasted with at least one sticking brilliant adhesive tape, this sticking brilliant adhesive tape is the anisotropic conductive film (ACF strip) for generally being strip, connect a chip for bonding and anisotropy conduction, and can save existing known routing bonding wire and can avoid diffusion or the chip of reflow projection on lead frame to fall in (collapse), thereby be suitable for practicality more.
In sum, the invention relates to IC circuit packing structure and the chip bearing member thereof of a kind of pin on chip.The IC circuit packing structure of this pin on chip, comprise that mainly a chip, a plurality of projection, have the lead frame of a plurality of pins, at least one sticking brilliant adhesive tape and an adhesive body, should sticking brilliant adhesive tape be for generally being the anisotropic conductive film of strip, facilitate the bonding of lead frame pin and chip and electrically connect, thus can solve tradition with the routing joint connected mode was produced breasts the tape and reveal the shortcoming of gold thread.It has above-mentioned many advantages and practical value, and in like product, do not see have similar structural design to publish or use and really genus innovation, no matter it all has bigger improvement on product structure or function, have large improvement technically, and produced handy and practical effect, and have the multinomial effect of enhancement than the existing integrated circuits packaging structure, thus be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 existing traditional makes the pin of lead frame and the schematic cross-section of the IC circuit packing structure that chip is finished electric connection with the routing juncture.
Fig. 2 is according to first specific embodiment of the present invention, is a kind of schematic cross-section that utilizes the sticking brilliant adhesive tape that attaches on the lead frame pin to finish the IC circuit packing structure of electric connection.
Fig. 3 is according to first specific embodiment of the present invention, is the top view of sticking brilliant adhesive tape on the chip active surface of this IC circuit packing structure.
Fig. 4 is according to second specific embodiment of the present invention, is the schematic cross-section of another kind of IC circuit packing structure.
1: IC circuit packing structure 10: chip
11: active surface 12: weld pad
20: pin 30: sticking brilliant adhesive tape
40: gold thread 50: adhesive body
10: IC circuit packing structure 110: chip
111: active surface 112: the back side
113: weld pad 120: projection
121: flat top surface 130: pin
131: upper surface 132: lower surface
142: the second sticking brilliant adhesive tapes of 141: the first sticking brilliant adhesive tapes
143: space 150: adhesive body
200: 210: the first projection chips of IC circuit packing structure
211: active surface 212: the back side
213: weld pad 214: projection
220: the second projection chips 221: projection
230: pin 231: upper surface
232: lower surface 240: sticking brilliant adhesive tape
250: the first routing chips 251: active surface
252: the back side 253: weld pad
261: adhesion coating 262: bonding wire
270: the second routing chips 281: adhesion coating
282: bonding wire 290: adhesive body
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to IC circuit packing structure and chip bearing member its embodiment, structure, feature and the effect thereof of pin on chip that foundation the present invention proposes, describe in detail as after.
See also shown in Figure 2, be according to first specific embodiment of the present invention, this IC circuit packing structure 100 mainly includes a chip 110, a plurality of projection 120, a plurality of pins 130 of a lead frame, an at least one sticking brilliant adhesive tape 141,142 and adhesive body 150 that is attached at this lead frame on this chip 110.This chip 110 has an active surface 111 and a back side 112, and has a plurality of weld pads 113 on this active surface 111.Those projections 120 are arranged on those weld pads 113.Those projections 120 are to should be the projection with reflow, for example golden projection, copper bump or aluminium projection or the like.And preferable, each projection 120 should have a flat top surface 121, is beneficial to press touch the anisotropy conducting particles.In a concrete structure,, be beneficial to engage those projections 120 producing projection lower metal layer (UBM) (not shown) earlier below those projections 120 and on those weld pads 113.
Usually this lead frame is the lead frame for a kind of shortage chip bearing (die pad).Each pin 130 of this lead frame has a upper surface 131 and a lower surface 132.In addition, in the present embodiment, this first sticking brilliant adhesive tape 141 is the lower surfaces 132 that are attached at those pins 130 with this second sticking brilliant adhesive tape 142.This first sticking brilliant adhesive tape 141 (or this second sticking brilliant adhesive tape 142) is to be lateral cross with those pins 130 that attached, and its standing part position is in convergence the inner of same row's pin 130, and in order to the active surface 111 of bonding this chip 110.This first sticking brilliant adhesive tape 141 and the second sticking brilliant adhesive tape 142 are to be the anisotropic conductive film (ACF strip) that generally is strip, and it contains particle diameter uniform conductive particle.Preferable, this the first sticking brilliant adhesive tape 141 and the second sticking brilliant adhesive tape 142 are for being parallel to each other, between this first sticking brilliant adhesive tape 141 and the second sticking brilliant adhesive tape 142 is to be reserved with an equidistant space 143, being beneficial to adhesive body 150 is filled between this first sticking brilliant adhesive tape 141 and the second sticking brilliant adhesive tape 142, to reduce the generation of bubble.
In addition, those projections 120 should be made up of refractory metal, and the melting point metal of those projections 120 should be higher than the curing temperature of the first sticking brilliant adhesive tape 141 and the second sticking brilliant adhesive tape 142.Therefore, see also shown in Figure 3, when this chip 110 of chip bonding and those pins 130, those projections 120 are to keep the cardinal principle of projection shape constant, and embedding is sunk in this first sticking brilliant adhesive tape 141 and this second sticking brilliant adhesive tape 142, press the conducting particles that touches the first sticking brilliant adhesive tape 141 and second sticking brilliant adhesive tape 142 inside with its flat top surface 121, be electrically connected to corresponding pin 130 by conducting particles again.So this first sticking brilliant adhesive tape 141 and second effect of gluing brilliant adhesive tape 142 are except the active surface 111 of those pins 130 of part that can be fixed in same row, adhering chip 110, more can the anisotropy conduction connect this chip 110, save the gold thread that existing known routing forms to suitable pin 130.At last, can use compression molding techniques to form adhesive body 150, this adhesive body 150 is sealing first sticking brilliant adhesive tape 141, second sticking brilliant adhesive tape 142, the part of those pins 130 and active surfaces 111 of chip 110.In the present embodiment, this adhesive body 150 is more to cover chip 110 to seal chip 110 fully.And in a kind of concrete encapsulation kenel of present embodiment, the position that those pins 130 are sealed by adhesive body 150 is to can be interior pin, and the outer pin position of those pins 130 is that the side by adhesive body 150 extends, for externally electrically engaging.In different encapsulation kenels, the upper surface 131 of those pins 130 maybe can be revealed in adhesive body 150, does not externally electrically engage there to be outer pin kenel.
Therefore, in above-mentioned IC circuit packing structure 100, it is the first sticking brilliant adhesive tape 141 and the second sticking brilliant adhesive tape 142 that biadhesive PI (insulation) adhesive tape on the existing known LOC of the being attached at lead frame is replaced as strip and has the anisotropy conducting function, with as a kind of new chip bearing member, can solve existing traditional with routing engage connected mode was produced breasts the tape and reveal the shortcoming of gold thread, and have and improve the advantage of electrically transmitting.Those projections 120 also can not be diffused in other position of those pins 130 with dissolving.Another tangible effect is to use lead frame cheaply to encapsulate the high frequency chip of a new generation, and can enlarge the scope that lead frame can be used in Chip Packaging.
In addition, IC circuit packing structure of the present invention is the encapsulation field that can be used in the multicore sheet.See also shown in Figure 4ly, in second specific embodiment of the present invention, this IC circuit packing structure 200 mainly includes a plurality of pins 230 of a plurality of projection chips 210,220, a lead frame, a plurality of sticking brilliant adhesive tape 240 and an adhesive body 290.Wherein, each pin 230 is to have a upper surface 231 and a lower surface 232.Those sticking brilliant adhesive tapes 240 are the anisotropic conductive films (ACF strip) for strip, can be formed at the upper surface 231 and lower surface 232 of those pins 230 of part of same row respectively, the function of have that pin is fixed, die bonding and anisotropy conducting electricity.Glue the down auxiliary of brilliant adhesive tapes 240 at those in addition, one first projection chip 210 is chip bonding lower surfaces 232 in those pins 230; One second projection chip 220 is chip bonding upper surfaces 231 in those pins 230.This first projection chip 210 has an active surface 211, a back side 212 and a plurality of position weld pad 213 at this active surface 211, and those weld pads 213 are provided with a plurality of projections 214.Similarly, this second projection chip 220 also is provided with the projection 221 of a plurality of positions at its active surface.By those sticking brilliant adhesive tapes 240 respectively the active surface 211 of the first projection chip 210 is adhered to those pins 230 lower surface 232, the active surface 211 of the second projection chip 220 is adhered to the upper surface 231 of those pins 230, and projection 214 to those pins 230 and anisotropy conduction that the anisotropy conduction connects the first projection chip 210 connect the projection 221 of this second projection chip 220 to those pins 230.So save the member of existing known bonding wire, can not have the problem of breasting the tape, and can exempt existing known scolder or projection diffuse pollution problem on the pin of lead frame with naked wire.In addition, in the present embodiment, this IC circuit packing structure 200 includes one first routing chip 250 in addition, this first routing chip 250 has an active surface 251, a back side 252, and a plurality of weld pads 253 are to be formed on this active surface 251, the back side 252 of this first routing chip 250 is the back-to-back back side 212 that is arranged at the first projection chip 210 by an adhesion coating 261, and electrically connects the lower surface 232 of those weld pads 253 of this first routing chip 250 to those pins 230 with a plurality of bonding wires 262.Same, can with one second routing chip 270 by an adhesion coating 281 the back-to-back back side that is arranged at the second projection chip 220 and electrically connect the upper surface 231 of the second routing chips 270 and those pins 230 with a plurality of bonding wires 282.At last, those glue the interior pin position of brilliant adhesive tapes 240, the first projection chip 210, the second projection chip 220, the first routing chip 250, the second routing chip 270 and those pins 230 with adhesive body 290 sealings again, encapsulate kenel and reach multilayer chiop, so can not cause the raising of encapsulation complexity, also can not elongate encapsulation cycle time or cause acceptance rate to reduce.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the structure that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (8)
1, the IC circuit packing structure of a kind of pin on chip is characterized in that it comprises:
One chip, it has an active surface and a plurality of weld pad on this active surface;
A plurality of projections, it is arranged on those weld pads of this chip;
One lead frame, it has a plurality of pins;
At least one first sticking brilliant adhesive tape, it is to be attached at those pins, with this active surface of bonding this chip; And
One adhesive body, it seals the part of this first sticking brilliant adhesive tape and those pins;
Wherein, this first sticking brilliant adhesive tape is for generally being the anisotropic conductive film of strip, and those projections are that this first sticking brilliant adhesive tape is sunk in embedding, by this first sticking brilliant adhesive tape anisotropy conduction to those corresponding pins;
Described IC circuit packing structure also comprises one second sticking brilliant adhesive tape, it is for generally being the anisotropic conductive film of strip, this second sticking brilliant adhesive tape is to be attached at those pins and to be parallel to this first sticking brilliant adhesive tape, and this adhesive body is the space of filling up between this first sticking brilliant adhesive tape and this second sticking brilliant adhesive tape.
2, the IC circuit packing structure of pin according to claim 1 on chip is characterized in that wherein said projection has a flat top surface, and the melting point metal of those projections is higher than the curing temperature of this first sticking brilliant adhesive tape.
3, the IC circuit packing structure of pin according to claim 1 on chip it is characterized in that wherein said lead frame is the LOC lead frame of a shortage chip bearing, and this first sticking brilliant adhesive tape is vertically to connecting those pins.
4, a kind of IC circuit packing structure is characterized in that it comprises:
A plurality of projection chips, each projection chip have an active surface and a plurality of projection that is arranged on this active surface;
One lead frame, it has a plurality of pins;
A plurality of sticking brilliant adhesive tapes, it is attached at a upper surface and a lower surface of those pins of this lead frame, with the active surface of bonding those projection chips; And
One adhesive body, it is the part of those sticking brilliant adhesive tapes of sealing and those pins;
Wherein, those sticking brilliant adhesive tapes are for generally being strip and parallel each other anisotropic conductive film, those projections are that those sticking brilliant adhesive tapes are sunk in embedding, by those sticking brilliant adhesive tape anisotropy conductions those pins to correspondence, this adhesive body fills up the space between space between those pins and those the sticking brilliant adhesive tapes, to seal those sticking brilliant adhesive tapes fully.
5, IC circuit packing structure according to claim 4 is characterized in that wherein said sticking brilliant adhesive tape is to be arranged in parallel.
6, IC circuit packing structure according to claim 4 is characterized in that it also includes at least one routing chip, and it is back-to-back one of them the back side of those projection chips that is arranged at.
7, IC circuit packing structure according to claim 4 is characterized in that wherein said projection has a flat top surface, and the melting point metal of those projections is higher than the curing temperature of those sticking brilliant adhesive tapes.
8, IC circuit packing structure according to claim 4 is characterized in that wherein said sticking brilliant adhesive tape is vertically to connecting those pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100933921A CN100449744C (en) | 2005-08-23 | 2005-08-23 | Integrated circuit packaging structure with pin on the chip and its chip supporting member |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100933921A CN100449744C (en) | 2005-08-23 | 2005-08-23 | Integrated circuit packaging structure with pin on the chip and its chip supporting member |
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| Publication Number | Publication Date |
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| CN1921099A CN1921099A (en) | 2007-02-28 |
| CN100449744C true CN100449744C (en) | 2009-01-07 |
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| CNB2005100933921A Expired - Fee Related CN100449744C (en) | 2005-08-23 | 2005-08-23 | Integrated circuit packaging structure with pin on the chip and its chip supporting member |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20090045491A1 (en) * | 2007-08-15 | 2009-02-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and leadframe thereof |
| CN101527292B (en) * | 2008-03-04 | 2012-09-26 | 南茂科技股份有限公司 | Chip packaging structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5641996A (en) * | 1995-01-30 | 1997-06-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit package, semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging |
| US5918113A (en) * | 1996-07-19 | 1999-06-29 | Shinko Electric Industries Co., Ltd. | Process for producing a semiconductor device using anisotropic conductive adhesive |
| US20020142518A1 (en) * | 2001-01-24 | 2002-10-03 | Yi-Chuan Ding | Chip scale package and manufacturing method |
| US20020182778A1 (en) * | 2001-05-29 | 2002-12-05 | Pei-Wei Wang | Flexible package fabrication method |
| CN1531089A (en) * | 2003-03-18 | 2004-09-22 | 精工爱普生株式会社 | Semiconductor device, electronic apparatus and their manufacturing methods, elecronic equipment |
-
2005
- 2005-08-23 CN CNB2005100933921A patent/CN100449744C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5641996A (en) * | 1995-01-30 | 1997-06-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit package, semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging |
| US5918113A (en) * | 1996-07-19 | 1999-06-29 | Shinko Electric Industries Co., Ltd. | Process for producing a semiconductor device using anisotropic conductive adhesive |
| US20020142518A1 (en) * | 2001-01-24 | 2002-10-03 | Yi-Chuan Ding | Chip scale package and manufacturing method |
| US20020182778A1 (en) * | 2001-05-29 | 2002-12-05 | Pei-Wei Wang | Flexible package fabrication method |
| CN1531089A (en) * | 2003-03-18 | 2004-09-22 | 精工爱普生株式会社 | Semiconductor device, electronic apparatus and their manufacturing methods, elecronic equipment |
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| CN1921099A (en) | 2007-02-28 |
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